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Relevant bibliographies by topics / Hardware based encryption

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Academic literature on the topic 'Hardware based encryption'

Author: Grafiati

Published: 4 June 2025

Last updated: 8 July 2025

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Journal articles on the topic "Hardware based encryption"

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Huang, Xing Li, and Huan Chun Yang. "Two-Way ID Authentication and Hardware Encryption-Based Security Design of Mobile Hard Disk." Applied Mechanics and Materials 58-60 (June 2011): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.573.

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The design of the "two-way ID authentication and hardware encryption-based secure mobile hard disk" adopts the smart card-based technology of two way ID authentication, thus enables higher authentication strength than ordinary password authentication and USB-KEY one way certification; adoption of dedicated hardware encryption chip on encrypting the hard disk data enhances the encryption speed; since this encryption is a hardware level encryption, it is completely transparent to users, and do not rely on the operating system or other applications, with almost no impact on system performance; that the key of the encryption system will be loaded before the system initialization (system boot) prevents malicious code attacks from hard drive, and even when the mobile hard disk was stolen, the thief cannot read out any encrypted data from it on any other computer as long as the thief has no access to the encryption key. Therefore, this "encrypted mobile hard disk" is more secure with better reading and writing performance, and thus can effectively protect sensitive data on the mobile hard disk.

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Kanda, Guard, and Kwangki Ryoo. "Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design." Webology 19, no. 1 (2022): 4581–96. http://dx.doi.org/10.14704/web/v19i1/web19304.

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At present, there are several pieces of research on designing and implementing new cryptographic algorithms that are lightweight and resistant to several, if not major forms of security attacks. However, some algorithms such as the International Data Encryption Algorithm (IDEA), which has been around for some time is yet to record any real threat against its functionality. To ensure its continued usage, current implementations rely on multiphase encryption where it is combined with other algorithms such as ROTation (ROT) and Data Encryption Standard (DES) for maximum security strength. Multiphase encryption implies that there is a tendency for an increase in hardware area and a reduction in overall speed. In such cases, having fast and reduced area algorithms are much desired. This paper, therefore, proposes an efficient hardware implementation of the IDEA cipher that is based on arithmetic modulo multiplication—one of the main computations of the IDEA—on a novel Vedic multiplier architecture. The increase in efficiency of the IDEA crypto architecture and the reduction in resources utilization is achieved through an enhancement of its structural architecture to utilize a fixed set of resources for all eight identical rounds of computation and the use of a proposed fast and lightweight Vedic hardware multiplier. The proposed hardware modification and resulting architecture are designed using the Xilinx ISE and Vivado tools. The architecture is synthesized using Precision Synthesis Tool (PS) and simulated using Modelsim SE 10.6d and ISIM simulation tools. The proposed IDEA cipher is 100% more efficient when designed based on the Vedic multiplier compared to existing designs. The hardware architecture is implemented on Spartan-6-FGG484 Field Programmable Gate Array (FPGA) using Verilog HDL. Verified results show that the proposed Vedic-based IDEA occupied 212 Slices with the Vedic multiplier only occupying 28 Slices out of the total 212. The proposed architecture operates at a maximum frequency of 253.3 MHz.

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Lee, Jaehyeok, Phap Ngoc Duong, and Hanho Lee. "Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption." Sensors 23, no. 17 (2023): 7389. http://dx.doi.org/10.3390/s23177389.

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With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent. Homomorphic encryption (HE) provides a promising solution by not only preserving data privacy but also enabling meaningful computations on encrypted data; while considerable efforts have been devoted to accelerating expensive homomorphic evaluation in the cloud, little attention has been paid to optimizing encryption and decryption (ENC-DEC) operations on the edge. In this paper, we propose efficient hardware architectures for CKKS-based ENC-DEC accelerators to facilitate computations on the client side. The proposed architectures are configurable to support a wide range of polynomial sizes with multiplicative depths (up to 30 levels) at a 128-bit security guarantee. We evaluate the hardware designs on the Xilinx XCU250 FPGA platform and achieve an average encryption time 23.7× faster than that of the well-known SEAL HE library. By reducing time complexity and improving the hardware utilization of cryptographic algorithms, our configurable CKKS-supported ENC-DEC hardware designs have the potential to greatly accelerate cryptographic processes on the client side in the post-quantum era.

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PAPAEFSTATHIOU, IOANNIS. "LOW LEVEL HARDWARE COMPRESSION FOR MULTI-GIGABIT NETWORKS." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1307–19. http://dx.doi.org/10.1142/s0218126604001969.

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As it has already been proved, link layer compression is very effective when used in packet networks. In particular, packet compression is especially useful when encryption is applied to the network packets. Encrypting the packets causes the data to be random in nature, and thus no compression can be applied after it. It is believed that low level encryption will be applied to the vast majority of Internet Protocol (IP) networks in the near future, and thus a large number of very sophisticated encryption devices have already been manufactured. Based on these facts, we claim that hardware devices that can compress network streams at link speed (and perform the compression just before the encryption), will also be widely used in the future networks. In this paper, we present such a hardware compressor/decompressor core that can work at speeds up to 10 Gb/s, it is fairly inexpensive and can very easily be plugged into an existing network node without causing any side effects. We additionally examine the performance against complexity tradeoffs of such compressor/decompressor devices. Finally, it is claimed that compression devices with throughput ranging from 0.5 to 10 Gb/s can be efficiently implemented based on the reference architecture.

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B, Lakshmi, Kirubakaran E, and Prabakar T.N. "FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION." ICTACT Journal on Communication Technology 01, no. 03 (2010): 150–56. http://dx.doi.org/10.21917/ijct.2010.0022.

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Xiao Bao-Jin, Tong Hai-Li, Zhang Jian-Zhong, Zhang Chao-Xia, and Wang Yun-Cai. "Spread spectrum communication based on hardware encryption." Acta Physica Sinica 60, no. 8 (2011): 080506. http://dx.doi.org/10.7498/aps.60.080506.

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Huang, Birong, Zhansheng Hou, Peng Lin, and Fei Zhou. "Implementation Method Of Remote Assistance Instruction Based On Hardware Secure Encryption." Journal of Physics: Conference Series 2136, no. 1 (2021): 012031. http://dx.doi.org/10.1088/1742-6596/2136/1/012031.

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Abstract As a public service enterprise related to energy security and national economy and people’s livelihood, the safe work is related to all walks of life and thousands of households. In power scenarios, the remote cooperative guidance needs to ensure the security of data communication. The implementation method of remote cooperative guidance in power scenarios based on hardware security encryption realizes the functions of terminal registration, user online and offline management, message call, control signaling negotiation, audio and video real-time call, graphic guidance and target tracking and labeling. Configuration TF card encryption at the mobile terminal chip and video server configuration high speed encryption card, WIFI / 4 g wireless networks to establish encryption channel, remote collaborative guidance terminal power scene registration messages, messages, call, and by guiding and structured data security encryption transmission, the unstructured data such as audio stream and video stream is encrypted. It not only realizes the secure encryption of message communication, but also guarantees the high-speed transmission of audio and video streams.

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Li, Jiakun, Yixuan Luo, Fei Wang, and Wei Gao. "Design and Implementation of Real-Time Image Acquisition Chip Based on Triple-Hybrid Encryption System." Electronics 11, no. 18 (2022): 2925. http://dx.doi.org/10.3390/electronics11182925.

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With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 μm2. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm2.

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Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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张, 晓强. "Image Encryption Algorithm Based on the Hardware Platform." Journal of Image and Signal Processing 08, no. 02 (2019): 98–102. http://dx.doi.org/10.12677/jisp.2019.82014.

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Dissertations / Theses on the topic "Hardware based encryption"

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Sampath, Sowrirajan. "FPGA based Hardware Implementation of Advanced Encryption Standard." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189835736.

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Athreya, Manoj B. "Subverting Linux on-the-fly using hardware virtualization technology." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/34844.

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In this thesis, we address the problem faced by modern operating systems due to the exploitation of Hardware-Assisted Full-Virtualization technology by attackers. Virtualization technology has been of growing importance these days. With the help of such a technology, multiple operating systems can be run on a single piece of hardware, with little or no modification to the operating system. Both Intel and AMD have contributed to x86 full-virtualization through their respective instruction set architectures. Hardware virtualization extensions can be found in almost all x86 processors these days. Hardware virtualization technologies have opened a whole new frontier for a new kind of attack. A system hacker can abuse hardware virualization technology to gain control over an operating system on-the-fly (i.e., without a system restart) by installing a thin Virtual Machine Monitor (VMM) below the native operating system. Such a VMM based malware is termed a Hardware-Assisted Virtual Machine (HVM) rootkit. We discuss the technique used by a rootkit named Blue Pill to subvert the Windows Vista operating system by exploiting the AMD-V (codenamed "Pacifica") virtualization extensions. HVM rootkits do not hook any operating system code or data regions; hence detecting the existence of such malware using conventional techniques becomes extremely difficult. This thesis discusses existing methods to detect such rootkits and their inefficiencies. In this work, we implement a proof-of-concept HVM rootkit using Intel-VT hardware virtualization technology and also discuss how such an attack can be defended against by using an autonomic architecture called SHARK, which was proposed by Vikas et al., in MICRO 2008.

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Gough, Michael Andreas. "Applying Attribute-Based Encryption in Two-Way Radio Talk Groups: A Feasibility Study." BYU ScholarsArchive, 2018. https://scholarsarchive.byu.edu/etd/6836.

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In two-way radio systems, talk groups are used to organize communication. Some situations may call for creating a temporary talk group, but there are no straightforward ways to do this. Making a new talk group requires programming radios off-line. Temporary groups can be created, but this requires inputting radio IDs which is tedious on a radio's limited controls. By describing group members using attributes, ciphertext-policy attribute-based encryption (CP-ABE) can be used to quickly create sub-groups of a talk group. This scheme requires fewer button presses and messages sent in the new talk group are kept secret. CP-ABE can be used on deployed hardware, but performance varies with the type of embedded processor and the number of attributes used. Because radio communication is time-critical, care must be taken not to introduce too much audio delay. By using benchmark programs on a variety of single-board computers, we explore the limits of using CP-ABE on a two-way radio.

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Ibrahim, Mohamad A. "Hardware Realization of Chaos-based Symmetric Video Encryption." Thesis, 2013. http://hdl.handle.net/10754/293352.

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This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

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Barakat, Mohamed L. "Hardware Realization of Chaos Based Symmetric Image Encryption." Thesis, 2012. http://hdl.handle.net/10754/234953.

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This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

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CHANG, CHENG-HSIN, and 張鉦新. "Data Encryption based on Hardware and Software Parameters." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4huf4w.

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碩士<br>東海大學<br>電機工程學系<br>106<br>With the development of technology, electronic devices are used frequently in human beings’ daily lives. A large amount of data is stored in various electronic devices, e.g. personal computer, smart phone, cloud device, etc. However, without encryption, these data and files may be hacked by hackers or leaked out by insiders easily. The loss of important data in the cloud may result in huge personal/business-reputation damages, credit loss, and pecuniary loss. In this paper, we propose a data encryption method based on hardware and software parameters. An environmental key is created by utilizing trusted device’s hardware as well as software parameters. The important files are then encrypted by using the environmental key. In the proposed method, the encrypted files can only be decrypted in the same trusted device. Once the encrypted files are illegal copied to another untrusted device, the files cannot be decrypted since the environmental key is different. According to the experimental result, the proposed method is verified and suitable for important data encryption.

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Lin, Ya-Jheng, and 林亞正. "Hardware Implementations of Image Encryption Based on Chaotic Permutation-Diffusion Scheme." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/42275689096675550219.

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碩士<br>輔仁大學<br>電機工程學系碩士班<br>104<br>Due to some intrinsic features of images such as bulk data capacity and high correlation among pixels, traditional encryption algorithms such as AES and RSA are seldom used to handle image encryption. On the other hand, chaotic permutation-diffusion ciphers receive a lot of attention since they generally need far less computation cost. Most of previous works focus on the design of software algorithms. In this work, we present digital hardware implementation of a chaotic permutation-diffusion cipher, which is a symmetric encryption and allows reusing secret keys. . The typical cat map function is modified for pipeline architecture. Furthermore, loop optimization techniques are applied to reduce the hardware cost. A three-stage pipeline design was successfully implemented and synthesized with TSMC 90 nm technology. It can reach 4892 Mb/s throughput. Furthermore, the security analysis shows that the proposed design has not only high performance but also strong resistance to various attacks.

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FAN, HAO-SHIANG, and 范皓翔. "Hardware Design of Color Image Encryption Based on Chaotic Permutation-diffusion Scheme." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/856h4e.

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碩士<br>輔仁大學<br>電機工程學系碩士班<br>107<br>Due to bulk data capacity of images traditional symmetric or asymmetric encryption algorithms such as AES and RSA are seldom used to handle image encryption. A lot of works based on chaotic permutation-diffusion ciphers have been proposed to encrypt images since they generally need far less computation cost. In this work, we present a color-image cipher with chaotic permutation-diffusion scheme. This work extends a previous work that only deals with gray-level images. Furthermore, pipelined 2-round encryption is implemented. The security analysis shows that the implementation can produce encrypted images with strong resistance to various attacks. The design has been correctly verified with the NC-Verilog Simulator.

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Borges, Guilherme Rosas. "Practical Isolated Searchable Encryption in a Trusted Computing Environment." Master's thesis, 2018. http://hdl.handle.net/10362/59506.

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Cloud computing has become a standard computational paradigm due its numerous advantages, including high availability, elasticity, and ubiquity. Both individual users and companies are adopting more of its services, but not without loss of privacy and control. Outsourcing data and computations to a remote server implies trusting its owners, a problem many end-users are aware. Recent news have proven data stored on Cloud servers is susceptible to leaks from the provider, third-party attackers, or even from government surveillance programs, exposing users’ private data. Different approaches to tackle these problems have surfaced throughout the years. Naïve solutions involve storing data encrypted on the server, decrypting it only on the client-side. Yet, this imposes a high overhead on the client, rendering such schemes impractical. Searchable Symmetric Encryption (SSE) has emerged as a novel research topic in recent years, allowing efficient querying and updating over encrypted datastores in Cloud servers, while retaining privacy guarantees. Still, despite relevant recent advances, existing SSE schemes still make a critical trade-off between efficiency, security, and query expressiveness, thus limiting their adoption as a viable technology, particularly in large-scale scenarios. New technologies providing Isolated Execution Environments (IEEs) may help improve SSE literature. These technologies allow applications to be run remotely with privacy guarantees, in isolation from other, possibly privileged, processes inside the CPU, such as the operating system kernel. Prominent example technologies are Intel SGX and ARM TrustZone, which are being made available in today’s commodity CPUs. In this thesis we study these new trusted hardware technologies in depth, while exploring their application to the problem of searching over encrypted data, primarily focusing in SGX. In more detail, we study the application of IEEs in SSE schemes, improving their efficiency, security, and query expressiveness. We design, implement, and evaluate three new SSE schemes for different query types, namely Boolean queries over text, similarity queries over image datastores, and multimodal queries over text and images. These schemes can support queries combining different media formats simultaneously, envisaging applications such as privacy-enhanced medical diagnosis and management of electronic-healthcare records, or confidential photograph catalogues, running without the danger of privacy breaks in Cloud-based provisioned services.

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Books on the topic "Hardware based encryption"

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Khairallah, Mustafa. Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6344-4.

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Joye, Marc, and Jean-Jacques Quisquater. Cryptographic Hardware and Embedded Systems - CHES 2004 00: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings. Springer-Verlag Berlin Heidelberg, 2004.

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Kaliski, Burton S. Cryptographic Hardware and Embedded Systems - CHES 2002: 4th International Workshop Redwood Shores, CA, USA, August 13 15, 2002 Revised Papers. Springer-Verlag Berlin Heidelberg, 2003.

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Khairallah, Mustafa. Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer, 2022.

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Khairallah, Mustafa. Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore Pte. Limited, 2021.

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Robshaw, Matthew, and Lejla Batina. Cryptographic Hardware and Embedded Systems -- CHES 2014: 16th International Workshop, Busan, South Korea, September 23-26, 2014, Proceedings. Springer London, Limited, 2014.

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Cryptographic Hardware and Embedded Systems -- CHES 2014: 16th International Workshop, Busan, South Korea, September 23-26, 2014, Proceedings. Springer, 2014.

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Book chapters on the topic "Hardware based encryption"

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Sinha Roy, Sujoy, and Ingrid Verbauwhede. "Ring-LWE Public Key Encryption Processor." In Lattice-Based Public-Key Cryptography in Hardware. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9994-8_5.

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Khairallah, Mustafa. "On the Cost of ASIC Hardware Crackers." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_2.

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Khairallah, Mustafa. "Hardware Performance of the $$\Theta $$CB3 Algorithm." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_3.

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Doröz, Yarkın, Erdinç Öztürk, Erkay Savaş, and Berk Sunar. "Accelerating LTV Based Homomorphic Encryption in Reconfigurable Hardware." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-48324-4_10.

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Khairallah, Mustafa. "Analysis of Lightweight BC-Based AEAD." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_5.

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Khairallah, Mustafa. "Arguments for Tweakable Block Cipher-Based Cryptography." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_4.

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Würstlein, Alexander, Michael Gernoth, Johannes Götzfried, and Tilo Müller. "Exzess: Hardware-Based RAM Encryption Against Physical Memory Disclosure." In Architecture of Computing Systems – ARCS 2016. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30695-7_5.

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Bhatotia, Pramod, Markulf Kohlweiss, Lorenzo Martinico, and Yiannis Tselekounis. "Steel: Composable Hardware-Based Stateful and Randomised Functional Encryption." In Public-Key Cryptography – PKC 2021. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-75248-4_25.

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Khairallah, Mustafa. "Remus: Lighweight AEAD from Ideal Ciphers." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_7.

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Khairallah, Mustafa. "Romulus: Lighweight AEAD from Tweakable Block Ciphers." In Hardware Oriented Authenticated Encryption Based on Tweakable Block Ciphers. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-6344-4_6.

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Conference papers on the topic "Hardware based encryption"

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Li, Xiaoguo, Guomin Yang, Tao Xiang, et al. "Make Revocation Cheaper: Hardware-Based Revocable Attribute-Based Encryption." In 2024 IEEE Symposium on Security and Privacy (SP). IEEE, 2024. http://dx.doi.org/10.1109/sp54263.2024.00100.

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Singh, Gurdeep, and Sonam Mittal. "A Study on Hardware-based Implementation of Homomorphic Encryption." In 2025 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE). IEEE, 2025. https://doi.org/10.1109/iitcee64140.2025.10915411.

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Liu, Xuankai, and Bing Li. "Design of a Hybrid Encryption Scheme Based on Software and Hardware Collaboratin." In 2024 9th International Conference on Signal and Image Processing (ICSIP). IEEE, 2024. http://dx.doi.org/10.1109/icsip61881.2024.10671467.

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Adamo, Oluwayomi, and Murali R. Varanasi. "Hardware based encryption for wireless networks." In MILCOM 2010 - 2010 IEEE Military Communications Conference. IEEE, 2010. http://dx.doi.org/10.1109/milcom.2010.5679550.

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Nikhil, N. A., and D. S. Harish Ram. "Hardware implementation of quasigroup based encryption." In 2014 International Conference on Embedded Systems (ICES). IEEE, 2014. http://dx.doi.org/10.1109/embeddedsys.2014.6953050.

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Caroline Akinwonmi, Folasade, Boniface Kayode Alese, Folasade M. Dahunsi, Festus A. Osuolale, and Ayodele E Odo. "Design of Circuit System-Based Cryptography." In InSITE 2015: Informing Science + IT Education Conferences: USA. Informing Science Institute, 2015. http://dx.doi.org/10.28945/2155.

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Cryptography is the science of writing in secret codes which can be achieved either by using software encrypter or hardware encrypter. This study presents the development of a pair of circuit system-based (hardware) cryptographic processor. The hardware encryption in this study was achieved using the bitwise logic operations in the registers of the microcontroller and messages are streamed as serial ASCII data from the PC through the USB port to the microcontroller unit. The encryption is performed on each ASCII representation using a pass key embedded in the microcontroller unit. Decryption process is similar but in the reverse order. A comparative analysis of the encryption time for the hardware-based data encryption was made and findings recorded. The processor was implemented using PIC18F4550 microcontroller mounted on a Printed Circuit Board alongside other components to achieve the hardware based circuitry. The software end of the encryption and decryption algorithm was developed based on a library built into C Language Visual Studio version 2010 and the CCS C compiler for communication protocol stack.

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Giesl, Jiri, Ladislav behal, and Karel Vlcek. "Hardware solution of chaos based image encryption." In 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. IEEE, 2009. http://dx.doi.org/10.1109/ddecs.2009.5012127.

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Harper, S., and P. Athanas. "A security policy based upon hardware encryption." In 37th Annual Hawaii International Conference on System Sciences, 2004. Proceedings of the. IEEE, 2004. http://dx.doi.org/10.1109/hicss.2004.1265453.

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Qawaqneh, Zakariya, Khaled Elleithy, Bandar Alotaibi, and Munif Alotaibi. "A new hardware quantum-based encryption algorithm." In 2014 IEEE Long Island Systems, Applications and Technology Conference (LISAT). IEEE, 2014. http://dx.doi.org/10.1109/lisat.2014.6845201.

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Howe, J., C. Moore, M. O'Neill, F. Regazzoni, T. Güneysu, and K. Beeden. "Lattice-based Encryption Over Standard Lattices In Hardware." In DAC '16: The 53rd Annual Design Automation Conference 2016. ACM, 2016. http://dx.doi.org/10.1145/2897937.2898037.

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