Journal articles: 'Hardware based encryption'

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Huang, Xing Li, and Huan Chun Yang. "Two-Way ID Authentication and Hardware Encryption-Based Security Design of Mobile Hard Disk." Applied Mechanics and Materials 58-60 (June 2011): 573–78. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.573.

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The design of the "two-way ID authentication and hardware encryption-based secure mobile hard disk" adopts the smart card-based technology of two way ID authentication, thus enables higher authentication strength than ordinary password authentication and USB-KEY one way certification; adoption of dedicated hardware encryption chip on encrypting the hard disk data enhances the encryption speed; since this encryption is a hardware level encryption, it is completely transparent to users, and do not rely on the operating system or other applications, with almost no impact on system performance; that the key of the encryption system will be loaded before the system initialization (system boot) prevents malicious code attacks from hard drive, and even when the mobile hard disk was stolen, the thief cannot read out any encrypted data from it on any other computer as long as the thief has no access to the encryption key. Therefore, this "encrypted mobile hard disk" is more secure with better reading and writing performance, and thus can effectively protect sensitive data on the mobile hard disk.

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Kanda, Guard, and Kwangki Ryoo. "Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design." Webology 19, no. 1 (2022): 4581–96. http://dx.doi.org/10.14704/web/v19i1/web19304.

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At present, there are several pieces of research on designing and implementing new cryptographic algorithms that are lightweight and resistant to several, if not major forms of security attacks. However, some algorithms such as the International Data Encryption Algorithm (IDEA), which has been around for some time is yet to record any real threat against its functionality. To ensure its continued usage, current implementations rely on multiphase encryption where it is combined with other algorithms such as ROTation (ROT) and Data Encryption Standard (DES) for maximum security strength. Multiphase encryption implies that there is a tendency for an increase in hardware area and a reduction in overall speed. In such cases, having fast and reduced area algorithms are much desired. This paper, therefore, proposes an efficient hardware implementation of the IDEA cipher that is based on arithmetic modulo multiplication—one of the main computations of the IDEA—on a novel Vedic multiplier architecture. The increase in efficiency of the IDEA crypto architecture and the reduction in resources utilization is achieved through an enhancement of its structural architecture to utilize a fixed set of resources for all eight identical rounds of computation and the use of a proposed fast and lightweight Vedic hardware multiplier. The proposed hardware modification and resulting architecture are designed using the Xilinx ISE and Vivado tools. The architecture is synthesized using Precision Synthesis Tool (PS) and simulated using Modelsim SE 10.6d and ISIM simulation tools. The proposed IDEA cipher is 100% more efficient when designed based on the Vedic multiplier compared to existing designs. The hardware architecture is implemented on Spartan-6-FGG484 Field Programmable Gate Array (FPGA) using Verilog HDL. Verified results show that the proposed Vedic-based IDEA occupied 212 Slices with the Vedic multiplier only occupying 28 Slices out of the total 212. The proposed architecture operates at a maximum frequency of 253.3 MHz.

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Lee, Jaehyeok, Phap Ngoc Duong, and Hanho Lee. "Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption." Sensors 23, no. 17 (2023): 7389. http://dx.doi.org/10.3390/s23177389.

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With the increasing number of edge devices connecting to the cloud for storage and analysis, concerns about security and data privacy have become more prominent. Homomorphic encryption (HE) provides a promising solution by not only preserving data privacy but also enabling meaningful computations on encrypted data; while considerable efforts have been devoted to accelerating expensive homomorphic evaluation in the cloud, little attention has been paid to optimizing encryption and decryption (ENC-DEC) operations on the edge. In this paper, we propose efficient hardware architectures for CKKS-based ENC-DEC accelerators to facilitate computations on the client side. The proposed architectures are configurable to support a wide range of polynomial sizes with multiplicative depths (up to 30 levels) at a 128-bit security guarantee. We evaluate the hardware designs on the Xilinx XCU250 FPGA platform and achieve an average encryption time 23.7× faster than that of the well-known SEAL HE library. By reducing time complexity and improving the hardware utilization of cryptographic algorithms, our configurable CKKS-supported ENC-DEC hardware designs have the potential to greatly accelerate cryptographic processes on the client side in the post-quantum era.

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PAPAEFSTATHIOU, IOANNIS. "LOW LEVEL HARDWARE COMPRESSION FOR MULTI-GIGABIT NETWORKS." Journal of Circuits, Systems and Computers 13, no. 06 (2004): 1307–19. http://dx.doi.org/10.1142/s0218126604001969.

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As it has already been proved, link layer compression is very effective when used in packet networks. In particular, packet compression is especially useful when encryption is applied to the network packets. Encrypting the packets causes the data to be random in nature, and thus no compression can be applied after it. It is believed that low level encryption will be applied to the vast majority of Internet Protocol (IP) networks in the near future, and thus a large number of very sophisticated encryption devices have already been manufactured. Based on these facts, we claim that hardware devices that can compress network streams at link speed (and perform the compression just before the encryption), will also be widely used in the future networks. In this paper, we present such a hardware compressor/decompressor core that can work at speeds up to 10 Gb/s, it is fairly inexpensive and can very easily be plugged into an existing network node without causing any side effects. We additionally examine the performance against complexity tradeoffs of such compressor/decompressor devices. Finally, it is claimed that compression devices with throughput ranging from 0.5 to 10 Gb/s can be efficiently implemented based on the reference architecture.

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B, Lakshmi, Kirubakaran E, and Prabakar T.N. "FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION." ICTACT Journal on Communication Technology 01, no. 03 (2010): 150–56. http://dx.doi.org/10.21917/ijct.2010.0022.

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Xiao Bao-Jin, Tong Hai-Li, Zhang Jian-Zhong, Zhang Chao-Xia, and Wang Yun-Cai. "Spread spectrum communication based on hardware encryption." Acta Physica Sinica 60, no. 8 (2011): 080506. http://dx.doi.org/10.7498/aps.60.080506.

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Huang, Birong, Zhansheng Hou, Peng Lin, and Fei Zhou. "Implementation Method Of Remote Assistance Instruction Based On Hardware Secure Encryption." Journal of Physics: Conference Series 2136, no. 1 (2021): 012031. http://dx.doi.org/10.1088/1742-6596/2136/1/012031.

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Abstract As a public service enterprise related to energy security and national economy and people’s livelihood, the safe work is related to all walks of life and thousands of households. In power scenarios, the remote cooperative guidance needs to ensure the security of data communication. The implementation method of remote cooperative guidance in power scenarios based on hardware security encryption realizes the functions of terminal registration, user online and offline management, message call, control signaling negotiation, audio and video real-time call, graphic guidance and target tracking and labeling. Configuration TF card encryption at the mobile terminal chip and video server configuration high speed encryption card, WIFI / 4 g wireless networks to establish encryption channel, remote collaborative guidance terminal power scene registration messages, messages, call, and by guiding and structured data security encryption transmission, the unstructured data such as audio stream and video stream is encrypted. It not only realizes the secure encryption of message communication, but also guarantees the high-speed transmission of audio and video streams.

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Li, Jiakun, Yixuan Luo, Fei Wang, and Wei Gao. "Design and Implementation of Real-Time Image Acquisition Chip Based on Triple-Hybrid Encryption System." Electronics 11, no. 18 (2022): 2925. http://dx.doi.org/10.3390/electronics11182925.

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With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 μm2. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm2.

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Mahmood, Zainab H., and Mahmood K. Ibrahem. "HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV." Iraqi Journal of Information & Communications Technology 2, no. 2 (2019): 44–57. http://dx.doi.org/10.31987/ijict.2.2.69.

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In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

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张, 晓强. "Image Encryption Algorithm Based on the Hardware Platform." Journal of Image and Signal Processing 08, no. 02 (2019): 98–102. http://dx.doi.org/10.12677/jisp.2019.82014.

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Ruan, Wei Hua, and Qing Sheng Hu. "A Kind of Logarithmic Function Hardware Encryptor and Decryptor." Applied Mechanics and Materials 427-429 (September 2013): 2956–59. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.2956.

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This paper presents the realization of a kind of hardware encryptor and decryptor, which is based on Logarithmic Function principle. It shows how to design the encryption circuit and the decryption circuit by the sequential circuit. It had been designed in VHDL and simulated by Modelsim software, and then synthesized as well as realized on the FPGA chip EP2C5T144 by QuartusII software, last finished the test.

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Bin, Wang, Chong Ran Jiang, and Jing Li. "The Research of Hard Disk Encryption System Based on Advanced Encryption Standard Algorithm." Applied Mechanics and Materials 299 (February 2013): 172–75. http://dx.doi.org/10.4028/www.scientific.net/amm.299.172.

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The paper designs a hard disk encryption system with pure software realization, the system uses the Windows driver development technology, uses the AES（Advanced Encryption Standard） algorithm as the hard disk encryption algorithm.It could protect sensitive information effectively without additional hardware devices and implements encryption and decryption for the whole hard disk.

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Zeebaree, Subhi R. M. "DES encryption and decryption algorithm implementation based on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (2020): 774. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp774-781.

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Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

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Subhi, R. M. Zeebaree. "DES encryption and decryption algorithm implementation based on FPGA." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 18, no. 2 (2020): 774–81. https://doi.org/10.11591/ijeecs.v18.i2.pp774-781.

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Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept. The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

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Samir, El Adib, and Raissouni Naoufal. "CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications." International Journal of Embedded and Real-Time Communication Systems 10, no. 2 (2019): 19–36. http://dx.doi.org/10.4018/ijertcs.2019040102.

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For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.

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Nedjah, Nadia, and Luiza Mourelle. "Pareto-Optimal Hardware for Substitution Boxes." JUCS - Journal of Universal Computer Science 12, no. (4) (2006): 395–407. https://doi.org/10.3217/jucs-012-04-0395.

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In this paper, we propose a methodology based on genetic programming to automatically generate hardware designs of substitution boxes necessary for many cryptosystems such as DES encryption system. We aim at evolving minimal hardware specifications, which minimise both space (i.e. required gate number), response time (i.e. encryption and decryption time) and dissipated power. We compare our results against existing and well-known designs, which were produced by human designers using conventional methods.

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Stănică, George Cosmin, and Petre Anghelescu. "Multi-Layer Cryptosystem Using Reversible Cellular Automata." Electronics 14, no. 13 (2025): 2627. https://doi.org/10.3390/electronics14132627.

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The growing need for adaptable and efficient hardware-based encryption methods has led to increased interest in unconventional models such as cellular automata (CA). This study presents the hardware design and the field programmable gate array (FPGA)-based implementation of a multi-layer symmetric block encryption algorithm built on the principles of reversible cellular automata (RCA). The algorithm operates on 128-bit plaintext blocks processed over iterative rounds and integrates five RCA components, each assigned with specific transformation roles to ensure high data diffusion. A 256-bit secret key that governs the rule configuration yields a vast keyspace, significantly enhancing resistance to brute-force attacks. Key elements such as rule-based evolution, neighborhood radius, and hybrid cellular automata for random state generation are also integrated into the hardware logic. All cryptographic components, including initialization, encryption logic, and control, are built exclusively using CA, ensuring design consistency and low complexity. The cryptosystem takes advantage of the localized interactions and naturally parallel CA structure, which align with the architecture of FPGA devices, making them a suitable platform for implementing such encryption schemes. The results demonstrate the feasibility of deploying multi-layer RCA encryption schemes on reconfigurable devices and provide a viable path toward efficient and secure hardware-level encryption systems.

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Lin, Zhuosheng, Simin Yu, Chengqing Li, Jinhu Lü, and Qianxue Wang. "Design and Smartphone-Based Implementation of a Chaotic Video Communication Scheme via WAN Remote Transmission." International Journal of Bifurcation and Chaos 26, no. 09 (2016): 1650158. http://dx.doi.org/10.1142/s0218127416501583.

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This paper proposes a chaotic secure video remote communication scheme that can perform on real WAN networks, and implements it on a smartphone hardware platform. First, a joint encryption and compression scheme is designed by embedding a chaotic encryption scheme into the MJPG-Streamer source codes. Then, multiuser smartphone communications between the sender and the receiver are implemented via WAN remote transmission. Finally, the transmitted video data are received with the given IP address and port in an Android smartphone. It should be noted that, this is the first time that chaotic video encryption schemes are implemented on such a hardware platform. The experimental results demonstrate that the technical challenges on hardware implementation of secure video communication are successfully solved, reaching a balance amongst sufficient security level, real-time processing of massive video data, and utilization of available resources in the hardware environment. The proposed scheme can serve as a good application example of chaotic secure communications for smartphone and other mobile facilities in the future.

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Yang, Huiwei. "Application of Hybrid Encryption Algorithm in Hardware Encryption Interface Card." Security and Communication Networks 2022 (May 30, 2022): 1–11. http://dx.doi.org/10.1155/2022/7794209.

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In order to effectively solve the increasingly prominent network security problems, cryptographic algorithm is the key factor affecting the effectiveness of IPSec VPN encryption. Therefore, this paper mainly studies cryptographic algorithms and puts forward the following solutions: briefly analyze the concept and function of IPSec VPN, as well as the basic theoretical knowledge of IPSec Security Protocol and cryptography, and analyze the traditional cryptography, modern cryptography, symmetric cryptographic algorithms and asymmetric algorithms, and their security. At the same time, the executable and security performances of AES and DES algorithms are compared and analyzed. This paper studies the elliptic curve encryption algorithm ECC, expounds the mathematical basis of realizing the algorithm, and compares and analyzes the security performance and execution efficiency of ECC. Based on the above two algorithms, a hybrid encryption algorithm is proposed, and the realization mechanism of the hybrid encryption algorithm is studied and discussed. The hybrid encryption algorithm combines the advantages of ECC and AES. The algorithm selects 128-bit AES and 256-bit ECC. In order to better cover up plaintext C, AES is used to encrypt information. While enhancing security, speed is also considered. The improved encryption, decryption, and signature authentication algorithms are relatively safe and fast schemes. ECC algorithm is improved, and on this basis, ECC algorithm and AES algorithm are combined. Moreover, HMAC message authentication algorithm is added, and the performance of the improved algorithm is significantly improved.

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Olvera-Martinez, Luis, Manuel Cedillo-Hernandez, Carlos Adolfo Diaz-Rodriguez, Leonardo Faustinos-Morales, Antonio Cedillo-Hernandez, and Francisco Javier Garcia-Ugalde. "Symmetric Grayscale Image Encryption Based on Quantum Operators with Dynamic Matrices." Mathematics 13, no. 6 (2025): 982. https://doi.org/10.3390/math13060982.

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Image encryption is crucial for ensuring the confidentiality and integrity of digital images, preventing unauthorized access and alterations. However, existing encryption algorithms often involve complex mathematical operations or require specialized hardware, which limits their efficiency and practicality. To address these challenges, we propose a novel image encryption scheme based on the emulation of fundamental quantum operators from a multi-braided quantum group in the sense of Durdevich. These operators—coproduct, product, and braiding—are derived from quantum differential geometry and enable the dynamic generation of encryption values, avoiding the need for computationally intensive processes. Unlike quantum encryption methods that rely on physical quantum hardware, our approach simulates quantum behavior through classical computation, enhancing accessibility and efficiency. The proposed method is applied to grayscale images with 8-, 10-, and 12-bit depth per pixel. To validate its effectiveness, we conducted extensive experiments, including visual quality metrics (PSNR, SSIM), randomness evaluation using NIST 800-22, entropy and correlation analysis, key sensitivity tests, and execution time measurements. Additionally, comparative tests against AES encryption demonstrate the advantages of our approach in terms of performance and security. The results show that the proposed method provides a high level of security while maintaining computational efficiency.

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Hres, Oleksandr, Andrii Veryha, and Halyna Lastivka. "Using PIC18 Microcontrollers to Generate Chaotic Signals Based on Logistic Mapping." Security of Infocommunication Systems and Internet of Things, no. 1 (June 30, 2023): 01012. http://dx.doi.org/10.31861/sisiot2023.1.01012.

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In this paper, simulation and hardware implementation of the device for generating chaotic signals based on logistic mapping using microcontrollers of the РІС18 series was carried out. The operation of the device was investigated in the mode of generating chaotic oscillations at different values of the control parameter λ. By certain hardware and software modification, this generator can be used as a voice signal encryption The results of simulation and experimental studies confirm the possibility of using PIC18 microcontrollers for the implementation of chaotic oscillation generators based on discrete mappings, as well as using these controllers in the hardware implementation of language information encryption devices.

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Feng, YeJi, XiaoDong Liu, Shuai Jing, et al. "Optimization and Design of Key Expansion of SM4 Algorithm Based on ZYNQ." Journal of Physics: Conference Series 2296, no. 1 (2022): 012014. http://dx.doi.org/10.1088/1742-6596/2296/1/012014.

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Abstract As the application of "China Intelligent Manufacturing" in the field of production becomes more and more extensive, it becomes crucial to ensure the security of information interaction between production equipment. China's domestic encryption algorithm - SM4 block encryption algorithm came into being. The algorithm consists of a key expansion function and an encryption and decryption function. The key expansion function collects 128-bit keys at a time, and generates thirty-two 32-bit encryption keys after XOR operation, nonlinear permutation operation (S-box) and linear shift operation.The XOR operation parameter CK of the original key expansion function is obtained by the modulo method, which is similar to the system parameter FK and is a fixed value. In order to reduce the risk of deciphering caused by fixed parameters, the lightweight two-dimensional chaos algorithm Hemon is introduced for optimization design. The system parameters used in the SM4 algorithm are randomly generated with the change of the key, which improves the security of the algorithm. And use the hardware encryption platform ZYNQ-7000 series model xc7z100ffv900-1 FPGA side design and implementation, relying on the hard to decipher of hardware encryption to complete the optimization of SM4 algorithm key exchange.

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Wang, Mei Zhen, Feng Wu, Wei Ming Li, Ling Xiao, and Jiang Yuan. "A Packet-Combining Algorithm Based on SSLVPN with Hardware Acceleration Devices." Advanced Materials Research 660 (February 2013): 152–57. http://dx.doi.org/10.4028/www.scientific.net/amr.660.152.

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SSLVPN is widely used in Web applications, e-commerce, teleworking, etc...Due to the need to provide security, the complex computing has been seriously upset the performance of SSLVPN, may even cause the VPN throughput rates decline by one to two orders of magnitude. To improve SSLVPN encryption performance, domestic and foreign scholars have made a number of studies. This paper focuses on the SSLVPN with hardware acceleration devices, and put forward a packet-combining algorithms，which could effectively improve encryption performance and data throughput of SSLVPN.

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Yang, Chen, Ping Pan, and Qun Ding. "Image Encryption Scheme Based on Mixed Chaotic Bernoulli Measurement Matrix Block Compressive Sensing." Entropy 24, no. 2 (2022): 273. http://dx.doi.org/10.3390/e24020273.

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Many image encryption schemes based on compressive sensing have poor reconstructed image quality when the compression ratio is low, as well as difficulty in hardware implementation. To address these problems, we propose an image encryption algorithm based on the mixed chaotic Bernoulli measurement matrix block compressive sensing. A new chaotic measurement matrix was designed using the Chebyshev map and logistic map; the image was compressed in blocks to obtain the measurement values. Still, using the Chebyshev map and logistic map to generate encrypted sequences, the measurement values were encrypted by no repetitive scrambling as well as a two-way diffusion algorithm based on GF(257) for the measurement value matrix. The security of the encryption system was further improved by generating the Secure Hash Algorithm-256 of the original image to calculate the initial values of the chaotic mappings for the encryption process. The scheme uses two one-dimensional maps and is easier to implement in hardware. Simulation and performance analysis showed that the proposed image compression–encryption scheme can improve the peak signal-to-noise ratio of the reconstructed image with a low compression ratio and has good encryption against various attacks.

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Lian, Ji Hong, and Kai Chen. "Implementation of DES Encryption Algorithm Based on FPGA and Performance Analysis." Applied Mechanics and Materials 130-134 (October 2011): 2953–56. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.2953.

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This paper introduced the principle of DES encryption algorithm, designed and realized the DES encryption algorithm with verilog hardware description language, realized module simulation with Quartus II. Two comprehensive considerations from the resources and performance, one pipeline stage control is set in round function to improve the processing speed, Synchronous pipeline architecture of data XOR key round function and Key transformation function is realized on hardware to reducing logic complexity of the adjacent pipeline, round function multiplexing is realized by setting the round counter and controlling the data selector.

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Elrefai, Hisham M., Wafaa S. Sayed, and Lobna A. Said. "Hardware Implementation of a 2D Chaotic Map-Based Audio Encryption System Using S-Box." Electronics 13, no. 21 (2024): 4254. http://dx.doi.org/10.3390/electronics13214254.

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This paper presents a hardware-based audio encryption system using a 2D chaotic map and dynamic S-box design implemented on an Artix-7 FPGA platform. Three distinct chaotic maps—logistic–fraction (2D-LF), logistic–sine (2D-LS), and fraction–sine (2D-FS)—were investigated and implemented on an FPGA. The 2D-LF map was employed in the encryption system for its throughput and power efficiency performance. The proposed encryption system benefits from the randomness of chaotic sequences for block permutation and S-box substitution to enhance the diffusion and confusion properties of the encrypted speech signal. The system’s encryption strength is validated through performance evaluations, using the mean squared error (MSE), signal-to-noise ratio (SNR), correlation coefficients, and NIST randomness tests, which confirm the unpredictability of the encrypted speech signal. The hardware implementation results show a throughput of 2880 Mbps and power consumption of 0.13 W.

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Fadhil, Sahib Hasan, and Amer Saffo Maryam. "FPGA Hardware Co-Simulation of Image Encryption using Hybrid Chaotic Maps Based Stream Cipher." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 4 (2020): 215–25. https://doi.org/10.35940/ijeat.D6713.049420.

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In This paper, new model of image encryption is designed. This model using stream cipher based on finite precision chaotic maps. The model designed in efficient way by using Xilinx System Generator (XSG). Pseudo Random Bit Generator (PRBG) depends on chaotic maps is proposed to design Fixed Point Hybrid Chaotic Map-PRBG (FPHYBCM-PRBG). National Institute of Standards and Technology (NIST) randomness measures tested the randomness of the proposed FPHYBCM-PRBG system. The security analysis, such as histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPHYBCM-PRBG is suitable for image encryption based on stream cipher and outperform some encryption algorithms in sufficient way to enhance the security and robust against brute force attack with low maximum frequency and throughput.

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Li, Yong Fei. "Design and Implementation of Encryption Scheme in Web-Based Examination System." Advanced Materials Research 756-759 (September 2013): 1106–9. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.1106.

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Requirements on encryption of web-based examination system were analyze, and different encryption technologies were used to meet the needs on three levels, including important data, core processing logic and some restricted functions. For important data, its confidentiality and integrity were realized. The core processing logic in ASP script was built in COM component. And some restricted functions were protected with hardware key. Encryption which protected data, code and function provided necessary safety for the web-based examination system.

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Teli, Mallikarjun Awwanna. "Design and verification of AES cryptography algorithm on RISC-V." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 03 (2025): 1–9. https://doi.org/10.55041/ijsrem42109.

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—The implementation of the Advanced Encryption Standard (AES) on RISC-V processors has gained attention for its potential in secure and efficient cryptographic operations. Researchers have explored hardware acceleration techniques, custom instruction set extensions, and vector-based optimizations to enhance performance. AES integration into RISC-V cores has demonstrated improvements in execution speed, energy efficiency, and memory footprint, making it suitable for IoT and embedded applications. Several studies propose hardware accelerators and co-processors that reduce encryption time while maintaining cryptographic security. Vector-based AES implementations fur- ther improve efficiency by leveraging parallel processing capa- bilities of modern RISC-V architectures. The introduction of custom AES instructions enables high-throughput encryption and decryption with minimal software overhead. FPGA-based AES accelerators have also been explored to enhance adaptability and flexibility in cryptographic applications. Experimental results in- dicate that RISC-V AES implementations outperform traditional software-based encryption in terms of speed and power con- sumption. The standardization of AES instruction set extensions in RISC-V continues to evolve, contributing to a more secure and efficient cryptographic ecosystem. This paper reviews recent advancements in AES integration with RISC-V, highlighting key performance metrics and optimization techniques. Index Terms—AES-128 Encryption, RISC-V Cryptographic Extensions, Hardware Acceleration, FPGA-based AES Co- processor.

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LIN, XIN, WEIHUI SHI, and YONGXIANG DU. "INTERACTIVE DATA ENCRYPTION STRATEGY FOR DISTRIBUTED SIMULATION SYSTEM." International Journal of Modeling, Simulation, and Scientific Computing 04, no. 04 (2013): 1342005. http://dx.doi.org/10.1142/s1793962313420051.

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The distributed simulation system interoperation can be divided into six levels. Interactive data encryption can be completed in each level, lead to six encryption strategies: data field encryption, data package encryption, program module encryption, simulation application encryption, simulation node encryption, and simulation system encryption. There are four basic Encryption/decryption realization modes: serial modes with software or hardware realization, parallel modes based on embedded processor or FPGA/ASIC system. Large and Complex distributed simulation system may employ one or several encryption strategies and realization modes.

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Yu, Jiayin, Yaqin Xie, Shiyu Guo, Yanqi Zhou, and Erfu Wang. "Parallel Encryption of Noisy Images Based on Sequence Generator and Chaotic Measurement Matrix." Complexity 2020 (May 7, 2020): 1–18. http://dx.doi.org/10.1155/2020/1987670.

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With the rapid development of information technology in today’s society, the security of transmission and the storage capacity of hardware are increasingly required in the process of image transmission. Compressed sensing technology can achieve data sampling and compression at the rate far lower than that of the Nyquist sampling theorem and can effectively improve the efficiency of information transmission. Aiming at the problem of weak security of compressed sensing, this study combines the cryptographic characteristics of chaotic systems with compressed sensing technology. In the actual research process, the existing image encryption technology needs to be applied to the hardware. This paper focuses on the combination of image encryption based on compressed sensing and digital logic circuits. We propose a novel technology of parallel image encryption based on a sequence generator. It uses a three-dimensional chaotic map with multiple stability to generate a measurement matrix. This study also analyzes the effectiveness, reliability, and security of the parallel encryption algorithm for source noise pollution with different distribution characteristics. Simulation results show that parallel encryption technology can effectively improve the efficiency of information transmission and greatly enhance its security through key space expansion.

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Tang, Hong Wei. "32-bit Datapath AES IP Core Based on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1848–51. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1848.

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This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.

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Medileh, Saci, Abdelkader Laouid, Mohammad Hammoudeh, et al. "A Multi-Key with Partially Homomorphic Encryption Scheme for Low-End Devices Ensuring Data Integrity." Information 14, no. 5 (2023): 263. http://dx.doi.org/10.3390/info14050263.

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In today’s hyperconnected world, the Internet of Things and Cloud Computing complement each other in several areas. Cloud Computing provides IoT systems with an efficient and flexible environment that supports application requirements such as real-time control/monitoring, scalability, fault tolerance, and numerous security services. Hardware and software limitations of IoT devices can be mitigated using the massive on-demand cloud resources. However, IoT cloud-based solutions pose some security and privacy concerns, specifically when an untrusted cloud is used. This calls for strong encryption schemes that allow operations on data in an encrypted format without compromising the encryption. This paper presents an asymmetric multi-key and partially homomorphic encryption scheme. The scheme provides the addition operation by encrypting each decimal digit of the given integer number separately using a special key. In addition, data integrity processes are performed when an untrusted third party performs homomorphic operations on encrypted data. The proposed work considers the most widely known issues like the encrypted data size, slow operations at the hardware level, and high computing costs at the provider level. The size of generated ciphertext is almost equal to the size of the plaintext, and order-preserving is ensured using an asymmetrical encryption version.

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Gorlov, Lev, Maksim Iavich, and Razvan Bocu. "Linear Layer Architecture Based on Cyclic Shift and XOR." Symmetry 15, no. 8 (2023): 1496. http://dx.doi.org/10.3390/sym15081496.

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One of the nodes of a block symmetric encryption algorithm is represented by a linear layer, the purpose of which is to distribute the mutual influence of bits within the processed data block. Several methods exist for constructing a linear layer, the most common of which are matrix multiplication operations and the permutation of bits. Both approaches have high computational complexity and are not equally effective for both hardware and software implementations. This paper presents an approach for constructing linear functions for block symmetric encryption algorithms utilizing cyclic shift, and bitwise addition operations are formulated. We provide a preliminary assessment of certain properties of such functions, including the branch number. This linear operation can accommodate binary words of any length, allowing for the design of an optimal linear layer for software or hardware architectures with any word size. Furthermore, the developed architecture allows for balancing the laboriousness of linear operations and related branch numbers. The proposed novel linear layer architecture facilitates the creation of fast lightweight encryption algorithms as well as robust classical algorithms with a high level of cryptographic strength. For efficient implementation on software and hardware platforms, no additional optimizations are required, as the proposed linear layer allows for achieving high performance in both cases.

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Круліковський, Олег, Сергій Галюк, Ігор Сафронов, and Іван Горбенко. "Ukrainian National Encryption Standards for FPGA Based Embedded Systems." Security of Infocommunication Systems and Internet of Things, no. 1 (June 30, 2023): 01005. http://dx.doi.org/10.31861/sisiot2023.1.01005.

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The paper presents the hardware implementation based on FPGA of the main cryptographic transformations of the symmetric transformation algorithm of DSTU 7624:2014 and the stream cipher of DSTU 8845:2019, which are the national encryption standards of Ukraine. In the case of DSTU 7624: 2014 developed and implemented a hardware implementation for multiplication of two polynomials modulo x8+x4+x3+x2+1 in the form of a combinational circuit that allows to execute the MixColumn transformation by one cycle. SubBytes transformation is implemented based on asynchronous read-only memory. For stream cipher, DSTU 8845:2019 the nonlinear function T are implemented as subtitution byte operation in the form of precalculated cells of ROM memory. The multiplication function by α and α-1 in Galois field arithmetic GF (2 64) is realized based on ROM and combinational logic. The control of the modes of operation of the shift register with linear feedback is performed based on a FSM. Both hardware implementations of encryption standards have been verified by the authors according to the specified data in the standard, and their HDL code can be provided by the authors for further research to interested parties.

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Yang, Junpu. "Computer Data Encryption System Based on Nonlinear Partial Differential Equations." Mobile Information Systems 2022 (August 19, 2022): 1–9. http://dx.doi.org/10.1155/2022/3395019.

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Data encryption is to convert plaintext data into ciphertext through a data encryption algorithm and then transmit the ciphertext. After the recipient receives the ciphertext, the ciphertext is restored to plaintext, which provides protection and technical support for information security. The main purpose of this article is to design a computer data encryption system based on nonlinear partial differential equations. This paper uses the DES encryption algorithm to encrypt data and implements an onion encryption system that encrypts the outer layer of the database and tests and analyzes the encryption efficiency and additional overhead of the database encryption system on a general database to verify the design application prospects of ideas. In addition, the overall scheme of the encryption system, the hardware, and software of the system are designed in detail, the system is debugged, the overall test is tested, and the data encryption and decryption are effective and feasible. The experimental results of this paper show that after the construction of a computer data encryption system based on nonlinear partial differential equations, the overall security of the data is increased by 25%. In addition, after comparison, the security performance of the onion-type data encryption system is higher than that of the MySQL-type data. The performance of the encryption system is 21% lower. It has certain practical value and significance to apply it to the computer data encryption system.

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Papadogiannaki, Eva, and Sotiris Ioannidis. "Acceleration of Intrusion Detection in Encrypted Network Traffic Using Heterogeneous Hardware." Sensors 21, no. 4 (2021): 1140. http://dx.doi.org/10.3390/s21041140.

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More than 75% of Internet traffic is now encrypted, and this percentage is constantly increasing. The majority of communications are secured using common encryption protocols such as SSL/TLS and IPsec to ensure security and protect the privacy of Internet users. However, encryption can be exploited to hide malicious activities, camouflaged into normal network traffic. Traditionally, network traffic inspection is based on techniques like deep packet inspection (DPI). Common applications for DPI include but are not limited to firewalls, intrusion detection and prevention systems, L7 filtering, and packet forwarding. With the widespread adoption of network encryption though, DPI tools that rely on packet payload content are becoming less effective, demanding the development of more sophisticated techniques in order to adapt to current network encryption trends. In this work, we present HeaderHunter, a fast signature-based intrusion detection system even for encrypted network traffic. We generate signatures using only network packet metadata extracted from packet headers. In addition, we examine the processing acceleration of the intrusion detection engine using different heterogeneous hardware architectures.

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Pushpalatha, G. S., and Ramesh S. Dr. "Collective Research Review on Chaotic Based Encryption Algorithms, Speech Encryption Algorithms and Cryptographic Requirements." International Journal of Engineering and Management Research 14, no. 2 (2024): 165–70. https://doi.org/10.5281/zenodo.11201784.

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Chaotic cryptography has been a recent development by researchers due to its interesting properties such as non-linear behavior, sensitivity to initial conditions, ergodicity, mixing, confusion and diffusion etc. This paper is a brief review of various standard encryption algorithms, cryptographic requirements for design of chaotic based cryptosystem and chaos-based speech encryption algorithms. This study also gives various statistical tests needs to be considered for conformity about suitable randomness of the binary sequences generated using either hardware or software means for cryptographic applications as key sequence.

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Ma, Xiao Cong, Guang Hui Cai, Hong Chao Sun, and Hong Ye Li. "Design and Implementation of an Encryption/Decryption System Based on FPGA." Advanced Materials Research 1022 (August 2014): 368–71. http://dx.doi.org/10.4028/www.scientific.net/amr.1022.368.

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This paper designs an encryption and decryption system based on the FPGA. The system uses AES algorithm to encrypt and decrypt data. A pipeline IP core is designed with the reconfigurable technology complying with the Avalon bus interface specification. The IP core is applied to be a custom component on Nios II architecture so that the encryption and decryption processes through hardware can be controlled by software. Finally, the program is downloaded to the Altera DE2 development board and completes the testing of encryption and decryption processes. The system can be widely implemented in the field of data security.

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Liang, Wei, Jian Bo Xu, Wei Hong Huang, and Li Peng. "The Design and Implementation of ECC High-Speed Encryption Engine Based on FPGA." Advanced Materials Research 459 (January 2012): 544–48. http://dx.doi.org/10.4028/www.scientific.net/amr.459.544.

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Network security technology ensures secure data transmission in network. Meanwhile, it brings extra overhead of security system in terms of cost and performance, which seriously affects the rapid development of existing high-speed encryption systems. The existing encryption technology cannot meet the demand of high security, low cost and high real-time. For solving above problems, an ECC encryption engine architecture based on scalable public key cipher and a high-speed configurable multiplication algorithm are designed. The algorithm was tested on FPGA platform and the experiment results show that the system has better computation speed and lower cost overhead. By comparing with other systems, our system has benefits in terms of hardware overhead and encryption time ratio

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Salmanov, V. "POLYMORPHİC ENCRYPTİON AND DECRYPTİON ALGORİTHMS." Sciences of Europe, no. 98 (August 8, 2022): 76–79. https://doi.org/10.5281/zenodo.6973815.

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Based on the analysis, an algorithm for improving the development of automated distance learning systems is considered. The algorithm, designed to be integrated into existing educational systems, has been designed to be supported during use outside of robust computing systems. When preparing software based on the proposed algorithm, new data encryption technologies can be used. This completely eliminates the need for hardware.

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Shi, Yanfeng, Jiqiang Liu, Zhen Han, and Shuo Qiu. "Deterministic attribute-based encryption." International Journal of High Performance Computing and Networking 9, no. 5/6 (2016): 443. http://dx.doi.org/10.1504/ijhpcn.2016.080417.

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Fetteha, Marwan A., Wafaa S. Sayed, and Lobna A. Said. "A Lightweight Image Encryption Scheme Using DNA Coding and Chaos." Electronics 12, no. 24 (2023): 4895. http://dx.doi.org/10.3390/electronics12244895.

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Protecting transmitted multimedia data such as images is a significant concern. This work proposes an encryption algorithm for greyscale images using a Pseudo-Random Number Generator (PRNG), DNA coding, and pixel sum. The proposed approach is implemented on a Genesys 2 FPGA using minimal hardware resources and can operate at a maximum frequency of 110.8 MHz. In addition, several performance evaluation tests are conducted for multiple images, including statistical analysis of the encrypted image, keyspace analysis, and differential attack analysis. The system is compared to recent works with respect to encryption quality and used hardware resources. The proposed scheme outperformed recent chaos-based image encryption schemes.

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Do, Taehoon, Seungwoo Park, Jaehwan Lee, and Sangoh Park. "M-folding method–based elliptic curve cryptosystem for industrial cyber-physical system." International Journal of Distributed Sensor Networks 15, no. 10 (2019): 155014771987904. http://dx.doi.org/10.1177/1550147719879045.

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Recently, cyber-physical system is widely used for smart system control in various fields. Various functions of the cyber-physical system must overcome the limited hardware resources constraint of an embedded system. In addition, the data required from the industrial cyber-physical system are critical; therefore, a highly secure encryption technique is required. However, security and computational throughput are incompatible with each other in the cryptographic technique; therefore, the industrial cyber-physical system needs to adopt a highly efficient and secure encryption technique considering the limited available resources. This study applies the m-folding method to the highly secure elliptic curve algorithm to improve efficiency and proposes the cryptosystem optimized for the resource-constrained industrial cyber-physical system. The proposed m-folding method–based elliptic curve encryption showed 50% faster encryption than the existing methods.

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Chen, Baoju, Simin Yu, Ping Chen, Liangshan Xiao, and Jinhu Lü. "Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications." International Journal of Bifurcation and Chaos 30, no. 05 (2020): 2050075. http://dx.doi.org/10.1142/s0218127420500753.

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In this paper, a Virtex-7-based video chaotic secure communication scheme is investigated. First, the network sending and receiving controller Intellectual Property (IP) cores are designed. Next, the chaotic encryption and decryption IP cores are implemented using fixed-point algorithm, pipeline operation, and state machine control. Thus, video capturing, video displaying, network sending, network receiving, chaotic encrypting, and chaotic decrypting can be achieved via IP core integration design. An improved 7D chaotic stream cipher algorithm for resisting divide-and-conquer attack is then designed and realized on a Virtex-7 high-end FPGA platform. Hardware experimental results are also given to verify the feasibility of the scheme.

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Lee, Sung-Won, and Kwee-Bo Sim. "Design and Hardware Implementation of a Simplified DAG-Based Blockchain and New AES-CBC Algorithm for IoT Security." Electronics 10, no. 9 (2021): 1127. http://dx.doi.org/10.3390/electronics10091127.

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Recently, to enhance the security of the Internet of Things (IoT), research on blockchain-based encryption algorithms has been actively conducted. However, because blockchains have complex structures and process large amounts of data, there are still many difficulties in using the conventional blockchain-based encryption algorithms in an IoT system that must have low power consumption and be ultra-lightweight. In this study, to address these problems (1) we simplified the conventional Directed Acyclic Graph (DAG)-based blockchain structure, and (2) we proposed a new Advanced Encryption Standard (AES)-Cipher Block Chaining (CBC) algorithm with enhanced security by periodically changing the secret key and initialization vector (IV) in the conventional AES-CBC encryption algorithm. Because the DAG, which is the conventional blockchain structure, randomly transmits data to multiple blocks, there may be overlapping blocks, and the quantity of transmitted data is not limited; thus, the time and power consumption for encryption and decryption increase. In this study, a simplified DAG was designed to address these problems so that packets can be transmitted only to three blocks, without overlapping. Finally, to verify the effectiveness of the algorithm proposed in this paper, an IoT system consisting of 10 clients and one server was implemented in hardware, and an experiment was conducted. Through the experiment, it was confirmed that when the proposed AES-CBC algorithm was used, the time taken and the amount of power consumed for encryption and decryption were reduced by about 20% compared to the conventional AES-CBC algorithm.

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Álvarez, Rafael, Alicia Andrade, and Antonio Zamora. "Optimizing a Password Hashing Function with Hardware-Accelerated Symmetric Encryption." Symmetry 10, no. 12 (2018): 705. http://dx.doi.org/10.3390/sym10120705.

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Password-based key derivation functions (PBKDFs) are commonly used to transform user passwords into keys for symmetric encryption, as well as for user authentication, password hashing, and preventing attacks based on custom hardware. We propose two optimized alternatives that enhance the performance of a previously published PBKDF. This design is based on (1) employing a symmetric cipher, the Advanced Encryption Standard (AES), as a pseudo-random generator and (2) taking advantage of the support for the hardware acceleration for AES that is available on many common platforms in order to mitigate common attacks to password-based user authentication systems. We also analyze their security characteristics, establishing that they are equivalent to the security of the core primitive (AES), and we compare their performance with well-known PBKDF algorithms, such as Scrypt and Argon2, with favorable results.

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Huang, Gao Feng. "A File Encryption System Based on Fingerprint-Embedded Storage." Applied Mechanics and Materials 446-447 (November 2013): 1017–21. http://dx.doi.org/10.4028/www.scientific.net/amm.446-447.1017.

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A file encryption system based on fingerprint-embedded storage is proposed in this paper. The system uses the MBF200 to carry out the collection of fingerprints, uses the embedded chip ARM2410 to process and store the fingerprints as a hardware platform, and customs the man-machine interfaces for the processes of file encryption and decryption on the host side in accordance with the needs of development. Experimental results show that the system is easy to operate, with high stability, versatility, fast speed and high precision in the fingerprint acquisition.

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Zheng, Hanzhong, Simin Yu, and Xiangqian Xu. "A Systematic Methodology for Multi-Images Encryption and Decryption Based on Single Chaotic System and FPGA Embedded Implementation." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/698608.

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A systematic methodology is developed for multi-images encryption and decryption and field programmable gate array (FPGA) embedded implementation by using single discrete time chaotic system. To overcome the traditional limitations that a chaotic system can only encrypt or decrypt one image, this paper initiates a new approach to designn-dimensional (n-D) discrete time chaotic controlled systems via some variables anticontrol, which can achieve multipath drive-response synchronization. To that end, the designedn-dimensional discrete time chaotic controlled systems are used for multi-images encryption and decryption. A generalized design principle and the corresponding implementation steps are also given. Based on the FPGA embedded hardware system working platform with XUP Virtex-II type, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed, and the related system design and hardware implementation results are demonstrated, with the related mathematical problems analyzed.

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BIAN, Song, Masayuki HIROMOTO, and Takashi SATO. "Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A, no. 2 (2019): 430–39. http://dx.doi.org/10.1587/transfun.e102.a.430.

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Journal articles on the topic 'Hardware based encryption'

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