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Books on the topic 'Hardware Construction Languages (HCLs)'

Author: Grafiati

Published: 25 May 2024

Last updated: 31 July 2025

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Consult the top 44 books for your research on the topic 'Hardware Construction Languages (HCLs).'

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1

Alain, Vachoux, ed. Analog and mixed-signal hardware description languages. Kluwer Academic Publishers, 1997.

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2

IFIP WG10.2 International Symposium on Computer Hardware Description Languages and their Applications (9th 1989 Washington, D. C.). Computer hardware description languages and their applications: Proceedings of theIFIP WG 10.2 Ninth International Symposium on Computer Hardware Description Languages and their Applications : Washington, D. C., U.S.A., 19-21 June, 1989. North-Holland, 1990.

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3

Carlos, Delgado Kloos, and Damm Werner, eds. Practical formal methods for hardware design. Springer, 1997.

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4

1947-, Koomen C. J., Motooka To ru 1929-, IFIP TC-10, and IFIP WG 10 2, eds. Computer hardware description languages and their applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and Their Applications, Tokyo, Japan, 29-31 August 1985. North-Holland, 1985.

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5

IFIP WG 10.2 International Conference on Computer Hardware Description Languages and their Applications (7th 1985 Tokyo). Computer hardware description languages and their applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and their Applications : Tokyo, Japan, 29-31 August, 1985. North-Holland, 1985.

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6

(2003), FDL'03. Languages for system specification: Selected contributions on UML, SystemC, System Verilig, mixed-signal systems, and property specification from FDL'03. Kluwer Academic Publishers, 2004.

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7

Anne, Mignotte, Villar Eugenio, and Horobin Lynn, eds. System on chip design languages: Extended papers : best of FDL'01 and HDLCon'01. Kluwer Academic Publishers, 2002.

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8

Hoffmann, Andreas. Architecture exploration for embedded processors with LISA. Kluwer Academic Publishers, 2002.

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9

1956-, Foster Harry, ed. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. Kluwer Academic Publishers, 2000.

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10

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Kluwer Academic Publishers, 2001.

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11

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Kluwer Academic Publishers, 2001.

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12

G, Vranesic Zvonko, ed. Fundamentals of digital logic with VHDL design. 3rd ed. McGraw-Hill, 2008.

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13

G, Vranesic Zvonko, ed. Fundamentals of digital logic with VHDL design. 2nd ed. McGraw-Hill Companies, 2005.

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14

Chonlameth, Arpnikanondt, ed. A platform-centric approach to system-on-chip (SoC) design. Springer, 2005.

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15

Moto-Oka, T., and C. J. Koomen. Computer Hardware Description Languages and Their Applications. Elsevier Science & Technology, 1985.

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16

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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17

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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18

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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19

Palnitkar, Samir. Design Verification with e. Prentice Hall PTR, 2003.

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20

Villar, Eugenio, and Jean Mermet. System Specification and Design Languages: Best of FDL'02. Springer, 2010.

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21

Morawiec, Adam, and Philippe Coussy. High-Level Synthesis: From Algorithm to Digital Circuit. Coussy Philippe Morawiec Adam, 2010.

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22

Languages for Embedded Systems and Their Applications Lecture Notes in Electrical Engineering. Springer, 2009.

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23

Morawiec, Adam, and Philippe Coussy. High-Level Synthesis: From Algorithm to Digital Circuit. Springer, 2008.

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24

(Editor), Anne Mignotte, Eugenio Villar (Editor), and Lynn Horobin (Editor), eds. System on Chip Design Languages - Extended Papers: Best of FDL'01 and HDLCon'01. Springer, 2002.

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25

Sutherland, Stuart, Simon Davidmann, and Peter Flake. SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling. Springer, 2003.

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26

Schliebusch, Oliver, Heinrich Meyr, and Rainer Leupers. Optimized ASIP Synthesis from Architecture Description Language Models. Springer, 2007.

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27

Schliebusch, Oliver, Heinrich Meyr, and Rainer Leupers. Optimized ASIP Synthesis from Architecture Description Language Models. Springer, 2010.

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28

Vachoux, A. Applications of Specification and Design Languages for Socs: Selected Papers from FDL 2005. Springer London, Limited, 2006.

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29

Vachoux, A. Applications of Specification and Design Languages for SoCs: Selected papers from FDL 2005. Springer, 2010.

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30

Boulet, Pierre. Advances in Design and Specification Languages for SoCs: Selected Contributions from FDL'04. Springer, 2014.

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31

Boulet, Pierre. Advances in Design and Specification Languages for Socs: Selected Contributions from FDL'04. Springer London, Limited, 2006.

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32

Cerny, Eduard, Bachir Berkane, Pierre Girodias, and Karim Khordoc. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method. Springer, 1998.

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33

Hoffmann, Andreas, Heinrich Meyr, and Rainer Leupers. Architecture Exploration for Embedded Processors with LISA. Springer London, Limited, 2013.

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34

Hoffmann, Andreas, Heinrich Meyr, and Rainer Leupers. Architecture Exploration for Embedded Processors with LISA. Springer, 2010.

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35

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog. Springer, 2013.

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36

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog. 2nd ed. Springer, 2001.

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37

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog. Springer London, Limited, 2007.

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38

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog. Springer, 2013.

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39

Fundamentals of Digital Logic with Vhdl Design. McGraw-Hill Education, 2000.

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40

Fundamentals of Digital Logic with VHDL Design. McGraw-Hill Companies, The, 2022.

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41

Analysis and Design of CMOS Clocking Circuits for Low Phase Noise. Institution of Engineering & Technology, 2020.

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42

Embedded Microcontroller Interfacing: Designing Integrated Projects. Springer, 2012.

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43

Embedded Microcontroller Interfacing: Designing Integrated Projects. Springer, 2010.

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44

Hilgurt, S. Ya, and O. A. Chemerys. Reconfigurable signature-based information security tools of computer systems. PH “Akademperiodyka”, 2022. http://dx.doi.org/10.15407/akademperiodyka.458.297.

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Abstract:

The book is devoted to the research and development of methods for combining computational structures for reconfigurable signature-based information protection tools for computer systems and networks in order to increase their efficiency. Network security tools based, among others, on such AI-based approaches as deep neural networking, despite the great progress shown in recent years, still suffer from nonzero recognition error probability. Even a low probability of such an error in a critical infrastructure can be disastrous. Therefore, signature-based recognition methods with their theoretic

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