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Dissertations / Theses on the topic 'Hardware Emulator'

Author: Grafiati

Published: 6 September 2023

Last updated: 31 July 2025

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1

Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.

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This Master's Thesis handles prestudy work and early hardware development that resulted in architectural definitions and prototype hardware of electronic ground support equipment. This equipment is destined to emulate the electric power consumption of the PPS5000 Hall Effect Thruster (HET), for use in satellite end-to-end tests of the all-electric Geostationary Satellite Electra, developed at OHB Sweden AB. The Thruster Emulator (TEM) was defined through a resulting compilation of intricate interdependent components that interface the satellite power system and the thruster, which yielded an a

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2

Stanley, Berdenia Walker. "Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13360.

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3

Witkowsky, Jason. "A hardware emulator testbed for a software-defined radio." Thesis, Peninsula Technikon, 2003. http://hdl.handle.net/20.500.11838/1170.

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Submitted in fulfillment of the requirement for the Masters degree of Technology (MTech): Electrical Engineering, 2003<br>Contemporary software-defined radio (SDR) is continuously changing and challenging the way traditional RF systems operate. Having more of a radio system’s operation in software enables further flexibility through the use of software manipulation. Due to practical limitations, however, it is not always feasible to have the entire radio system’s operations performed using software. Practical limitations, therefore, require that a SDR employs some form of RF front-end in

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4

Daniil, Nickolaos. "Battery emulator operating in a power hardware-in-the-loop simulation : the concept of hybrid battery emulator." Thesis, University of Bristol, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.723517.

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5

O'Rourke, Colm Joseph. "Design of a hardware solar emulator for an experimental microgrid." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99852.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 67-68).<br>Microgrids are regions where local generation and loads are clustered together. Students from the LEES group at MIT are currently developing an experimental microgrid. This will enable various studies in the area of microgrid dynamics. The setup consists of a variety of modules that emulate both conventional and renewable sources. In this thesis, we focus on the design of one of th

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6

Petucco, Andrea. "Hardware in the loop, all-electronic wind turbine emulator for grid compliance testing." Doctoral thesis, Università degli studi di Padova, 2017. http://hdl.handle.net/11577/3422321.

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During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication

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7

Adnan, Muhammad Wasif. "Implementation of an FPGA based Emulator for High Speed Power Electronic Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175752.

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During development of control systems for power electronic systems, it is desirable to test the controller in real-time, by interfacing it with an emulator device. In this context, this work comprises the development of an emulator that can model accurately the dynamics of high speed power electronic systems and provides interfaces that are compatible with the real hardware. The realtime state calculations, based on discrete models, were performed on custom logic, implemented on an FPGA. The realized system allows to emulate Linear Parameter Varying (LPV) systems, achieving sampling rates up t

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8

Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Dresden TUDpress, 2008. http://d-nb.info/991847423/04.

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9

Shadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.

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The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel

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10

Oliveira, José Rodrigo de. "Emulador de turbina eólica : uma ferramenta para o estudo experimental e computacional /." Bauru, 2019. http://hdl.handle.net/11449/191354.

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Orientador: André Luiz Andreoli<br>Resumo: As fontes renováveis de energia apresentam-se como solução para problemas relacionados ao aumento da demanda por energia elétrica e crescimento dos níveis de emissão de gás carbônico, uma vez que são não poluentes, limpas e abundantes. Aproveitamentos eólicos se mostram como uma das mais promissoras fontes de energia renovável, e por essa razão as pesquisas envolvendo este tipo de aproveitamento têm despertado grande interesse na comunidade científica. Este trabalho apresenta o desenvolvimento de um emulador de turbina eólica (ETE), uma ferramenta de

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11

Tomaro, Emiliano. "Simulations and automated tests of battery management system control strategies and diagnosis on hardware in the loop system." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/19241/.

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The aim of this master’s degree thesis is to describe the activities performed during a four months internship in Magneti Marelli Powertrain, Bologna. The role I covered in this period was Validation Engineer for Hybrid & Electric systems in Hardware in the Loop (HIL) environment, the main activity was to develop automated tests in python involving software and control strategies. A first focus of this thesis is on the Battery Management System functionalities, Hardware in the Loop system and Test Automation. The second part of the thesis describes the experimental activity of the internishi

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12

Thornes, Tobias. "Investigating the potential for improving the accuracy of weather and climate forecasts by varying numerical precision in computer models." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:038874a3-710a-476d-a9f7-e94ef1036648.

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Accurate forecasts of weather and climate will become increasingly important as the world adapts to anthropogenic climatic change. Forecasts' accuracy is limited by the computer power available to forecast centres, which determines the maximum resolution, ensemble size and complexity of atmospheric models. Furthermore, faster supercomputers are increasingly energy-hungry and unaffordable to run. In this thesis, a new means of making computer simulations more efficient is presented that could lead to more accurate forecasts without increasing computational costs. This 'scale-selective reduced p

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13

Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.

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14

Williams, Steve. "Advanced Hardware-in-the-Loop Testing Assures RF Communication System Success." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/604299.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California<br>RF Communication (COMMS) systems where receivers and transmitters are in motion must be proven rigorously over an array of natural RF link perturbations such as Carrier Doppler shift, Signal Doppler shift, delay, path loss and noise. These perturbations play significant roles in COMMS systems involving satellites, aircraft, UAVs, missiles, targets and ground stations. In these ap

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15

Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.

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16

Ford, Gregory Fick. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.

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17

Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Doctoral thesis, Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-115411.

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Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration. An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatore

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18

Almeida, Filipe Afonso de. "Parallel software emulation of multi-processor dataflow machines on transputer networks." Thesis, University of Kent, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315170.

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19

Wells, George James. "Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ62899.pdf.

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20

Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." TUDpress, 2008. https://monarch.qucosa.de/id/qucosa%3A19914.

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Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration. An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatore

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21

Päivänsäde, V. (Ville). "Dynamic power estimation with a hardware emulation acquired switching activity model." Master's thesis, University of Oulu, 2016. http://urn.fi/URN:NBN:fi:oulu-201609082736.

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This thesis is a study of dynamic power estimation at register-transfer level using an activity model acquired with a hardware emulator. The thesis consists of a practical part that presents the studied flow and the testing work related to it and a theory part that supports the topics of the practical part. In the theory part, the common sources of power consumption in complementary metal-oxide-semiconductor logic are studied, along with brief introductions about their reduction techniques. The electronic design automation tool methodologies, commonly used for power estimation and analysis, ar

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22

Tournez, Florian. "Du composant au conducteur dans la boucle de simulation pour le test de véhicules électriques hybrides." Electronic Thesis or Diss., Université de Lille (2022-....), 2023. http://www.theses.fr/2023ULILN060.

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L'électrification des véhicules joue un rôle essentiel dans la lutte contre le réchauffement climatique. En réponse à la croissance de plus en plus marquée des véhicules électrifiés sur le marché automobile mondial, de nouvelles technologies ont émergé pour satisfaire la demande. Les simulations Hardware-in-the-Loop de type Signal (S-HIL) et Puissance (P-HIL) sont déjà utilisées dans l'industrie automobile pour tester différents composants et sous-systèmes de nouvelle génération avant leur intégration dans le prototype final, mais leur potentiel reste sous-exploité. Afin de favoriser leur util

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23

Driscoll, Scott Crawford. "The Design and Qualification of a Hydraulic Hardware-in-the-Loop Simulator." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7132.

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The goal of this work was to design and evaluate a hydraulic Hardware-in-the-Loop (HIL) simulation system based around electric and hydraulic motors. The idea behind HIL simulation is to install real hardware within a physically emulated environment, so that genuine performance can be assessed without the expense of final assembly testing. In this case, coupled electric and hydraulic motors were used to create the physical environment emulation by imparting flows and pressures on test hardware. Typically, servo-valves are used for this type of hydraulic emulation, and one of the main purpos

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24

Hanono, Silvina Zimi. "InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11855.

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25

Marko, Vekić. "Нови поступак за развој управљачких склопова енергетске електронике заснован на емулацији у стварном времену". Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2014. http://dx.doi.org/10.2298/NS20131223VEKIC.

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У тези je предложен поступак развоја управљачких склопова енергетскеелектронике заснован на технологији Hardware In the Loop. Подробно јеописан предложени емулатор са нагласком на специфичноммоделовању погодном за извршење у стварном времену што јепредуслов веродостојности. Сама веродостојност је проверенапоређењем резултата са симулацијом, као и са измереним резултатимау неколико стварних погона. Затим је поступак развоја управљачкихсклопова подробно објашњен на примеру развоја и испитивања једногновог контролног алгоритма за повезивање синхроног генератора наелектричну мрежу.<br>U tezi je pr

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26

Noon, John Patrick. "Development of a Power Hardware-in-the-Loop Test Bench for Electric Machine and Drive Emulation." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/101498.

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This work demonstrates the capability of a power electronic based power hardware-inthe- loop (PHIL) platform to emulate electric machines for the purpose of a motor drive testbench with a particular focus on induction machine emulation. PHIL presents advantages over full-hardware testing of motor drives as the PHIL platform can save space and cost that comes from the physical construction of multiple electric machine test configurations. This thesis presents real-time models that were developed for the purpose of PHIL emulation. Additionally, real-time modeling considerations are presented as

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27

Schmitt, Alexander [Verfasser]. "Hochdynamische Power Hardware-in-the-Loop Emulation hoch ausgenutzter Synchronmaschinen mit einem Modularen-Multiphasen-Multilevel Umrichter / Alexander Schmitt." Karlsruhe : KIT Scientific Publishing, 2017. http://www.ksp.kit.edu.

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28

Serdar, Usenmez. "Design Of An Integrated Hardware-in-the-loop Simulation System." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/2/12612051/index.pdf.

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This thesis aims to propose multiple methods for performing a hardware-in-the-loop simulation, providing the hardware and software tools necessary for design and execution. For this purpose, methods of modeling commonly encountered dynamical system components are explored and techniques suitable for calculating the states of the modeled system are presented. Modules and subsystems that enable the realization of a hardware-in-the-loop simulation application and its interfacing with external controller hardware are explained. The thesis also presents three different simulation scenarios. Solutio

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Levrini, Giacomo. "Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/22105/.

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In the next 10 years, a radical upgrade is expected for the Large Hadron Collider focused in achieving the highest values in the instantaneous and integrated luminosity. Both the subdetectrors of the experiments and their data acquisition systems will need an upgrade. For the Phase-II upgrade of the Trigger and Data Acquisition System (TDAQ) of the ATLAS experiment a common platform has been created to share the common firmware, software and tools that are ongoing and that will come in the next years within the ATLAS TDAQ collaboration. The environment includes a set of design procedures, a

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Varais, Andy. "Modèles à échelle réduite en similitude pour l'ingénierie système et l'expérimentation simulée "temps compacté" : application à un microréseau incluant un stockage électrochimique." Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0007/document.

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Cette thèse a été réalisée en collaboration avec la société SCLE SFE (Groupe ENGIE) et le laboratoire Laplace. Elle porte sur le développement d’une méthodologie permettant d’élaborer des modèles dits « en similitude », à échelle de puissance et de temps réduites. Ces modèles peuvent servir pour l’analyse des systèmes mais ils sont en particulier utiles pour l’expérimentation en temps réel des systèmes énergétiques. En effet, les expérimentations sont très souvent menées à échelle réduite pour des questions de taille, de coût,… Certaines parties de ces expérimentations peuvent être « émulées »

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MONTEIRO, Heron Aragão. "Emulação de circuitos quânticos em Placa FPGA." Universidade Federal de Campina Grande, 2012. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/1368.

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Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-06T19:17:03Z No. of bitstreams: 1 HERON ARAGÃO MONTEIRO - DISSERTAÇÃO PPGCC 2012..pdf: 15948168 bytes, checksum: e445512265f530700a45c3924f68aa02 (MD5)<br>Made available in DSpace on 2018-08-06T19:17:03Z (GMT). No. of bitstreams: 1 HERON ARAGÃO MONTEIRO - DISSERTAÇÃO PPGCC 2012..pdf: 15948168 bytes, checksum: e445512265f530700a45c3924f68aa02 (MD5) Previous issue date: 2012-05-31<br>Com o avanço da nanotecnologia, a computação quântica tem recebido grande destaque no meio científico. Utilizando os fundamentos da mecânica q

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Olivier, Paul L. R. "Improving Hardware-in-the-loop Dynamic Security Testing For Linux-based Embedded Devices." Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS049.

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Les techniques d'analyse dynamique ont prouvé leur efficacité dans l'évaluation de la sécurité. Il est en revanche nécessaire de pouvoir exécuter le code à analyser et c'est souvent un défi pour les firmware dont la plupart sont profondément intégrés à l’architecture matérielle du système embarqué. L'émulation permet d’exécuter une grande partie du code mais se retrouve rapidement limitée lorsqu’il est nécessaire d'interagir avec des composants spécialisés. Pour cela, l’approche d'émulation partielle, ou hardware-in-the-loop, offre plusieurs avantages: transférer les accès aux matériels qui so

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Beckert, René [Verfasser], Wolfram [Gutachter] Hardt, Ulrich [Gutachter] Heinkel, Christophe [Gutachter] Bobda, Wolfram [Akademischer Betreuer] Hardt, and Ulrich [Akademischer Betreuer] Heinkel. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration / René Beckert ; Gutachter: Wolfram Hardt, Ulrich Heinkel, Christophe Bobda ; Wolfram Hardt, Ulrich Heinkel." Dresden : TUDpress, 2013. http://d-nb.info/1214245722/34.

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Mehrnoosh, Behzad. "Comparing Analog and Digital Non-Linear Sonic Signatures : an Investigation on Creative Application and Subjective Perception using the Universal Audio 1176 FET Compressor." Thesis, Luleå tekniska universitet, Institutionen för ekonomi, teknik, konst och samhälle, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-84598.

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Historically, compression was primarily used as a preventative measure to reduce the risk of clipping or overloading equipment in the recording signal chain. Research on the topic has revealed that modern production applications more commonly include utilizing compression as a creative effect, to impart distortion, manipulate timbre, and modify transients, rather than to control the dynamic range of audio signals. It has also been found that specific compressors are regularly chosen for the sonic signatures that they impart onto audio material. To evaluate the quality of a digitally modeled em

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Santos, Vitor Alexandre. "Caso de estudo de sistema de emulação em hardware para aplicação com controlador lógico programável." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/2720.

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Este trabalho consiste em um caso de estudo de um emulador de planta industrial implementado em FPGA (Field Programmable Gate Array), a fim de simulação de sistemas em conjunto com um CLP (Controlador Lógico Programável). Com isso, fundamentado na indústria de manufatura, são confrontados resultados práticos de um protótipo de processo industrial com os resultados de um modelo aplicado em FPGA. Dessa maneira, tem-se como objetivo o auxílio em testes em níveis de validação de aplicação em desenvolvimento, aproximação de condições de chão de fábrica, otimização de controle de processo e treiname

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Souza, Igor Dias Neto de. "Controle digital com malha dupla de tensão aplicado a um conversor formador de rede." Universidade Federal de Juiz de Fora (UFJF), 2017. https://repositorio.ufjf.br/jspui/handle/ufjf/4083.

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Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-18T14:49:13Z No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5)<br>Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-18T14:50:11Z (GMT) No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5)<br>Made available in DSpace on 2017-04-18T14:50:11Z (GMT). No. of bitstreams: 1 igordiasnetodesouza.pdf: 13872772 bytes, checksum: 45517d7a6da7ae06ecacec6a7fb7ebd8 (MD5) Previous is

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Guimarães, Marcelo Alves. "Transporte TDM em redes GPON." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-07042011-152547/.

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Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos

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BOUKADIDA, Yassine. "The i-motor: a system for end-of-line testing of electric drives for vehicles." Doctoral thesis, Università degli studi di Cassino, 2021. http://hdl.handle.net/11580/83957.

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This work is developed within a current trend aimed at time simulation-based testing systems, especially those dedicated to complex process where different sub-processes interact with different dynamics. The Hardware in the loop (HIL) is currently considered as a viable candidate to fulfill the requirements of real time simulation for the testing of complex systems. Within this trend, a HIL simulation system dedicated to the testing of a variable speed traction drive is developed. It incorporates a power system made up of two DC-AC converters connected through their AC sides by a three

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Li, Ming-You, and 李明祐. "Hardware Implementation of Analog Emulator Based on Wave Digital Filters." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/46414417801929081152.

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碩士<br>國立中央大學<br>電機工程學系<br>105<br>Modern System-on-Chip (SOC) designs usually contain analog and digital circuits. However, it is difficult to simulate them together because the design and verification processes are quite different for analog and digital circuits in traditional design flow. In order to provide a rapid and reliable verification method, we adopt Wave Digital Filter (WDF) theory to map resistors, capacitors, inductors and voltage source to wave domain one-by-one and connect them with serial or parallel adaptors. By this way, analog circuits can be transformed to digital circuits a

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"Digital implementation of an upstream DOCSIS QAM modulator and channel emulator." Thesis, 2014. http://hdl.handle.net/10388/ETD-2015-06-1783.

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The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century. At the dawn of the internet the dominant mode of access

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Mazumdar, Sushmit. "Hardware Emulation of a Long Transmission Line by High Frequency Power Electronic Converter for the study of Switching Transients." Thesis, 2019. https://etd.iisc.ac.in/handle/2005/5099.

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To ensure smooth functioning of the grid, the reliability and robustness of the power system equipment needs to be precisely evaluated during their development process. But direct on- eld tests of most of the equipment are not possible. This urges for having an emulated environment which will operate in real-time thereby capturing all the physical phenomenon of the Hardware Under Test (HUT). The control and pro- tection equipments are generally tested by Hardware-In-The-Loop (HIL) technology, where a Real-Time Simulator (RTS) implemented on a digital platform, interacts with the HUT in

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Πρίσκας, Θεόδωρος. "Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs". Thesis, 2012. http://hdl.handle.net/10889/5575.

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Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL. H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια: Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4]. Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10]. Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες κ

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Lee, Chao-Cheng, and 李朝丞. "Emulation-Based Open-Hardware Course Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/by735u.

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碩士<br>國立臺灣師範大學<br>資訊教育研究所<br>107<br>This study developed task-specific software to emulate the behaviors of an open-hardware. Students could test-run their programs on the emulation software before transmit it into the hardware. The Quasi-experimental design was implemented and the participants were a class of 8th graders in a class with a total of 45 students. Among them, 23 students served as the experiment group using emulation in programming, whereas the other 22 students served as the control group without using emulation. The experiment lasted for five weeks with a total of 5 hours. Data

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Wieler, Richard. "Emulation systems based on reconfigurable hardware devices." 1995. http://hdl.handle.net/1993/19040.

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Peng, Fei, and 彭飛. "OpenCL 2.0 Enabled HSA Hardware Platform Emulation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/38981095842033467767.

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碩士<br>國立清華大學<br>資訊工程學系<br>103<br>Heterogeneous System Architecture (HSA) is an open industry standard that tightly coupled the CPU with variety accelerators and also designed to support data-parallel programming models. Although there is a HSA-compatible machine, it is still not the HSA fully supported machine. A lot of software components using HSA is in development, so it is useful by providing an emulation environment for verifying HSA software components and tool-chains In this paper, we introduce a HSA emulation platform that can support OpenCL 2.0, which is based on HSAemu framework.

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LI, MENG-LIN, and 李孟霖. "Resource Optimization for Hardware Generation of WDF-based Circuit Emulators." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/r29jm6.

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碩士<br>國立中央大學<br>電機工程學系<br>107<br>With the advance of semiconductor technologies, the design of Very-Large-Scale Integration (VLSI) circuits becomes more complex. System-on-Chip (SOC) has become the main stream of VLSI design style . Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter(WDF) theorem to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit charact

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Sá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Master's thesis, 2011. http://hdl.handle.net/10216/63317.

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Sá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Dissertação, 2011. http://hdl.handle.net/10216/63317.

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Lee, Tsing Gen, and 李清根. "EMPAR: An Interactive Design Environment for Hardware Emulation Applications." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/45774630746461439061.

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Wu, Cheng-Chang, and 吳誠昌. "A Real-Time Emulation Hardware Platform for Channel Decoder." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/65843466950607930475.

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碩士<br>國立清華大學<br>電機工程學系<br>91<br>ABSTRACT In modern communication systems, the interference of the channel noise is unavoidable when we transmit data. To overcome this problem, many theories about channel coding have been developed. Firstly, the data in the transmitter is coded, and then transmitted to the receiver via channel. Though it may be corrupted by the channel interference, the decoder can still get the decoded data that is like the original data. The most commonly used error control coding is the convolutional code in communication systems. The Viterbi algorithm is a Maxim

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