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Journal articles on the topic 'Hardware language description'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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1

PARK, SUNGWOO, and HYEONSEUNG IM. "A calculus for hardware description." Journal of Functional Programming 21, no. 1 (2010): 21–58. http://dx.doi.org/10.1017/s0956796810000249.

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AbstractIn efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a calculus, called lλ (linear lambda), which may serve as an intermediate f

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2

Shahdad, Lipsett, Marschner, Sheehan, and Cohen. "VHSIC Hardware Description Language." Computer 18, no. 2 (1985): 94–103. http://dx.doi.org/10.1109/mc.1985.1662802.

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3

Gai, S., and A. Lioy. "A multilevel hardware description language." Microprocessing and Microprogramming 25, no. 1-5 (1989): 183–87. http://dx.doi.org/10.1016/0165-6074(89)90193-2.

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4

Acharya, Anurag, Sudipta Bhawmik, C. R. K. Prasad, and P. Palchaudhuri. "KIDLAN: A hardware description language." Microprocessing and Microprogramming 26, no. 1 (1989): 1–13. http://dx.doi.org/10.1016/0165-6074(89)90276-7.

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5

Sciuto, D. "VHDL( VHSIC Hardware Description Language)." Journal of Systems Architecture 42, no. 2 (1996): 95–96. http://dx.doi.org/10.1016/1383-7621(96)00015-x.

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6

Collis, G. V., and E. J. Kappos. "Occam as a hardware description language." Software Engineering Journal 2, no. 6 (1987): 213. http://dx.doi.org/10.1049/sej.1987.0028.

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7

Lieberherr, Karl J. "Toward a Standard Hardware Description Language." IEEE Design & Test of Computers 2, no. 1 (1985): 55–62. http://dx.doi.org/10.1109/mdt.1985.294685.

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8

Mita, Rosario, and Gaetano Palumbo. "Microprocessor design using hardware description language." European Journal of Engineering Education 33, no. 4 (2008): 425–32. http://dx.doi.org/10.1080/03043790802253384.

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9

Saini, J. S. "MODLAN: a hardware module description language." Microprocessors and Microsystems 9, no. 7 (1985): 359. http://dx.doi.org/10.1016/0141-9331(85)90324-2.

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10

Kuszynski, C. A., T. Busfield, A. M. Koelmans, M. R. McLauchlan, and D. J. Kinniment. "Graphical representation of a hardware description language." IEE Proceedings E Computers and Digital Techniques 137, no. 6 (1990): 462. http://dx.doi.org/10.1049/ip-e.1990.0058.

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11

Raczkowycz, Julian. "Modeling with an analog hardware description language." Microelectronics Journal 26, no. 5 (1995): xix. http://dx.doi.org/10.1016/0026-2692(95)90049-7.

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12

Felzmann, Isaías B., Matheus M. Susin, Liana Duenha, Rodolfo Azevedo, and Lucas F. Wanner. "ADeLe: A description language for approximate hardware." Future Generation Computer Systems 102 (January 2020): 245–58. http://dx.doi.org/10.1016/j.future.2019.07.073.

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13

Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.

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Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.

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14

Csopaki, G. "Hardware description language for specification of digital systems." Microprocessing and Microprogramming 25, no. 1-5 (1989): 151–55. http://dx.doi.org/10.1016/0165-6074(89)90188-9.

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15

Sziray, József, and Zsolt Nagy. "Opart: A hardware-description language for test generation." Microprocessing and Microprogramming 32, no. 1-5 (1991): 525–30. http://dx.doi.org/10.1016/0165-6074(91)90396-b.

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16

Schulze, S., and S. Sawitzki. "Processor design using a functional hardware description language." Microprocessors and Microsystems 36, no. 8 (2012): 676–94. http://dx.doi.org/10.1016/j.micpro.2012.05.006.

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17

Al-Junaid, Hessa. "Modeling Single Flexible Link Using Hardware Description Language." International Journal of Computing and Digital Systems 5, no. 3 (2016): 283–89. http://dx.doi.org/10.12785/ijcds/050308.

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18

TANAHASHI, Shinya, Toshiro KUTSUWA, and Ken-ichi KOBORI. "Evaluation of Various Adders by Using Hardware Description Language." Journal of Japan Institute of Electronics Packaging 2, no. 2 (1999): 132–34. http://dx.doi.org/10.5104/jiep.2.132.

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19

Collis, G. V., and M. D. Edwards. "Automatic hardware synthesis from a behavioural description language: occam." Microprocessing and Microprogramming 18, no. 1-5 (1986): 243–50. http://dx.doi.org/10.1016/0165-6074(86)90051-7.

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20

Elkeelany, Omar, and Vivekanand S. Todakar. "Data Archival to SD Card Via Hardware Description Language." IEEE Embedded Systems Letters 3, no. 4 (2011): 105–8. http://dx.doi.org/10.1109/les.2011.2168804.

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21

Mantooth, A., A. Francis, Y. Feng, and W. Zheng. "Modelling tools built upon the hardware description language foundation." IET Computers & Digital Techniques 1, no. 5 (2007): 519. http://dx.doi.org/10.1049/iet-cdt:20050213.

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22

Khan, Wilayat, David Sanan, Zhe Hou, and Liu Yang. "On embedding a hardware description language in Isabelle/HOL." Design Automation for Embedded Systems 23, no. 3-4 (2019): 123–51. http://dx.doi.org/10.1007/s10617-019-09226-1.

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23

Mrc˘arica, Z˘, V. B. Litovski, and H. Detter. "Modelling and simulation of microsystems using hardware description language." Microsystem Technologies 3, no. 2 (1997): 80–85. http://dx.doi.org/10.1007/s005420050060.

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24

Li, Juncao, Nicholas T. Pilkington, Fei Xie, and Qiang Liu. "Embedded architecture description language." Journal of Systems and Software 83, no. 2 (2010): 235–52. http://dx.doi.org/10.1016/j.jss.2009.09.043.

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25

Harrold, S. J. "Using a Hardware Description Language to Teach Top-Down Design Methodology for IC Design." International Journal of Electrical Engineering & Education 30, no. 3 (1993): 269–74. http://dx.doi.org/10.1177/002072099303000309.

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Using a hardware description language to teach top-down design methodology for IC design This paper described how a hardware description language can be used to give students experience in top-down IC design and achieve a reasonably demanding hardware realisation within an acceptable time-scale.

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26

KumarN, Naveen, Rohith S, and H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language." International Journal of Computer Applications 102, no. 6 (2014): 8–13. http://dx.doi.org/10.5120/17817-8752.

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27

Mita, Rosario, and Gaetano Palumbo. "Modeling of analog blocks by using standard hardware description language." Analog Integrated Circuits and Signal Processing 48, no. 2 (2006): 107–20. http://dx.doi.org/10.1007/s10470-006-7225-7.

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28

Ancona, M., A. Clematis, L. de Floriani, and E. Puppo. "A hardware description language based on a hierarchical graph model." Microprocessing and Microprogramming 20, no. 1-3 (1987): 183–88. http://dx.doi.org/10.1016/0165-6074(87)90139-6.

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29

Kobayashi, Kazuo, Haruo Wakabayashi, and Yoshiaki Wakimura. "Schematic description language for a hardware top-down design approach." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 74, no. 6 (1991): 85–95. http://dx.doi.org/10.1002/ecjc.4430740609.

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30

Duley, Adam, Chris Spandikow, and Miryung Kim. "Vdiff: a program differencing algorithm for Verilog hardware description language." Automated Software Engineering 19, no. 4 (2012): 459–90. http://dx.doi.org/10.1007/s10515-012-0107-6.

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31

Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.

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To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust

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32

Заризенко, Инна Николаевна, та Артём Евгеньевич Перепелицын. "АНАЛИЗ СРЕДСТВ И ТЕХНОЛОГИЙ РАЗРАБОТКИ FPGA КАК СЕРВИС". RADIOELECTRONIC AND COMPUTER SYSTEMS, № 4 (25 грудня 2019): 88–93. http://dx.doi.org/10.32620/reks.2019.4.10.

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This article has analyzed the most effective integrated development environments from leading programmable logical device (PLD) manufacturers. Heterogeneous calculations and the applicability of a general approach to the description of hardware accelerator designs are considered. An analytical review of the use of the OpenCL language in the construction of high-performance FPGA-based solutions is performed. The features of OpenCL language usage for heterogeneous computing for FPGA-based accelerators are discussed. The experience of a unified description of projects for solutions based on CPU,

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33

Hartenstein, R. W., and K. Lemmert. "A CAD tool box for VLSI around a hardware description language." Microprocessing and Microprogramming 18, no. 1-5 (1986): 99–105. http://dx.doi.org/10.1016/0165-6074(86)90033-5.

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34

Miriampally, Venkata Raghavendra. "Simulation of PCI Express™ Transaction Layer Using Hardware Description Language." International Journal of Informatics and Communication Technology (IJ-ICT) 4, no. 1 (2015): 7. http://dx.doi.org/10.11591/ijict.v4i1.pp7-12.

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<p>PCI Express is a high-speed serial connection that operates more like a network than a bus.<strong> </strong>PCI Express will serve as a general purpose I/O interconnects for a wide variety of future computing and communications platforms.<strong> </strong>PCI Express (PCIe) is implemented with a split-transaction protocol that provides more bandwidth and is compatible with existing operating systems. PCI Express has three discrete logical layers: the Transaction Layer, the Data Link Layer, and the Physical Layer. This paper analyze and simulates the function o

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35

Yanbing Li and M. Leeser. "HML, a novel hardware description language and its translation to VHDL." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 1 (2000): 1–8. http://dx.doi.org/10.1109/92.820756.

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36

Peterson, Gregory D., and John C. Willis. "High-Performance Hardware Description Language simulation: Modeling Issues and Recommended Practices." SIMULATION 72, no. 3 (1999): 148. http://dx.doi.org/10.1177/003754979907200303.

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37

Dickinson, Brian. "VHDL '92: The new features of the VHDL hardware description language." Microprocessors and Microsystems 19, no. 2 (1995): 106–7. http://dx.doi.org/10.1016/0141-9331(95)90002-0.

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38

O'Donnell, John T. "Connecting the Dots: Computer Systems Education using a Functional Hardware Description Language." Electronic Proceedings in Theoretical Computer Science 106 (January 20, 2013): 20–39. http://dx.doi.org/10.4204/eptcs.106.2.

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39

Navabi, Zainalabedin, and Kia Doroudi. "Compiling an RT level hardware description language into layout of NMOS cells." Microprocessing and Microprogramming 18, no. 1-5 (1986): 123–29. http://dx.doi.org/10.1016/0165-6074(86)90035-9.

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40

Christen, E., and K. Bakalar. "VHDL-AMS-a hardware description language for analog and mixed-signal applications." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 46, no. 10 (1999): 1263–72. http://dx.doi.org/10.1109/82.799677.

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41

Robson, A. P., and D. J. Kinniment. "SIMSTRICT: A Behavioural Simulator for Use with the STRICT Hardware Description Language." Computer Journal 35, no. 6 (1992): 651–54. http://dx.doi.org/10.1093/comjnl/35.6.651.

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42

Assaad, Maher. "A Hardware Description Language-Based Serial Link for Multicores SoC/NoC Interconnect." Journal of Low Power Electronics 14, no. 1 (2018): 28–37. http://dx.doi.org/10.1166/jolpe.2018.1544.

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43

Narendran, S., and J. Selvakumar. "Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling." Advances in Condensed Matter Physics 2018 (May 27, 2018): 1–5. http://dx.doi.org/10.1155/2018/2683723.

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We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Through our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to find which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the suppl

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44

Soe, Ei Phyu, Myint Myint Soe, and Htet Htet Yi. "Analysis and Synthesis of Elevator Controller Based On VHSIC Hardware Description Language." International Journal of Scientific and Research Publications (IJSRP) 9, no. 4 (2019): p8806. http://dx.doi.org/10.29322/ijsrp.9.04.2019.p8806.

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45

Girczyc, E. F., R. J. A. Buhr, and J. P. Knight. "Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 4, no. 2 (1985): 134–42. http://dx.doi.org/10.1109/tcad.1985.1270106.

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46

Dimopoulos, Alexandros C., Christos Pavlatos, and George Papakonstantinou. "Hardware Inexact Grammar Parser." International Journal of Pattern Recognition and Artificial Intelligence 31, no. 11 (2017): 1759025. http://dx.doi.org/10.1142/s021800141759025x.

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In this paper, a platform is presented, that given a Stochastic Context-Free Grammar (SCFG), automatically outputs the description of a parser in synthesizable Hardware Description Language (HDL) which can be downloaded in an FPGA (Field Programmable Gate Arrays) board. Although the proposed methodology can be used for various inexact models, the probabilistic model is analyzed in detail and the extension to other inexact schemes is described. Context-Free Grammars (CFG) are augmented with attributes which represent the probability values. Initially, a methodology is proposed based on the fact

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47

Mishra, Prabhat, Mahesh Mamidipaka, and Nikil Dutt. "Processor-memory coexploration using an architecture description language." ACM Transactions on Embedded Computing Systems 3, no. 1 (2004): 140–62. http://dx.doi.org/10.1145/972627.972634.

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48

Doligalski, Michał, and Marian Adamski. "Hierarchical Configurable Petri Net Modeling in VHDL." International Journal of Electronics and Telecommunications 58, no. 4 (2012): 397–402. http://dx.doi.org/10.2478/v10177-012-0054-y.

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Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL l

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49

Ploegaerts, W., D. Verkest, L. Claesen, and H. De Man. "Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language." Microprocessing and Microprogramming 27, no. 1-5 (1989): 279–86. http://dx.doi.org/10.1016/0165-6074(89)90060-4.

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50

Mahmudi, Ali, Sentot Achmadi, and Michael. "Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes." MATEC Web of Conferences 164 (2018): 01003. http://dx.doi.org/10.1051/matecconf/201816401003.

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In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

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