Journal articles: 'Hardware - Peripherals'

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Antara, Gede Krisnanda Juni. "Peripherals Using in Working Area." International Research Journal of Management, IT & Social Sciences 2, no. 5 (May 1, 2015): 7. http://dx.doi.org/10.21744/irjmis.v2i5.63.

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Peripherals is additional hardware who connected to the computer, usually with the aid of wires or now many wireless peripheral devices. These computer peripherals duty to help accomplish the task cannot be performed by hardware which is mounted inside the casing. These peripherals can be divided into 2 of the input and output peripherals. In daily activities, peripherals much help humanity though not much like the example Printer. Human previously prints using a typewriter that is very inefficient and after the invention of a machine that can print very fast then this machine that replaces the role of the previous cumbersome machine becomes very easy to use. In its development until now very much changed peripherals ranging in terms of composition and form very striking. For example a mouse which only consists of 1 buttons until now that could be a wireless

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Huang, Chun Ming, Kai Chao Yang, Yu Tsang Chang, Chien Ming Wu, and Shian Wen Chen. "A Tiny Development Platform with Virtualized Peripherals for Education of Embedded Software Design." Advanced Materials Research 748 (August 2013): 936–40. http://dx.doi.org/10.4028/www.scientific.net/amr.748.936.

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In the embedded software education, it is usually a burden to give every student a development board in the class due to limited budget. Besides, peripheral devices such as LCD panels also increase the cost. A cheap and flexible way is to use virtual embedded systems in the class. However, virtual systems cannot completely reflect the developing environment on real platforms. In this article, we propose the idea that combines the virtual and real embedded platforms. The proposed platform preserves the core of the hardware board, so that developers can design embedded software applications in the real developing environment. In addition, we eliminate the peripheral wires and connectors on hardware board and use virtual peripherals and peripherals on PC instead, such that designers can easily control and change peripherals. The proposed idea can significantly reduce cost and increase flexibility when teaching embedded software design. Moreover, the size of development board can be reduced as well. Without the restriction of peripheral connectors and devices, development boards become portable and more easy to use.

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An, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (January 20, 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.

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Although the RISC-V ISA has not been around for long, it is a processor architecture that has been highlighted by many businesses and individuals for its low-cost and rapid pace of development. They are open-source-synthesizable hardware processors with minimal functionality that is ideal for current IoT applications involving simple sensors and actuator controls. Due to some qualities of hardware, they can operate in areas where software programs and applications cannot be used whereas, these software programs that run on such hardware equally help in understanding how hardware operates. This paper, therefore, proposes and discusses the design, implementation, and internal verification and test platform for a Reduced Instruction Set Code-V’s (RISC-V) Instruction Set Architecture (ISA), using an interactive desktop program for a 32-bit single-cycle processor. This paper developed a system that functions as interactive assistance to RISC-V's ISA design and debugger using a more user-friendly desktop UI application. The uniqueness of this design is the flexibility of testing and debugging that is possible through either the software interface or through hardware peripherals such as Universal Asynchronous Receiver/Transmitter (UART) protocols in FPGA or even both. These peripherals allow users to view the contents of the register files and RAM being utilized by the implemented processor on the FPGA. The proposed desktop User Interface program monitors and controls the sequential processing and states of a 32-bit single-cycle RISC-V processor’s operation on an FPGA. Contents of the proposed processor’s registers and memory are displayed alongside other temporal or internal data. Internal components such as Program Counters (PC), Random Access Memory (RAM), are displayed all through the proposed User Interface (UI) program and also through various peripherals on the FPGA board. The software program is implemented using C# programing language through Microsoft Visual Studio 2019 Integrated Development Environment (IDE). The proposed hardware synthesizable processor core is implemented using Verilog Hardware Description Language (HDL) and synthesized with Xilinx Integrated Synthesis Environment (ISE) version 14.7. The proposed processor and its corresponding hardware test modules occupy 6476 Look-Up-Tables (LUT) and operate at a maximum frequency of 49MHz and its operation is verified on a Field Programmable Gate Array (FPGA). The proposed processor and its test platform can serve as a good educational tool as well as a help for processor design engineers both experienced and beginners.

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Khurshid, Anum, Sileshi Demesie Yalew, Mudassar Aslam, and Shahid Raza. "TEE-Watchdog: Mitigating Unauthorized Activities within Trusted Execution Environments in ARM-Based Low-Power IoT Devices." Security and Communication Networks 2022 (May 25, 2022): 1–21. http://dx.doi.org/10.1155/2022/8033799.

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Trusted execution environments (TEEs) are on the rise in devices all around us ranging from large-scale cloud-based solutions to resource-constrained embedded devices. With the introduction of ARM TrustZone-M, hardware-assisted trusted execution is now supported in IoT nodes. TrustZone-M provides isolated execution of security-critical operations and sensitive data-generating peripherals. However, TrustZone-M, like all other TEEs, does not provide a mechanism to monitor operations in the trusted areas of the device and software in the secure areas of an IoT device has access to the entire secure and nonsecure software stack. This is crucial due to the diversity of device manufacturers and component suppliers in the market, which manifests trust issues, especially when third-party peripherals are incorporated into a TEE. Compromised TEEs can be misused for industrial espionage, data exfiltration through system backdoors, and illegal data sharing. It is of utmost importance here that system peripheral behaviour in terms of resource access is in accordance with their intended usage that is specified during integration. We propose TEE-Watchdog, a lightweight framework that establishes MPU protections for secure system peripherals in TrustZone-enabled low-end IoT devices. TEE-Watchdog ensures blocking unauthorized peripheral accesses and logging of application misbehaviour running in the TEE based on a manifest file. We define lightweight specifications and structure for the application manifest file enlisting permissions for critical system peripherals using concise binary object representation (CBOR). We implement and evaluate TEE-Watchdog using a Musca-A2 test chipboard. Our microbenchmark evaluations on CPU time and RAM usage demonstrated the practicality of TEE-Watchdog. Securing the system peripherals using TEE-Watchdog protections induced a 1.4% overhead on the latency of peripheral accesses, which was 61 microseconds on our test board. Our optimized CBOR-encoded manifest file template also showed a decrease in manifest file size by 40% as compared to the standard file formats, e.g., JSON.

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Laney, Samuel R. "A General-Purpose Microcontroller-Based Framework for Integrating Oceanographic Sensors, Instruments, and Peripherals." Journal of Atmospheric and Oceanic Technology 34, no. 2 (February 2017): 415–27. http://dx.doi.org/10.1175/jtech-d-16-0069.1.

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AbstractSensors and instruments for basic oceanographic properties are becoming increasingly sophisticated, which both simplifies and complicates their use in field studies. This increased sophistication disproportionately affects smaller-scale observational efforts that are less likely to be well supported technically but which need to integrate instruments, sensors, and commonly needed peripheral devices in ways not envisioned by their manufacturers. A general-purpose hardware and software framework was developed around a widely used family of low-power microcontrollers to lessen the technical expertise and customization required to integrate sensors, instruments, and peripherals, and thus simplify such integration scenarios. Both the hardware and associated firmware development tools provide a range of features often required in such scenarios: serial data interfaces, analog inputs and outputs, logic lines and power-switching capability, nonvolatile storage of data and parameters for sampling or configuration, and serial communication interfaces to supervisory or telemetry systems. The microcontroller and additional components needed to implement this integration framework are small enough to encapsulate in standard cable splices, creating a small form factor “smart cable” that can be readily wired and programmed for a range of integration needs. An application programming library developed for this hardware provides skeleton code for functions commonly desired when integrating sensors, instruments, and peripherals. This minimizes the firmware programming expertise needed to apply this framework in many integration scenarios and thus streamlines the development of firmware for different field applications. Envisioned applications are in field programs where significant technical instrumentation expertise is unavailable or not cost effective.

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Vahid, Frank, Rilesh Patel, and Greg Stitt. "Propagating constants past software to hardware peripherals in fixed-application embedded systems." ACM SIGARCH Computer Architecture News 29, no. 5 (December 2001): 25–30. http://dx.doi.org/10.1145/563647.563654.

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Chrastecky, Libor, Jaromir Konecny, Martin Stankus, and Michal Prauzek. "A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module." Elektronika ir Elektrotechnika 25, no. 6 (December 6, 2019): 35–39. http://dx.doi.org/10.5755/j01.eie.25.6.24824.

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This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

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Jin, Fei, and Lian Yu Zhao. "Development and Implementation of a Bootloader Based on the Embedded Systems." Applied Mechanics and Materials 48-49 (February 2011): 419–22. http://dx.doi.org/10.4028/www.scientific.net/amm.48-49.419.

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This paper introduces design principles and steps of a bootloader, including the analysis of S3C2440A microprocess with its peripherals, hardware initialization process and the automatic loading mode and the steps of Shell command interpreter, and gives parts of the core codes and the experi- mental results.

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Bhatia, S. N. "A Comprehensive Interactive On-line Computer System for Research and Clinical Practice in Orthodontics." British Journal of Orthodontics 12, no. 1 (January 1985): 15–26. http://dx.doi.org/10.1179/bjo.12.1.15.

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An interactive on-line computer system for the measurement of cephalometric radiographs, and facial and plaster cast photographs is described. The details of the hardware (computer and peripherals) and software are provided. Numerical and graphical analysis and presentation of the resultant data are discussed. Many research and clinical applications of the system are outlined.

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Dubey, Awanish Chandra, and Anantha V. Subramanian. "Hardware in the Loop Simulation and Control Design for Autonomous Free Running Ship Models." Defence Science Journal 70, no. 4 (July 13, 2020): 469–76. http://dx.doi.org/10.14429/dsj.70.14926.

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This paper presents an hardware-in-the-loop (HIL) simulation system tool to test and validate an autonomous free running model system for ship hydrodynamic studies with a view to verification of the code, the control logic and system peripherals. The computer simulation of the plant model in real-time computer does not require the actual physical system and reduces the development cost and time for control design and testing purposes. The HIL system includes: the actual programmable embedded controller along with peripherals and a plant model virtually simulated in a real-time computer. With regard to ship controller design for ship model testing, this study describes a plant model for surge and a Nomoto first order steering dynamics, both implemented using Simulink software suit. The surge model captures a quasi-steady state relationship between surge speed and the propeller rpms, obtained from simple forward speed towing tank tests or derived analytically. The Nomoto first order steering dynamics is obtained by performing the standard turning circle test at model scale. The control logic obtained is embedded in a NI-cRIO based controller. The surge and steering dynamics models are used to design a proportional-derivative controller and an LQR controller. The controller runs a Linux based real-time operating system programmed using LabVIEW software. The HIL simulation tool allows for the emulation of standard ship hydrodynamic tests consisting of straight line, turning circle and zigzag to validate the combined system performance, prior to actual for use in the autonomous free-running tests.

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Wang, Hai Feng, Xu Ming Long, and Xiao Lu Cui. "The Design of Stereo Vision Autonomic Navigation Robot Based on SOC." Applied Mechanics and Materials 397-400 (September 2013): 1589–92. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1589.

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The design of an autonomous navigation robot is introduced. The robot system is used a SOC chip, which is used SPARC V8 architecture supporting the DSP instruction, integrated a hardware multiplier, a five level water treatment, a variety of bus and peripherals. The robot system includes stereo vision module, distance measurement module and motor drive module. It can achieve some functions such as real-time signal processing, target search, multi-window tracking and communication.

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Diaz, Kristian, and Ying-Khai Teh. "Design and Power Management of a Secured Wireless Sensor System for Salton Sea Environmental Monitoring." Electronics 9, no. 4 (March 25, 2020): 544. http://dx.doi.org/10.3390/electronics9040544.

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An embedded system composed of commercial off the shelf (COTS) peripherals and microcontroller. The system will collect environmental data for Salton Sea, Imperial Valley, California in order to understand the development of environmental and health hazards. Power analysis of each system features (i.e. Central Processing Unit (CPU) core, Input/Output (I/O) buses, and peripheral (temperature, humidity, and optical dust sensor) are studied. Software-based power optimization utilizes the power information with hardware-assisted power gating to control system features. The control of these features extends system uptime in a field deployed finite energy scenario. The proposed power optimization algorithm can collect more data by increasing system up time when compared to a Low Power Energy Aware Processing (LEAP) approach. Lastly, the 128 bit Advanced Encryption Standard (AES) algorithm is applied on the collected data using various parameters. A hidden peripheral requirement that must be considered during design are also noted to impact the efficacy of this method.

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Van Meter, Rodney. "A brief survey of current work on network attached peripherals (extended abstract)." ACM SIGOPS Operating Systems Review 30, no. 1 (January 1996): 63–70. http://dx.doi.org/10.1145/218646.218650.

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Qu, Ai Ling, Chang Lu Ma, and Bing Bing Qu. "The Design of the Minimum CPU System of TMS320VC54x." Applied Mechanics and Materials 721 (December 2014): 564–68. http://dx.doi.org/10.4028/www.scientific.net/amm.721.564.

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The minimum CPU system of TMS320VC54x DSP does not have redundant extended peripherals, it can work independently, perform real-time online simulation and burn program code. The paper mainly introduces the system design idea, the key points of design and matters needing attention, the paper offers the hardware circuit principle diagram of each unit of the minimum CPU system of TM320VC54x and the PCB diagram. The paper can work as the reference for the design of the minimum system of other CPU.

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Yang, Shang Wei, Shu Kun Cao, and Jia Jia. "Design of Five Axis Cooperation Machine Based on Motion Control Board." Applied Mechanics and Materials 300-301 (February 2013): 1463–66. http://dx.doi.org/10.4028/www.scientific.net/amm.300-301.1463.

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Abstract. PC-based open CNC system can fully take advantage of the computer's hardware and software resources, which can use a common high-level language: Visual C++ or Visual Basic to program. User can mix and use the standardized peripherals, application software flexibly, we use the self-developed five-axis CNC machine is experimental platform, which can develop open CNC system based on PC and motion control card. Using of five-axis machine motion control design based on "PC + motion control card" on Visual C++ platform.

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Fu, Xiao Guang, and Xiao Jun Wang. "Design and Realization of the Data Collecting System Based on USB Bus Line." Key Engineering Materials 428-429 (January 2010): 440–43. http://dx.doi.org/10.4028/www.scientific.net/kem.428-429.440.

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Universal serial bus (USB) is a kind of new bus interface specification, whose characteristics are convenience, high speed, easiness to expand, low cost and low disturbance, etc. So it is extremely fit to be the communication interface between host computer and peripherals. This paper is mainly about the development of data collecting system based on of USB, including hardware design, firmware design, equipment driver programming and application software design based on Windows driver model (WDM). This system works stable. Both the sampling precision and the data transmission speed have reached expected effect.

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Wiedenhoeft, Alex C. "The XyloPhone: toward democratizing access to high-quality macroscopic imaging for wood and other substrates." IAWA Journal 41, no. 4 (October 29, 2020): 699–719. http://dx.doi.org/10.1163/22941932-bja10043.

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Abstract One rate-limiting factor in the fight against illegal logging is the lack of powerful, affordable, scalable wood identification tools for field screening. Computer vision wood identification using smartphones fitted with customized imaging peripherals offers a potential solution, but to date, such peripherals suffer from one or more weaknesses: low image quality, lack of lighting control, uncontrolled magnification, unknown distortion, and spherical aberration, and/or no access to or publication of the system design. To address cost, optical concerns, and open access to designs and parameters, I present the XyloPhone, a 3D printed research quality macroscopic imaging attachment adaptable to virtually any smartphone. It provides a fixed focal distance, exclusion of ambient light, selection of visible light or UV illumination, uses the lens from a commercially available loupe, is powered by a rechargeable external battery, is fully open-sourced, at a price point of less than USD 110 is a highly affordable tool for the laboratory or the field, and can serve as the foundational hardware for a scalable field-deployable computer vision wood identification system.

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Ferguson, F. Joel. "Microprocessor Interfacing and the 68000: Peripherals and systems." Microprocessors and Microsystems 13, no. 10 (December 1989): 674. http://dx.doi.org/10.1016/0141-9331(89)90078-1.

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Rez, Peter, and D. J. Fathers. "Computer system architecture for image and spectral processing." Proceedings, annual meeting, Electron Microscopy Society of America 45 (August 1987): 92–95. http://dx.doi.org/10.1017/s0424820100125415.

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In this paper we shall discuss digital imaging and spectroscopy systems from the perspective of a system designer and we shall concentrate on those design choices that limit performance in microscopy and analysis applications. The hardware of a computer system can be broken down into three main components. These are the processor which performs arithmetic and logical operations, the memory for storing data and instructions and the peripherals for long term data storage (disks, tapes) and communication with the outside world. Linking these components is a data highway or bus for passing digital information from one section of the machine to another. A good definition of a bus is a set of interconnections with a defined procedure (protocol) for information transmission. In many small systems the bus is not only a set of electrical connections but is also an enclosure (a backplane) into which the different modules (processor, memory, peripheral controllers) are added.

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DEL CAMPO, INÉS, JAVIER ECHANOBE, KOLDO BASTERRETXEA, and GUILLERMO BOSQUE. "SCALABLE ARCHITECTURE FOR HIGH-SPEED MULTIDIMENSIONAL FUZZY INFERENCE SYSTEMS." Journal of Circuits, Systems and Computers 20, no. 03 (May 2011): 375–400. http://dx.doi.org/10.1142/s0218126611007359.

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This paper presents a scalable architecture suitable for the implementation of high-speed fuzzy inference systems on reconfigurable hardware. The main features of the proposed architecture, based on the Takagi–Sugeno inference model, are scalability, high performance, and flexibility. A scalable fuzzy inference system (FIS) must be efficient and practical when applied to complex situations, such as multidimensional problems with a large number of membership functions and a large rule base. Several current application areas of fuzzy computation require such enhanced capabilities to deal with real-time problems (e.g., robotics, automotive control, etc.). Scalability and high performance of the proposed solution have been achieved by exploiting the inherent parallelism of the inference model, while flexibility has been obtained by applying hardware/software codesign techniques to reconfigurable hardware. Last generation reconfigurable technologies, particularly field programmable gate arrays (FPGAs), make it possible to implement the whole embedded FIS (e.g., processor core, memory blocks, peripherals, and specific hardware for fuzzy inference) on a single chip with the consequent savings in size, cost, and power consumption. As a prototyping example, we implemented a complex fuzzy controller for a vehicle semi-active suspension system composed of four three-input FIS on a single FPGA of the Xilinx's Virtex 5 device family.

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Lv, Qian, and Li Gong Cui. "FPGA Verification for the OR1200 Subsystem in AVS-SoC." Advanced Materials Research 651 (January 2013): 807–11. http://dx.doi.org/10.4028/www.scientific.net/amr.651.807.

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This paper adopts a completely open-source OR1200 to development the CPU subsystem in AVS-SoC video decoder. Through the reasonable optimization and configuration for the core and its peripherals, it greatly enhanced the AVS chip’s reusability and integration level. At first, the author successfully completed the simulation in RTL-level. And then for the OR1200 can be better used in AVS video decoder chip, designers set up a verification platform for OR1200 subsystem on FPGA board. The author elaborated on the process of software design and hardware transplant from ASIC to FPGA, and then verified and optimized the performance for this CPU subsystem. Setting up AVS decoding system on FPGA, the project can software/hardware co-verify the video decoder, which will greatly accelerate the SoC chip’s development. Through the verification on FPGA board, testing for OR1200-based system has achieved the desired results.

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Zhang, Kun, and Xi Wei Peng. "Design of Human Machine Interface Based on ARM and Linux." Applied Mechanics and Materials 241-244 (December 2012): 2714–17. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2714.

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In order to provide more convenient options for users and developers, the design of Human Machine Interface (HMI) based on ARM and embedded Linux is put forward. It makes full use of multiple peripherals of ARM and flexibility of Linux OS. Firstly, hardware design of the HMI system is presented. Then methods of embedded Linux transplanting and the device drivers programming are discussed. Finally, running results and applications of the designed HMI are considered. The design combines the features of traditional HMI and Micro Control Unit (MCU) HMI, including low cost, rich interfaces and easy programming.

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Wu, Xun, Yue Song Mei, Jian Qiao Yu, Tian Peng Yu, and Jing Xu Li. "A Design of UART Serial Communication between the TMS320C6748 DSP and PC." Applied Mechanics and Materials 380-384 (August 2013): 3657–60. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3657.

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The digital signal processor (DSP: Digital Signal Proceeding) are widely used in industrial, military, communications and the other fields, so the research and design work about DSP is one of the hot spots of scholars and research. Communication and data transfer between the DSP and peripherals is one of the DSP function in the process of using which is the basic but important. This paper introduces a TMS320C6748 DSP with PC serial communication method based on the UART module. The hardware connection and software programming were highlights description. Finally, this paper gives some key code about TMS320C6748 DSP and PC serial communication programming.

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Jones, Julie A., and T. Kiki Widjaja. "Electronic Human Factors Guide for Aviation Maintenance." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 39, no. 1 (October 1995): 71–74. http://dx.doi.org/10.1177/154193129503900117.

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Technological advances in the area of computer software, hardware and peripherals have made digital information technology feasible. The Federal Aviation Administration Office of Aviation Medicine has been investigating the application of such technology. The overall goal is to increase accessibility and to improve distribution of Human Factors research reports and information to the aviation maintenance industry. The latest digital documentation project is the Electronic Human Factors Guide for Aviation Maintenance (E-Guide). The E-Guide is a hypermedia version of the Human Factors Guide for Aviation Maintenance (the Guide) which is described elsewhere in this symposium. This paper describes the design goals, key features, and future plans for the E-Guide.

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Merchan-Villalba, Luis Ramon, Jose Merced Lozano-Garcia, Diego Armando de Jesus Gutierrez-Torres, Juan Gabriel Avina-Cervantes, and Alejandro Pizano-Martinez. "Four-Step Current Commutation Strategy for a Matrix Converter Based on Enhanced-PWM MCU Peripherals." Electronics 8, no. 5 (May 15, 2019): 547. http://dx.doi.org/10.3390/electronics8050547.

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In this paper, an efficient implementation of the four-step current commutation technique for controlling bidirectional power switches in a Matrix Converter (MC) is proposed. This strategy is based on the enhanced pulse width modulation peripheral included in the C 2000 Delfino 32-bit microcontroller of Texas Instruments. By tuning the algorithmic parameters contained in this module, the four-step commutation process is carried out on the Microcontroller Unit (MCU) without overloading the full complex processor and avoiding the use of additional special hardware such as Field-Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD) when controlling the MC. The algorithm is implemented on the TMS320F28379D MCU and operationally validated on an MC prototype, where the functionality of the proposal is demonstrated.

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Dushku, Edlira, Jeppe Hagelskjær Østergaard, and Nicola Dragoni. "Memory Offloading for Remote Attestation of Multi-Service IoT Devices." Sensors 22, no. 12 (June 8, 2022): 4340. http://dx.doi.org/10.3390/s22124340.

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Remote attestation (RA) is an effective malware detection mechanism that allows a trusted entity (Verifier) to detect a potentially compromised remote device (Prover). The recent research works are proposing advanced Control-Flow Attestation (CFA) protocols that are able to trace the Prover’s execution flow to detect runtime attacks. Nevertheless, several memory regions remain unattested, leaving the Prover vulnerable to data memory and mobile adversaries. Multi-service devices, whose integrity is also dependent on the integrity of any attached external peripheral devices, are particularly vulnerable to such attacks. This paper extends the state-of-the-art RA schemes by presenting ERAMO, a protocol that attests larger memory regions by adopting the memory offloading approach. We validate and evaluate ERAMO with a hardware proof-of-concept implementation using a TrustZone-capable LPC55S69 running two sensor nodes. We enhance the protocol by providing extensive memory analysis insights for multi-service devices, demonstrating that it is possible to analyze and attest the memory of the attached peripherals. Experiments confirm the feasibility and effectiveness of ERAMO in attesting dynamic memory regions.

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Mohanram, Praveen, Alice Passarella, Elena Zattoni, Roberto Padovani, Niels König, and Robert H. Schmitt. "5G-Based Multi-Sensor Platform for Monitoring of Workpieces and Machines: Prototype Hardware Design and Firmware." Electronics 11, no. 10 (May 19, 2022): 1619. http://dx.doi.org/10.3390/electronics11101619.

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In this paper, we introduce a 5G-based multi-sensor platform for monitoring workpieces and machines. The prototype is realized within the EU-funded 5G-SMART project, which aims to enable smart manufacturing through 5G, demonstrating and validating new generation network technology in industrial processes. There are already state-of-the-art solutions, but with drawbacks such as limited flexibility, brief real-time capability, and sensors aimed at single applications. The 5G-SMART multi-sensor platform is designed to overcome these points and meet the requirements of Industry 4.0. The device is equipped with different sensors to acquire multiple data from workpieces and machines of the shop floor, wirelessly connected by 5G to the factory cloud. A hardware design description of the prototype is provided, focusing on the electronic components and their interaction with the microcontroller. Verification of the correct functioning of the board is given, with a basic library for the main peripherals used as a basis for the final firmware.

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Nugmanova, S. A., and М. Erbolat. "TEACHING STUDENTS TO WTHE USE OF MICROCOMPUTER IN TEACHING STUDENTS." BULLETIN Series of Physics & Mathematical Sciences 69, no. 1 (March 10, 2020): 387–97. http://dx.doi.org/10.51889/2020-1.1728-7901.70.

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This article discusses the prerequisites for using the Arduino Uno brand of hardware and software, which are necessary when creating simple automation and robotics systems for non-professional users in teaching the basics of microcontroller robotics. The article discusses the capabilities of the Arduino hardware computing platform as applied to mechatronic complexes. A functional description and technical specifications are given using the Arduino UNO board as an example. A comparative analysis of the hardware of the most relevant boards has been compiled. The prospects for the use of the Arduino microprocessor platform for training and design in the field of physical process control are determined. The article compares various microcontrollers Arduino, Raspberry Pi, Lego Mindstroms. based on the analysis, it is concluded that Lego Mindstroms microcontrollers are the most convenient for teaching younger students, and for teaching middle and high school students - Arduino microcontrollers. Mindstorms microcontrollers are sold complete with instructions, peripherals, parts, and sensors. Their body protects against damage, and familiar to many children LEGO allows you to create various mechanisms and robots using a visual programming language. This set is easily mastered by primary and secondary school students. High school students can develop programming skills in the integrated Arduino environment.

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Apostolakis, Andreas, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, and Matteo Sonza Reorda. "Test Program Generation for Communication Peripherals in Processor-Based SoC Devices." IEEE Design & Test of Computers 26, no. 2 (March 2009): 52–63. http://dx.doi.org/10.1109/mdt.2009.43.

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Zhang, Yuedong. "gDevice: A Protocol for the Grid-Enabling of the Computer Peripherals." Journal of Computer Research and Development 42, no. 6 (2005): 918. http://dx.doi.org/10.1360/crad20050603.

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Apostolakis, A., M. Psarakis, D. Gizopoulos, and A. Paschalis. "Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 8 (August 2007): 971–75. http://dx.doi.org/10.1109/tvlsi.2007.900750.

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Álvarez Ariza, Jonathan. "DSCBlocks: An Open-Source Platform for Learning Embedded Systems Based on Algorithm Visualizations and Digital Signal Controllers." Electronics 8, no. 2 (February 18, 2019): 228. http://dx.doi.org/10.3390/electronics8020228.

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DSCBlocks is an open-source platform in hardware and software developed in JavaFX, which is focused on learning embedded systems through Digital Signal Controllers (DSCs). These devices are employed in industrial and educational sectors due to their robustness, number of peripherals, processing speed, scalability and versatility. The platform uses graphical blocks designed in Google’s tool Blockly that can be used to build different Algorithm Visualizations (AVs). Afterwards, the algorithms are converted in real-time to C language, according to the specifications of the compiler for the DSCs (XC16) and they can be downloaded in one of the two models of development board for the dsPIC 33FJ128GP804 and dsPIC 33FJ128MC802. The main aim of the platform is to provide a flexible environment, drawing on the educational advantages of the AVs with different aspects concerning the embedded systems, such as declaration of variables and functions, configuration of ports and peripherals, handling of Real-Time Operating System (RTOS), interrupts, among others, that are employed in several fields such as robotics, control, instrumentation, etc. In addition, some experiments that were designed in the platform are presented in the manuscript. The educational methodology and the assessment provided by the students (n = 30) suggest that the platform is suitable and reliable to learn concepts relating to embedded systems.

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Chen, Li Gang. "The Development of UC/OS Application System Based on Embedded System." Applied Mechanics and Materials 543-547 (March 2014): 689–92. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.689.

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To solve the effect that the multi threading task can be achieved by the TFT of color screen, we adopt MSP430F5438 as the main controller, the main equipment of its hardware system was built by the TFT of touch screen, and the task driving function was completed by using buttons and wireless communication module and other peripherals. And we have developed the application program based on UC/OS operating system utility with the kernel structure and characteristics of UC/OS. It can be realized these function, such as digital tube display, TFT display task, multi-tasking, wireless communication, the task driving system, touch screen and low power verification task. The experimental results show that it completely meets the desired design goals, it works reliable and stable.

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Gan, Ke, Xi Wei Peng, and Zhan Dong Zhao. "Design of Intelligent Display Meter Based on ARM." Applied Mechanics and Materials 241-244 (December 2012): 525–28. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.525.

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Display meter is the basic unit of automation system. In order to improve the performance and the compatibility of display meter, a design of intelligent display meter based on ARM is put forward. The Micro Control Unit (MCU) STM32F103VE based on the 32 bit ARM Cortex–M3 core is used as the host controller of the meter system. On the basis of this controller, hardware and software design were carried out. The intelligent display meter can receive voltage and current signals from most sensors. Because of the excellent processing capability and rich peripherals of the MCU, the meter can handle large amounts of data rapidly so as to monitor the status of industrial field in real time and communicate with different upper computers.

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Parrilla, Luis, Antonio García, Encarnación Castillo, José Antonio Álvarez-Bermejo, Juan Antonio López-Villanueva, and Uwe Meyer-Baese. "Dracon: An Open-Hardware Based Platform for Single-Chip Low-Cost Reconfigurable IoT Devices." Electronics 11, no. 13 (July 2, 2022): 2080. http://dx.doi.org/10.3390/electronics11132080.

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The development of devices for the Internet of Things (IoT) requires the rapid prototyping of different hardware configurations. In this paper, a modular hardware platform allowing to prototype, test and even implement IoT appliances on low-cost reconfigurable devices is presented. The proposed platform, named Dracon, includes a Z80-clone microprocessor, up to 64 KB of RAM, and 256 inputs/outputs (I/Os). These I/Os can be used to connect additional co-processors within the same FPGA, external co-processors, communications modules, sensors and actuators. Dracon also includes as default peripherals a UART for programming and accessing the microprocessor, a Real Time Clock, and an Interrupt Timer. The use of an 8-bit microprocessor allows the use of the internal memory of the reconfigurable device as program memory, thereby, enabling the implementation of a complete IoT device within a single low-cost chip. Indeed, results using a Spartan 7 FPGA show that it is possible to implement Dracon with only 1515 6-input LUTs while operating at a maximum frequency of 80 MHz, which results in a better trade-off in terms of area and performance than other less powerful and less versatile alternatives in the literature. Moreover, the presented platform allows the development of embedded software applications independently of the selected FPGA device, enabling rapid prototyping and implementations on devices from different manufacturers.

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Rajagopalan, Sundararaman, Sivaraman R, Har Narayan Upadhyay, John Bosco Balaguru Rayappan, and Rengarajan Amirtharajan. "ON Chip peripherals are ON for chaos – an image fused encryption." Microprocessors and Microsystems 61 (September 2018): 257–78. http://dx.doi.org/10.1016/j.micpro.2018.06.011.

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Zhang, Xu Hui, Jia Liu, and Zeng Ji Cheng. "Design of Three-Phase Multi-Function Energy Meter Based on Measurement Chip RN8302." Applied Mechanics and Materials 226-228 (November 2012): 1888–91. http://dx.doi.org/10.4028/www.scientific.net/amm.226-228.1888.

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According to the development status of the energy meter, we put forward a design of a Three-phase multi-function energy meter based on professional measurement chip RN8302 and High-performance single chip microcomputer MSP430 in this article. It has the characteristics which are low-power consumption, high-precision and electricity anti-theft. It could also real-time measured current, voltage, active power, reactive power, power factor, over-voltage and over-current signal. The design also has the functions of surge prevention, lightning prevention and voltage protection, improving the overall safety and reliability of the system.Use the Low-voltage power line carrier communication, there is no need to build another peripherals,saving the cost of grid investment. The article also gave the overall design scheme and the main hardware principle Schematic.

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Lee, Edward, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, and Saibal Mukhopadhyay. "A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process." ACM Journal on Emerging Technologies in Computing Systems 18, no. 1 (January 31, 2022): 1–20. http://dx.doi.org/10.1145/3466681.

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We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers of transistors for access and peripheral circuits. The compiler includes an automated flow for generation of subarrays of different dimensions and larger arrays of a target capacity by integrating multiple subarrays. The compiler is demonstrated using an M3D process design kit (PDK) based on a Carbon Nanotube Transistor technology. The PDK includes multiple layers of transistors and back-end-of-the-line integrated ReRAM. Simulations show the compiled ReRAM macros with multiple tiers of transistors reduces footprint and improves performance over the macros with single-tier transistors. The compiler creates layout views that are exported into library exchange format or graphic data system for full-array assembly and schematic/symbol views to extract per-bit read/write energy and read latency. Comparison of the proposed M3D subarray architectures with baseline 2D subarrays, generated with a custom-designed set of bit cells and peripherals, demonstrate up to 48% area reduction and 13% latency improvement.

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Huang, Wei Fu, and Chi Liu Shen. "Control Language for Public - An Example Based on 328eforth." Applied Mechanics and Materials 418 (September 2013): 116–19. http://dx.doi.org/10.4028/www.scientific.net/amm.418.116.

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Although robot has been around for many years, the programming language for robot control is still hard for ordinary persons. To promote robot into live of ordinary persons, an easier control language is one of necessity. We need a control language that can be programmed in any words and not limited to English. Forth is one of computer language that can define new commands in any printable characters on keyboard. This study explored eforth, one of kind of Forth, build on ATMEGA328P chip which is used on the world wide popular Ardunino UNO board is called 328eForth system. A 328eForth system has been developed that can be used to control hardware peripherals using Traditional Chinese command. It has simple programming rules, compact system size, and is an open source control language which used in robotic and mechatronic control and education for public.

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van Deursen, Alexander JAM, and Jan AGM van Dijk. "The first-level digital divide shifts from inequalities in physical access to inequalities in material access." New Media & Society 21, no. 2 (September 7, 2018): 354–75. http://dx.doi.org/10.1177/1461444818797082.

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For a long time, a common opinion among policy-makers was that the digital divide problem would be solved when a country’s Internet connection rate reaches saturation. However, scholars of the second-level digital divide have concluded that the divides in Internet skills and type of use continue to expand even after physical access is universal. This study—based on an online survey among a representative sample of the Dutch population—indicates that the first-level digital divide remains a problem in one of the richest and most technologically advanced countries in the world. By extending basic physical access combined with material access, the study finds that a diversity in access to devices and peripherals, device-related opportunities, and the ongoing expenses required to maintain the hardware, software, and subscriptions affect existing inequalities related to Internet skills, uses, and outcomes.

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Haldar, M. K., and H. S. Yeoh. "A circuit for sharing peripherals and instruments with the IEEE-488 interface between two or more microcomputers." Computer Standards & Interfaces 5, no. 1 (January 1986): 47–53. http://dx.doi.org/10.1016/0920-5489(86)90068-1.

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Si, Qilin, Santosh Shetty, and Benjamin Carrion Schaefer. "Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs." Electronics 10, no. 14 (July 20, 2021): 1746. http://dx.doi.org/10.3390/electronics10141746.

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High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.

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Lv, Qian, and Jin Lan Zhang. "The Design of Controller in AVS Video Decoder Chip Based on Openrisc." Applied Mechanics and Materials 263-266 (December 2012): 53–59. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.53.

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Separate software is hard to achieve real-time HD decoding for its sequential execution, while pure hardware is unable to complete the complex AVS video decoding. Aiming at this, this paper adopts the SoC scheme to develop the controller in AVS decoder. The author selected the OpenRISC1200 processor for its no licensing fees and completely open source. For AVS decoder’s high-complexity, we reconfigured the core to optimize it and designed some peripherals - SDRAM controller, VGA controller, and Wishbone bus module. By elaborating the module’s design, simulation, synthesis, static timing analysis and formal verification, this paper proposes a solution of high-speed & high integration controller in AVS-SoC decoder chip. This controller can quickly complete the AVS stream parsing and system controlling, and also it can improve the AVS chip’s integration and the versatility. Overall, it has great application value and broad market prospects.

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Fakki, Altamash, Salahaldein Ahmed, Jongwon Park, and Chang-Soo Kim. "Versatile Optochemical Quantification with Optical Mouse." Journal of Sensors 2017 (2017): 1–7. http://dx.doi.org/10.1155/2017/1243754.

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There is an ever increasing need for simple, low-cost instruments for ubiquitous medical and environmental measurements in conjunction with networks and Internet-of-things. This work demonstrates that the optical mouse, one of the most common optoelectronic computer peripherals, can be used for chemical quantification. Particularly, we explore the feasibility of using the preassembled optical platform of mouse for oxygen and pH quantification. The image sensor and the light-emitting diode (LED) serve as photodetector and excitation/illumination light source, respectively, while the preinstalled microoptics (e.g., lens and waveguide) provide a fixed optical arrangement convenient for sample analysis. This novel, cost-effective approach demonstrates the potential application of optical mouse for bioanalytical devices in conjunction with commercial sensor strips or simple microfluidic elements. This is one viable option for seamless integration of bioanalytical capability into existing personal computers and associate networks without significant additional hardware.

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Tatlas, Nikolas Alexander, Dimitris Ballios, Stelios M. Potirakis, Christina Charitou, Stelios Koutroubinas, and Maria Rangoussi. "A Smart Sensor Platform for Greenhouse Applications." Key Engineering Materials 644 (May 2015): 92–95. http://dx.doi.org/10.4028/www.scientific.net/kem.644.92.

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A platform for a flexible, smart sensing system using available hardware components for monitoring the operation of a greenhouse is presented. The smart sensor is based on a ZigBee MCU embedded system with multiple connectivity options to facilitate digital or analogue sensors as well as the necessary peripherals for energy management and programming/debugging. A number of physical parameters may be simultaneously monitored by each node, such as temperature, relative humidity, CO2, light intensity, soil pH / moisture through appropriate sensors. Basic functions, such as sensor differential detection and measurement consistency may be performed at the smart sensor. A central node, also acting as the Zigbee network coordinator will concentrate the various measurements through the wireless network, act as a local display and also forward the information to a back-end. The back-end will provide proper measurement visualization (including history) through any web-enabled device, as well as services such as alert notification in hazardous situations (e.g. flood / heating failure).

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Charij, Stephanie, and Andreas Oikonomou. "Using Biometric Measurement in Real-Time as a Sympathetic System in Computer Games." International Journal of Game-Based Learning 3, no. 3 (July 2013): 21–42. http://dx.doi.org/10.4018/ijgbl.2013070103.

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With the increasing potential for gaming hardware and peripherals to support biometrics, their application within the games industry for software and design should be considered. This paper assesses the ability to use a form of biometric measurement, heart rate, in real-time to improve the challenge and enjoyment of a game by catering it to individuals of varying ability. While the findings of this study are valuable to game developers interested in providing additional dimensions to gameplay and testing, they may also be useful for those researching medical or therapeutic applications for games. The results suggest that although the tested game was inherently challenging and enjoyable, the adaptive affective gameplay was not altering the game enough to induce strong physiological or emotional responses from participants. Biofeedback games lend themselves to medical applications, but adaptive affective games can be used to respond sympathetically to the player without requiring direct control of physiological responses as a form of input.

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Gerschütz, Benjamin, Marius Fechter, Benjamin Schleich, and Sandro Wartzack. "A Review of Requirements and Approaches for Realistic Visual Perception in Virtual Reality." Proceedings of the Design Society: International Conference on Engineering Design 1, no. 1 (July 2019): 1893–902. http://dx.doi.org/10.1017/dsi.2019.195.

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AbstractThe amount of new virtual reality input and output devices being developed is enormous. Those peripherals offer novel opportunities and possibilities in the industrial context, especially in the product development process. Nevertheless, virtual reality has to face several problems, counteracting reliable use of the technology, especially in ergonomic and aesthetic assessments. In particular, the discrepancies in perception between the real world and virtual reality are of great importance.Therefore, we discuss these most important issues of current virtual reality technology and highlight approaches to solve them. First, we illustrate the use cases of VR in the product development process. In addition, we show which hardware is currently available for professional use and which issues exist with regard to visual perception and interaction. Derived from the depiction of a perfect virtual reality, we define the requirements to address visual perception and interaction. Subsequently we discuss approaches to solve the issues regarding visual perception and evaluate their suitability to enhance the use of virtual reality technology in engineering design.

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Rossi, Stefano, and Enrico Boni. "Embedded GPU Implementation for High-Performance Ultrasound Imaging." Electronics 10, no. 8 (April 8, 2021): 884. http://dx.doi.org/10.3390/electronics10080884.

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Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

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Devine, James, Michal Moskal, Peli de Halleux, Thomas Ball, Steve Hodges, Gabriele D'Amone, David Gakure, et al. "Plug-and-play Physical Computing with Jacdac." Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies 6, no. 3 (September 6, 2022): 1–30. http://dx.doi.org/10.1145/3550317.

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Physical computing is becoming mainstream. More people than ever---from artists, makers and entrepreneurs to educators and students---are connecting microcontrollers with sensors and actuators to create new interactive devices. However, physical computing still presents many challenges and demands many skills, spanning electronics, low-level protocols, and software---road blocks that reduce participation. While USB has made connecting peripherals to a personal computing device (PC) trivial, USB components are expensive and require a PC to operate. This makes USB impractical for many physical computing scenarios where cost, size and low power operation are often important.

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Güvengir, Umut, Işık Çadırcı, and Muammer Ermiş. "On-Line Application of SHEM by Particle Swarm Optimization to Grid-Connected, Three-Phase, Two-Level VSCs with Variable DC Link Voltage." Electronics 7, no. 8 (August 20, 2018): 151. http://dx.doi.org/10.3390/electronics7080151.

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This paper is devoted to an otablen-line application of the selective harmonic elimination method (SHEM) to three-phase, two-level, grid-connected voltage source converters (VSCs) by particle swarm optimization (PSO). In such systems, active power can be controlled by the phase shift angle, and reactive power by the modulation index, against variations in the direct current (DC) link voltage. Some selected, low-odd-order harmonic components in the line-to-neutral output voltage waveforms are eliminated by calculating the SHEM angle set continuously through the developed PSO algorithm on field-programmable gate array (FPGA)-based computing hardware as the modulation index is varied. The use of powerful computing hardware permits the elimination of all harmonics up to 50th. The cost function of the developed PSO algorithm is formulated by using an optimum number of particles to obtain a global optimum solution with a small fitness value in each half-cycle of the grid voltage and then updating the SHEM angle set at the beginning of the next full-cycle. Since the convergence of the solution to a global minimum point depends upon the use of correct initial values especially for a large number of SHEM angles, a generalized initialization procedure is also described in the paper. Theoretical results are verified initially using hardware co-simulation. They are also tested using a small scale photovoltaic (PV) supply prototype developed specifically for this purpose. It is demonstrated that the 5th, 7th, 11th, 13th, 17th, and 19th sidekick harmonics are eliminated by on-line calculation of seven SHEM angles through the developed PSO algorithm on a moderately powerful XEM6010-LX150, USB-2.0-integrated FPGA module. All control and protection actions and the calculation of SHEM angles are achieved by a single FPGA chip and its peripherals within the FPGA board.

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Journal articles on the topic 'Hardware - Peripherals'

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