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Journal articles on the topic 'Hardware-Software Codesign Accelerators'

Author: Grafiati

Published: 6 September 2023

Last updated: 31 July 2025

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1

Xiao, Chunhua, Lei Zhang, Yuhua Xie, Weichen Liu, and Duo Liu. "Hardware/Software Adaptive Cryptographic Acceleration for Big Data Processing." Security and Communication Networks 2018 (August 27, 2018): 1–24. http://dx.doi.org/10.1155/2018/7631342.

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Along with the explosive growth of network data, security is becoming increasingly important for web transactions. The SSL/TLS protocol has been widely adopted as one of the effective solutions for sensitive access. Although OpenSSL could provide a freely available implementation of the SSL/TLS protocol, the crypto functions, such as symmetric key ciphers, are extremely compute-intensive operations. These expensive computations through software implementations may not be able to compete with the increasing need for speed and secure connection. Although there are lots of excellent works with th

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2

Kritikakou, Angeliki, Francky Catthoor, George S. Athanasiou, Vasilios Kelefouras, and Costas Goutis. "Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints." ACM Transactions on Architecture and Code Optimization 10, no. 2 (2013): 1–25. http://dx.doi.org/10.1145/2459316.2459317.

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3

Sorrentino, Giuseppe, Marco Venere, Davide Conficconi, Eleonora D’Arnese, and Marco Domenico Santambrogio. "Hephaestus : Codesigning and Automating 3D Image Registration on Reconfigurable Architectures." ACM Transactions on Embedded Computing Systems 22, no. 5s (2023): 1–24. http://dx.doi.org/10.1145/3607928.

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Healthcare is a pivotal research field, and medical imaging is crucial in many applications. Therefore finding new architectural and algorithmic solutions would benefit highly repetitive image processing procedures. One of the most complex tasks in this sense is image registration, which finds the optimal geometric alignment among 3D image stacks and is widely employed in healthcare and robotics. Given the high computational demand of such a procedure, hardware accelerators are promising real-time and energy-efficient solutions, but they are complex to design and integrate within software pipe

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4

Hernández, Mario, Juan M. Cebrián, José M. Cecilia, and José M. García. "Offloading strategies for Stencil kernels on the KNC Xeon Phi architecture: Accuracy versus performance." International Journal of High Performance Computing Applications 34, no. 2 (2017): 199–207. http://dx.doi.org/10.1177/1094342017738352.

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The ever-increasing computational requirements of HPC and service provider applications are becoming a great challenge for hardware and software designers. These requirements are reaching levels where the isolated development on either computational field is not enough to deal with such challenge. A holistic view of the computational thinking is therefore the only way to success in real scenarios. However, this is not a trivial task as it requires, among others, of hardware–software codesign. In the hardware side, most high-throughput computers are designed aiming for heterogeneity, where acce

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5

Morales-Sandoval, Miguel, Luis Armando Rodriguez Flores, Rene Cumplido, Jose Juan Garcia-Hernandez, Claudia Feregrino, and Ignacio Algredo. "A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks." Journal of Sensors 2021 (January 6, 2021): 1–13. http://dx.doi.org/10.1155/2021/8860413.

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The main topic of this paper is low-cost public key cryptography in wireless sensor nodes. Security in embedded systems, for example, in sensor nodes based on field programmable gate array (FPGA), demands low cost but still efficient solutions. Sensor nodes are key elements in the Internet of Things paradigm, and their security is a crucial requirement for critical applications in sectors such as military, health, and industry. To address these security requirements under the restrictions imposed by the available computing resources of sensor nodes, this paper presents a low-area FPGA-prototyp

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6

Ahmed, O., S. Areibi, K. Chattha, and B. Kelly. "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability." International Journal of Reconfigurable Computing 2011 (2011): 1–21. http://dx.doi.org/10.1155/2011/648483.

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Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluat

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7

Ashna, Farheen, Fatima Zoha, and Tahura Muskan. "Applications of Embedded System Using AI: A Review." Journal of Optoelectronics and Communication 7, no. 2 (2025): 1–7. https://doi.org/10.5281/zenodo.15349209.

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<em>Conventional methods for implementing logic programming applications on embedded systems are software- based, requiring a compiler to convert the initial declarative logic program to its equivalent procedural one. This increases the complexity of the final implementation and reduces system performance. However, hardware implementations that only support logic programs prevent their use in applications where logic programs need to be intertwined with traditional procedural ones. This paper exploits HW/SW codesign methods to present a microprocessor capable of supporting hybrid ap- plication

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8

Pedram, Ardavan, Andreas Gerstlauer, and Robert A. van de Geijn. "Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator." IEEE Transactions on Computers 63, no. 8 (2014): 1854–67. http://dx.doi.org/10.1109/tc.2014.2315627.

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9

Acer, Seher, Ariful Azad, Erik G. Boman, et al. "EXAGRAPH: Graph and combinatorial methods for enabling exascale applications." International Journal of High Performance Computing Applications 35, no. 6 (2021): 553–71. http://dx.doi.org/10.1177/10943420211029299.

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Combinatorial algorithms in general and graph algorithms in particular play a critical enabling role in numerous scientific applications. However, the irregular memory access nature of these algorithms makes them one of the hardest algorithmic kernels to implement on parallel systems. With tens of billions of hardware threads and deep memory hierarchies, the exascale computing systems in particular pose extreme challenges in scaling graph algorithms. The codesign center on combinatorial algorithms, ExaGraph, was established to design and develop methods and techniques for efficient implementat

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10

Kumar, Rakesh, Alejandro Martínez, and Antonio González. "Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment." ACM Transactions on Architecture and Code Optimization 11, no. 3 (2014): 1–23. http://dx.doi.org/10.1145/2629681.

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11

Karl, Patrick, Jonas Schupp, Tim Fritzmann, and Georg Sigl. "Post-Quantum Signatures on RISC-V with Hardware Acceleration." ACM Transactions on Embedded Computing Systems, January 6, 2023. http://dx.doi.org/10.1145/3579092.

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CRYSTALS-Dilithium and Falcon are digital signature algorithms based on cryptographic lattices, that are considered secure even if large-scale quantum computers will be able to break conventional public-key cryptography. Both schemes have been selected for standardization in the NIST post-quantum competition. In this work, we present a RISC-V HW/SW codesign that aims to combine the advantages of software- and hardware implementations, i.e. flexibility and performance. It shows the use of flexible hardware accelerators, which have been previously used for Public-Key Encryption (PKE) and Key-Enc

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12

Zhang, Woyu, Zhi Li, Xinyuan Zhang, et al. "Fully Binarized Graph Convolutional Network Accelerator Based on In‐Memory Computing with Resistive Random‐Access Memory." Advanced Intelligent Systems, March 25, 2024. http://dx.doi.org/10.1002/aisy.202300784.

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Artificial intelligence for graph‐structured data has achieved remarkable success in applications such as recommendation systems, social networks, drug discovery, and circuit annotation. Graph convolutional networks (GCNs) are an effective way to learn representations of various graphs. The increasing size and complexity of graphs call for in‐memory computing (IMC) accelerators for GCN to alleviate massive data transmission between off‐chip memory and processing units. However, GCN implementation with IMC is challenging because of the large memory consumption, irregular memory access, and devi

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13

Bahadori, Milad, Kimmo Järvinen, Tilen Marc, and Miha Stopar. "Speed Reading in the Dark: Accelerating Functional Encryption for Quadratic Functions with Reprogrammable Hardware." IACR Transactions on Cryptographic Hardware and Embedded Systems, July 9, 2021, 1–27. http://dx.doi.org/10.46586/tches.v2021.i3.1-27.

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Functional encryption is a new paradigm for encryption where decryption does not give the entire plaintext but only some function of it. Functional encryption has great potential in privacy-enhancing technologies but suffers from excessive computational overheads. We introduce the first hardware accelerator that supports functional encryption for quadratic functions. Our accelerator is implemented on a reprogrammable system-on-chip following the hardware/software codesign methogology. We benchmark our implementation for two privacy-preserving machine learning applications: (1) classification o

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14

Vetter, Jeffrey S., Prasanna Date, Farah Fahim, et al. "Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials." International Journal of High Performance Computing Applications, June 22, 2023. http://dx.doi.org/10.1177/10943420231178537.

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The Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic devices that are based on resistive-switching materials, such as memristors and electrochemical RAM. Equally important, Abisko uses a deep codesign approach to pursue this goal by engaging experts from across the entire range of disciplines: materials, devices and circuits, architectures and integration, software, and algorithms. The key objectives of our Abisko project are t

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15

Oberhansl, Felix, Tim Fritzmann, Thomas Pöppelmann, Debapriya Basu Roy, and Georg Sigl. "Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography." Journal of Cryptographic Engineering, August 24, 2023. http://dx.doi.org/10.1007/s13389-023-00332-2.

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AbstractHybrid key encapsulation is in the process of becoming the de-facto standard for integration of post-quantum cryptography (PQC). Supporting two cryptographic primitives is a challenging task for constrained embedded systems. Both contemporary cryptography based on elliptic curves or RSA and PQC based on lattices require costly multiplications. Recent works have shown how to implement lattice-based cryptography on big-integer coprocessors. We propose a novel hardware design that natively supports the multiplication of polynomials and big integers, integrate it into a RISC-V core, and ex

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