Relevant bibliographies by topics / Hardware-software design / Journal articles
To see the other types of publications on this topic, follow the link: Hardware-software design.

Journal articles on the topic 'Hardware-software design'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Hardware-software design.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

De Michell, G., and R. K. Gupta. "Hardware/software co-design." Proceedings of the IEEE 85, no. 3 (March 1997): 349–65. http://dx.doi.org/10.1109/5.558708.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Mills, Mike, and Greg Peterson. "Hardware/software co-design." ACM SIGAda Ada Letters XVIII, no. 6 (November 1998): 18–27. http://dx.doi.org/10.1145/301687.289528.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Kuchcinski, Krzysztof. "Design of hardware and software systems." Journal of Systems Architecture 42, no. 9-10 (February 1997): 663–64. http://dx.doi.org/10.1016/s1383-7621(96)00068-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Aronsson, Markus, and Mary Sheeran. "Hardware software co-design in Haskell." ACM SIGPLAN Notices 52, no. 10 (October 31, 2017): 162–73. http://dx.doi.org/10.1145/3156695.3122970.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Naidu, DS. "Microprocessors: hardware, software and design applications." Microprocessors and Microsystems 9, no. 2 (March 1985): 86–87. http://dx.doi.org/10.1016/0141-9331(85)90431-4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (October 18, 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.

Full text
Abstract:
Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.
APA, Harvard, Vancouver, ISO, and other styles
7

Kent, K. B., M. Serra, and N. Horspool. "Hardware/software co-design for virtual machines." IEE Proceedings - Computers and Digital Techniques 152, no. 5 (2005): 537. http://dx.doi.org/10.1049/ip-cdt:20041264.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Wirth, Niklaus. "Hardware/software co-design then and now." Information Processing Letters 88, no. 1-2 (October 2003): 83–87. http://dx.doi.org/10.1016/s0020-0190(03)00385-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Gómez-Pulido, Juan A. "Recent advances in Hardware/Software co-design." Journal of Systems Architecture 56, no. 8 (August 2010): 303–4. http://dx.doi.org/10.1016/j.sysarc.2010.06.008.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wolf, W. H. "Hardware-software co-design of embedded systems." Proceedings of the IEEE 82, no. 7 (July 1994): 967–89. http://dx.doi.org/10.1109/5.293155.

Full text
APA, Harvard, Vancouver, ISO, and other styles
11

Vranken, H. P. E., M. F. Witteman, and R. C. Van Wuijtswinkel. "Design for testability in hardware software systems." IEEE Design & Test of Computers 13, no. 3 (1996): 79–86. http://dx.doi.org/10.1109/54.536098.

Full text
APA, Harvard, Vancouver, ISO, and other styles
12

Mian, Riaz-ul-haque, Michihiro Shintani, and Michiko Inoue. "Hardware–Software Co-Design for Decimal Multiplication." Computers 10, no. 2 (January 27, 2021): 17. http://dx.doi.org/10.3390/computers10020017.

Full text
Abstract:
Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.
APA, Harvard, Vancouver, ISO, and other styles
13

Edwards, M. D., J. Forrest, and A. E. Whelan. "Acceleration of software algorithms using hardware/software co-design techniques." Journal of Systems Architecture 42, no. 9-10 (February 1997): 697–707. http://dx.doi.org/10.1016/s1383-7621(96)00071-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
14

Lee, Edward A., Stephen Neuendorffer, and Michael J. Wirthlin. "Actor-Oriented Design of Embedded Hardware and Software Systems." Journal of Circuits, Systems and Computers 12, no. 03 (June 2003): 231–60. http://dx.doi.org/10.1142/s0218126603000751.

Full text
Abstract:
In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is an abstraction layer in the design flow. For example, a core-based architecture and an instruction set architecture are platforms. We focus on the set of designs induced by this abstraction layer. For example, the set of all ASICs based on a particular core-based architecture and the set of all x86 programs are induced sets. Hence, a platform is equivalently a set of designs. Model-based design is about using platforms with useful modeling properties to specify designs, and then synthesizing implementations from these specifications. Hence model-based design is the view from above (more abstract, closer to the problem domain) and platform-based design is the view from below (less abstract, closer to the implementation technology). One way to define a platform is to provide a design language. Any valid expression in the language is an element of the set. A platform provides a set of constraints together with known tradeoffs that flow from those constraints. Actor-oriented platforms, such as Simulink, abstract aspects of program-level platforms, such as Java, C++, and VHDL. Actor-oriented platforms orthogonalize the actor definition language and the actor composition language, enabling highly polymorphic actor definitions and design using multiple models of computation. In particular, we concentrate on the use of constrained models of computation in design. The modeling properties implied by well chosen constraints allow more easily understood designs and are preserved during synthesis into program-level descriptions. We illustrate these concepts by describing a design framework built on Ptolemy II.
APA, Harvard, Vancouver, ISO, and other styles
15

Wang, Xiaolin, Jiarui Zang, Zhenlin Wang, Yingwei Luo, and Xiaoming Li. "Selective hardware/software memory virtualization." ACM SIGPLAN Notices 46, no. 7 (July 15, 2011): 217–26. http://dx.doi.org/10.1145/2007477.1952710.

Full text
APA, Harvard, Vancouver, ISO, and other styles
16

Xiang, Lingxiang, and Michael L. Scott. "Software partitioning of hardware transactions." ACM SIGPLAN Notices 50, no. 8 (December 18, 2015): 76–86. http://dx.doi.org/10.1145/2858788.2688506.

Full text
APA, Harvard, Vancouver, ISO, and other styles
17

Xiaoying Liang. "Information System Security Design Using Hardware/Software Co-design Technology." International Journal of Digital Content Technology and its Applications 6, no. 8 (May 31, 2012): 351–60. http://dx.doi.org/10.4156/jdcta.vol6.issue8.41.

Full text
APA, Harvard, Vancouver, ISO, and other styles
18

Alecsa, Bogdan, and Alexandru Onea. "Hardware-Software Co-Design for BLDC Motor Speed Controller Design." Advanced Materials Research 463-464 (February 2012): 1256–59. http://dx.doi.org/10.4028/www.scientific.net/amr.463-464.1256.

Full text
Abstract:
This paper proposes a combined hardware-software approach for a controller design. The case of a brushless DC (BLDC) motor speed controller is studied. A hardware controller is implemented inside a field programmable gate array (FPGA) device, together with soft core processors that implement by software non-critical tasks, like liquid crystal display (LCD) interface and serial data communication to a host computer. This way, the control algorithm is executed in hardware, as fast as possible, while the monitoring tasks are performed by the software. Experimental results are provided, showing the working design.
APA, Harvard, Vancouver, ISO, and other styles
19

Abid, M., T. Ben Ismail, A. Changuel, C. A. Valderrama, M. Romdhani, G. F. Marchioro, J. M. Daveau, and A. A. Jerraya. "Hardware/Software Co-Design Methodology for Design of Embedded Systems." Integrated Computer-Aided Engineering 5, no. 1 (January 1, 1998): 69–84. http://dx.doi.org/10.3233/ica-1998-5106.

Full text
APA, Harvard, Vancouver, ISO, and other styles
20

Phanomchoeng, Gridsada, Muhammad Saadi, Pruk Sasithong, Jedsada Tangmongkhonsuk, Sanika K. Wijayasekara, and Lunchakorn Wuttisittikulkij. "Hardware Software Co-Design of a Farming Robot." Engineering Journal 24, no. 1 (February 8, 2020): 199–208. http://dx.doi.org/10.4186/ej.2020.24.1.199.

Full text
APA, Harvard, Vancouver, ISO, and other styles
21

Dolinsky, M. "High-level design of embedded hardware–software systems." Advances in Engineering Software 31, no. 3 (March 2000): 197–201. http://dx.doi.org/10.1016/s0965-9978(99)00044-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
22

Schmidt, Ryan, and Matt Ratto. "Design-to-Fabricate: Maker Hardware Requires Maker Software." IEEE Computer Graphics and Applications 33, no. 6 (November 2013): 26–34. http://dx.doi.org/10.1109/mcg.2013.90.

Full text
APA, Harvard, Vancouver, ISO, and other styles
23

Bolsens, I., H. J. De Man, B. Lin, K. Van Rompaey, S. Vercauteren, and D. Verkest. "Hardware/software co-design of digital telecommunication systems." Proceedings of the IEEE 85, no. 3 (March 1997): 391–418. http://dx.doi.org/10.1109/5.558713.

Full text
APA, Harvard, Vancouver, ISO, and other styles
24

Glass, Robert L. "The “software-first” revolution in computer hardware design." Journal of Systems and Software 51, no. 1 (April 2000): 1–5. http://dx.doi.org/10.1016/s0164-1212(99)00101-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
25

Philipson, L. "Multilevel design and verification of hardware/software systems." IEEE Journal of Solid-State Circuits 25, no. 3 (June 1990): 714–19. http://dx.doi.org/10.1109/4.102665.

Full text
APA, Harvard, Vancouver, ISO, and other styles
26

Salewski, Falk, and Stefan Kowalewski. "Hardware/Software Design Considerations for Automotive Embedded Systems." IEEE Transactions on Industrial Informatics 4, no. 3 (August 2008): 156–63. http://dx.doi.org/10.1109/tii.2008.2002919.

Full text
APA, Harvard, Vancouver, ISO, and other styles
27

Krawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (March 1, 2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.

Full text
Abstract:
Whirlpool SoPC Implementation - Hardware/Software Co-Design Example The aim of this work was to design a System on Programmable Chip (SoPC), that implements the Whirlpool Hash Function (WHF) algorithm. An assumption of the project was to use an embedded soft-processor NIOS II controlling the whole system, which functionality was extended by a custom logic in order to improve the used algorithm efficiency. This paper presents the Whirlpool Hash Function realized in several SoPC configurations, which differ in implementation complexity and performance.
APA, Harvard, Vancouver, ISO, and other styles
28

Nahvi, M. "Design-oriented DSP courseware-hardware, software, and simulation." IEEE Signal Processing Magazine 9, no. 4 (October 1992): 30–35. http://dx.doi.org/10.1109/79.157328.

Full text
APA, Harvard, Vancouver, ISO, and other styles
29

Wong, Sy, and Gertrude Levine. "Kernel Ada to unify hardware and software design." ACM SIGAda Ada Letters XVIII, no. 6 (November 1998): 28–38. http://dx.doi.org/10.1145/301687.289529.

Full text
APA, Harvard, Vancouver, ISO, and other styles
30

Kramer, William, and David Skinner. "An Exascale Approach to Software and Hardware Design." International Journal of High Performance Computing Applications 23, no. 4 (September 30, 2009): 389–91. http://dx.doi.org/10.1177/1094342009347768.

Full text
APA, Harvard, Vancouver, ISO, and other styles
31

Hartley, M. G. "Book Review: Microprocessors: Hardware, Software and Design Applications." International Journal of Electrical Engineering Education 22, no. 3 (September 1985): 285–86. http://dx.doi.org/10.1177/002072098502200331.

Full text
APA, Harvard, Vancouver, ISO, and other styles
32

Gajski, D. D., and F. Vahid. "Specification and design of embedded hardware-software systems." IEEE Design & Test of Computers 12, no. 1 (1995): 53–67. http://dx.doi.org/10.1109/54.350695.

Full text
APA, Harvard, Vancouver, ISO, and other styles
33

Whitworth, Ian. "Microprocessor systems design: 68000 hardware, software, and interfacing." Microprocessors and Microsystems 12, no. 1 (January 1988): 61–62. http://dx.doi.org/10.1016/0141-9331(88)90040-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
34

Gandhi, Sharad. "Graphics software and hardware design with the 82786." Microprocessors and Microsystems 12, no. 5 (June 1988): 271–76. http://dx.doi.org/10.1016/0141-9331(88)90128-7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
35

Wullert, John R., and Peter D. T. Ngo. "Hardware and software design of the Programmable Displayphone." Displays 10, no. 4 (October 1989): 211–14. http://dx.doi.org/10.1016/0141-9382(89)90065-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
36

Sheliga, Michael, and Edwin Hsing-Mean Sha. "Hardware/Software co-design with the HMS framework." Journal of VLSI signal processing systems for signal, image and video technology 13, no. 1 (August 1996): 37–56. http://dx.doi.org/10.1007/bf00930666.

Full text
APA, Harvard, Vancouver, ISO, and other styles
37

Baldwin, Brian, Raveen R. Goundar, Mark Hamilton, and William P. Marnane. "Co- $$Z$$ ECC scalar multiplications for hardware, software and hardware–software co-design on embedded systems." Journal of Cryptographic Engineering 2, no. 4 (October 16, 2012): 221–40. http://dx.doi.org/10.1007/s13389-012-0042-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
38

Feng, Xiao Jing, Xi Li, Wang Chao, Xue Hai Zhou, and Jun Neng Zhang. "A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration." Advanced Materials Research 433-440 (January 2012): 5172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5172.

Full text
Abstract:
The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.
APA, Harvard, Vancouver, ISO, and other styles
39

King, Myron, Nirav Dave, and Arvind. "Automatic generation of hardware/software interfaces." ACM SIGPLAN Notices 47, no. 4 (June 2012): 325–36. http://dx.doi.org/10.1145/2248487.2151011.

Full text
APA, Harvard, Vancouver, ISO, and other styles
40

Lazear, Tom. "PC Hardware Developments and CAD Software." IEEE Computer Graphics and Applications 7, no. 10 (October 1987): 28–31. http://dx.doi.org/10.1109/mcg.1987.276843.

Full text
APA, Harvard, Vancouver, ISO, and other styles
41

Mérillion, Fabrice, and Gilles Muller. "Dealing with Hardware in Embedded Software." ACM SIGPLAN Notices 36, no. 8 (August 2001): 121–27. http://dx.doi.org/10.1145/384196.384214.

Full text
APA, Harvard, Vancouver, ISO, and other styles
42

Contreras, Luis, Sérgio Cruz, J. M. S. T. Motta, and Carlos H. Llanos. "Hardware and Software Co-design for the EKF Applied to the Mobile Robotics Localization Problem." International Journal of Machine Learning and Computing 5, no. 2 (April 2015): 101–5. http://dx.doi.org/10.7763/ijmlc.2015.v5.491.

Full text
APA, Harvard, Vancouver, ISO, and other styles
43

Yong Zhang, Kai Kuang Ma, and Qindong Yao. "A software/hardware co-design methodology for embedded microprocessor core design." IEEE Transactions on Consumer Electronics 45, no. 4 (1999): 1241–46. http://dx.doi.org/10.1109/30.809214.

Full text
APA, Harvard, Vancouver, ISO, and other styles
44

Nedjah, Nadia, and Luiza de Macedo Mourelle. "Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware co-design." Integration 40, no. 1 (January 2007): 36–44. http://dx.doi.org/10.1016/j.vlsi.2005.12.010.

Full text
APA, Harvard, Vancouver, ISO, and other styles
45

Müller, Jan, Dirk Fimmel, Renate Merker, and Rainer Schaffer. "A Hardware–Software System for Tomographic Reconstruction." Journal of Circuits, Systems and Computers 12, no. 02 (April 2003): 203–29. http://dx.doi.org/10.1142/s021812660300074x.

Full text
Abstract:
We present the design of a hardware–software system for the reconstruction of tomographic images. In a systematic approach we developed the parallel processor array, a reconfigurable hardware controller and processing kernel, and the software control up to the integration into a graphical user interface. The processor array acting as a hardware accelerator, is constructed using theoretical results and methods of application-specific hardware design. The reconfigurability of the system allows one to utilize a much wider realm of algorithms than the three reconstruction algorithms implemented so far. In the paper we discuss the system design at different levels from algorithm transformations to board development.
APA, Harvard, Vancouver, ISO, and other styles
46

Tsoeunyane, Lekhobola, Simon Winberg, and Michael Inggs. "Automatic Configurable Hardware Code Generation for Software-Defined Radios." Computers 7, no. 4 (October 19, 2018): 53. http://dx.doi.org/10.3390/computers7040053.

Full text
Abstract:
The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.
APA, Harvard, Vancouver, ISO, and other styles
47

Zhang, Jia Tian, Jian Guo Zhan, Zheng Guo Yan, Xiong He, and Lin Ma. "Design of Software and Hardware Based on JRB230240B LCD." Advanced Materials Research 301-303 (July 2011): 467–71. http://dx.doi.org/10.4028/www.scientific.net/amr.301-303.467.

Full text
Abstract:
This paper introduces the basic content of JRB320240B, including LCD tube foot function and operation sequence. Gives a kind of simple and practical hardware interface circuit of LCD and MCU. Design two general functions ,the painting line and circle; and indicate the algorithm of the bottom function. Then realize dials clock based on bottom function.
APA, Harvard, Vancouver, ISO, and other styles
48

Carchiolo, Vincenza, Michele Malgeri, and Giuseppe Mangioni. "TTL: a modular language for hardware/software systems design." Journal of Computer and System Sciences 66, no. 2 (March 2003): 293–315. http://dx.doi.org/10.1016/s0022-0000(03)00002-3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
49

Xiaoying Liang. "Hardware Software Co-Design for JPEG Encoder Test Bench." INTERNATIONAL JOURNAL ON Advances in Information Sciences and Service Sciences 4, no. 2 (February 15, 2012): 258–66. http://dx.doi.org/10.4156/aiss.vol4.issue2.32.

Full text
APA, Harvard, Vancouver, ISO, and other styles
50

López, M., J. Daugman, and E. Cantó. "Hardware–software co-design of an iris recognition algorithm." IET Information Security 5, no. 1 (2011): 60. http://dx.doi.org/10.1049/iet-ifs.2009.0267.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the bibliographies on the topic 'Hardware-software design' for other source types:
Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography