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Relevant bibliographies by topics / Hardware testing

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Journal articles
Dissertations / Theses
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Conference papers
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Academic literature on the topic 'Hardware testing'

Author: Grafiati

Published: 4 June 2021

Last updated: 30 May 2022

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Journal articles on the topic "Hardware testing"

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Krauβ, Stefan. "Hardware for ECU testing." ATZelektronik worldwide 3, no. 1 (February 2008): 52–55. http://dx.doi.org/10.1007/bf03242156.

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Zhi-hong, Liang, Luo Jian-zhen, and Liang Zhi-qiang. "System Recovery Testing of Hardware Firewall." Procedia Engineering 15 (2011): 4574–78. http://dx.doi.org/10.1016/j.proeng.2011.08.859.

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Torku, Kofi E., and Dave A. Kiesling. "Noise Problems in Testing VLSI Hardware." IEEE Design & Test of Computers 2, no. 6 (December 1985): 36–43. http://dx.doi.org/10.1109/mdt.1985.294795.

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Rajski, J., and J. Tyszer. "Testing of telecommunications hardware [Guest Editorial]." IEEE Communications Magazine 37, no. 6 (June 1999): 60–62. http://dx.doi.org/10.1109/mcom.1999.769275.

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Rajsuman, Rochit. "Special Issue on Digital Hardware Testing." VLSI Design 1, no. 4 (January 1, 1994): i. http://dx.doi.org/10.1155/1994/24312.

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Kundel, Ralf, Fridolin Siegmund, Rhaban Hark, Amr Rizk, and Boris Koldehofe. "Network Testing Utilizing Programmable Network Hardware." IEEE Communications Magazine 60, no. 2 (February 2022): 12–17. http://dx.doi.org/10.1109/mcom.001.2100191.

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Gouache, Thibault P., Christopher Brunskill, Gregory P. Scott, Yang Gao, Pierre Coste, and Yves Gourinat. "Regolith simulant preparation methods for hardware testing." Planetary and Space Science 58, no. 14-15 (December 2010): 1977–84. http://dx.doi.org/10.1016/j.pss.2010.09.021.

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Bazzazi, Amin, Mohammad Taghi Manzuri Shalmani, and Ali Mohammad Afshin Hemmatyar. "Hardware Trojan Detection Based on Logical Testing." Journal of Electronic Testing 33, no. 4 (June 22, 2017): 381–95. http://dx.doi.org/10.1007/s10836-017-5670-0.

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Kilaru, Chaitanya, Dr JKR Sastry, and Dr K RajaSekhara Rao. "Testing distributed embedded systems through logic analyzer." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 297. http://dx.doi.org/10.14419/ijet.v7i2.7.10601.

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Testing distributed embedded systems is complex as the individual systems connected on to the network are heterogeneous in nature.The communication system that is used for establishing the networking also varies greatly leading to different testing requirements. Testing of embedded systems can be carried using different methods that include Scaffolding, assert macros, instruction set simulators. In-circuit emulators, logic analyzers each requiring establishment of different testing environment required for undertaking actual testing. Testing of any embedded systems involves testing hardware, testing hardware dependent code, and testing hardware independent code. Logic analyzers are generally used for testing proper working of the Hardware.In this paper, a framework is presented using which testing of hardware distributed across the distributed embedded system using logic analyzer is presented.

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Karasyov, A. V., and I. A. Pustyl’nyak. "Hardware-software complex for testing digital control systems." Russian Electrical Engineering 79, no. 3 (March 2008): 127–29. http://dx.doi.org/10.3103/s1068371208030036.

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Dissertations / Theses on the topic "Hardware testing"

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Vanak, Salim K. "Complete functional testing of hardware descriptions." Thesis, University of Sheffield, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.251380.

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Rask, Ulf, and Pontus Mannestig. "Improvement of hardware basic testing : Identification and development of a scripted automation tool that will support hardware basic testing." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik och datavetenskap, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-3392.

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In the ever-increasing development pace, circuits and hardware are no exception. Hardware designs grow and circuits gets more complex at the same time as the market pressure lowers the expected time-to-market. In this rush, verification methods often lag behind. Hardware manufacturers must be aware of the importance of total verification if they want to avoid quality flaws and broken deadlines which in the long run will lead to delayed time-to-market, bad publicity and a decreasing market share. This paper discusses how a basic testing team may use an automated test environment in order to establish intellectual control regarding the testing and verification in a large hardware project. Company-specific factors that influence the design of an automated test environment are analyzed and a suggestion of a suitable environment is made. A prototype of the environment is constructed so that the project results may be evaluated in the real world. The thesis support the academic field in stating that large chips are hard to verify and that script-automation tools are one way to make verification of larger chips possible. Hardware verification should be made without complicated and untested software so that the debugging process only has the hardware to deal with. The thesis also indicates that an automated test tool increases the test rate, provides better test coverage and make regression testing feasible.

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Stern, Christopher. "Hardware-in-the-Loop rammeverk for UAV testing." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for teknisk kybernetikk, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13236.

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I denne rapporten presenteres et rammeverk for Hardware in the Loop Simulation (HILS) i forbindelse med utvikling av Unmanned Aerial Vehicle (UAV) styresystemer. Oppgaven er utført som masteroppgave ved Teknisk Kybernetikk, NTNU.Rammeverket er utviklet i Windows 7 og baserer seg på dynamisk simulator programmert i MATLAB/Simulink og Flight Gear er brukt for visuell fremstilling av flyet. Resultatet består av tre deler som til sammen kompletterer en fullstendig HIL simulator. Oppgaven avgrenser seg til det datatekniske omkring utviklingen av HIL. Det vil si at den matematiske bakgrunnen for flymodeller og simuleringen ikke er utledet.Kapittel 2 gir en innføring i begreper og maskinvare utviklet for Odin Recce UAV. Resultatet er deretter presentert i tre deler.I kapittel 3 er oppbyggingen av et driverbibliotek for avlesing av joystick gjennomgått i detalj for språkene: C/C++, Java, MATLAB og Simulink. En grafisk bakkestasjon for logging av data og styring av modellen utviklet i MATLAB i kapittel 4.Tilsvarende systemer er beskrevet og analysert som basis for videre utvikling som siste av resultatet tilhørende kapittel 5. Her også testprosedyrer og feilkilder redegjort for.Oppgaven presenterer en generell fremgangsmåte for HIL simulering. Rammeverket er kodet med lavest mulig kobling og høy kohesjon for at løsningen skal kunne gjenbrukes senere.Ved å tilpasse den dynamiske modellen til ønsket fysisk system kan en legge til reguleringssløyfer og kontrollsystem med mulighet for å påtrykke eventuelle feilsituasjoner brukeren får visuell tilbakemelding på flyets oppførsel via Flight Gear og bakkestasjonen gjør det også mulig å logge sanntidsdata.Prosjektet er en del av utviklingen omkring Odin Recce D6 UAV, men denne modellen er ikke brukt spesifikt i utviklingen. Mer informasjon om Odin er på www.odin.aero.

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Day, Steven M. "A Graphical Approach to Testing Real-Time Embedded Devices." DigitalCommons@CalPoly, 2009. https://digitalcommons.calpoly.edu/theses/114.

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Software Testing is both a vital and expensive part of the software development lifecycle. Improving the testing process has the potential for large returns. Current testing methodologies used to test real-time embedded devices are examined and the weaknesses in them are exposed. This leads to the introduction of a new graphical testing methodology based on flowcharts. The new approach is both a visual test creation program and an automated execution engine that together frame a new way of testing. The new methodology incorporates flow-based diagrams, visual layouts, and simple execution rules to improve upon traditional testing approaches. The new methodology is evaluated against other methodologies and is shown to provide significant improvements in the area of software testing.

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Orre, Martin. "Hardware Synthesis of Automated Electrical Fault Testing in Trucks." Thesis, KTH, Mikro- och nanosystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-168246.

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In modern trucks there is a number of control units, which tasks are varying; control of the engine, brakes, gearbox, etc. In order to ensure that these devices work properly, they must be thoroughly tested under normal conditions but also when they are exposed to stresses such as electrical faults (short circuit, breaks, etc.). A breakout box, BOB, is a type of test equipment used to stress test a controller by inducing electrical fault on its cables. It is done manually and is time consuming. The aim of this thesis is to develop an ABOB (Automated BreakOut Box). It should be placed in the driver's cab. It was designed in three different versions. Electrical faults are simulated. They along with a test program verify that no serious events occur for the vehicle. Literature studies of earlier works with automated electrical faults were made initially as a background for the selection of the automation method. The faults that have been implemented for the prototype of the ABOB is short circuit with di_erent supply voltages (including earth) and breakage. This report describes the development from a simple functional model to prototype with a focus on the hardware. The ABOB can run automatically without human interaction except at boot time. The ignition needs only to be switched on and the device can work in the evening and at night. The results were that the implemented ABOB could simulate the given electrical faults with verification. The automation method proved feasible. The work has been done in cooperation with Anna Bladh. This report takes up the hardware of the prototype for the three versions. Anna's report describes the software in the System design of automated test equipment for electrical control units into trucks.
I moderna lastbilar sitter ett flertal styrenheter, vars uppgifter varierar; styrning av motor, bromsar, växellåda osv. För att säkra att dessa enheter fungerar som de ska måste de testas noggrant - dels under normala förhållanden men också då de utsätts för påfrestningar såsom elektriska fel (kortslutning, avbrott osv.). En breakout box, BOB, ar en typ av testutrustning som används för att stress testa en styrenhet genom att inducera elektriska fel på dess kablage. Det görs manuellt och ar tidskrävande. Syftet med det här examensarbetet är att ta fram en ABOB (Automatiserad BreakOut Box). Den ska placeras i förarhytten. Under arbetets gång designades ABOB:en i tre olika utföranden. Elektriska fel simuleras. De tillsammans med ett här framtaget testprogram verifierar att inga händelser inträffar för fordonet. Litteraturstudier av tidigare arbeten med automatiserade elektriska fel gjordes inledningsvis som bakgrund för valet av automatiseringsmetod. Felen som har implementerats för ABOB-prototypen ar kortslutning med annan matningsspänning (inklusive jord) och avbrott. Denna rapport beskriver utvecklingen från en enkel funktionsmodell till färdig prototyp med fokus på hårdvaran. ABOB:n kan köras automatiskt utan att tillsyn erfordras utom vid uppstarten. Tändningen behöver bara slas på och enheten kan arbeta kvälls- och nattetid. Resultaten blev att den implementerade ABOB:en kunde simulera de givna elektriska felen med verifiering. Den framtagna automatiseringsmetoden visade sig genomförbar. Arbetet har skett i samarbete med Anna Bladh. Den här rapporten tar upp prototypens hårdvara för de tre versionerna. Annas rapport beskriver mjukvaran i System design of automated test equipment for electrical control units in trucks.

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Davis, Richard Christopher. "Functional testing of ASICs designed with hardware description languages." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36606.

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Belsick, Charlotte Ann. "Space Vehicle Testing." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/888.

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Requirement verification and validation is a critical component of building and delivering space vehicles with testing as the preferred method. This Master’s Project presents the space vehicle test process from planning through test design and execution. It starts with an overview of the requirements, validation, and verification. The four different verification methods are explained including examples as to what can go wrong if the verification is done incorrectly. Since the focus of this project is on test, test verification is emphasized. The philosophy behind testing, including the “why” and the methods, is presented. The different levels of testing, the test objectives, and the typical tests are discussed in detail. Descriptions of the different types of tests are provided including configurations and test challenges. While most individuals focus on hardware only, software is an integral part of any space product. As such, software testing, including mistakes and examples, is also presented. Since testing is often not performed flawlessly the first time, sections on anomalies, including determining root cause, corrective action, and retest is included. A brief discussion of defect detection in test is presented. The project is actually presented in total in the Appendix as a Power Point document.

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Patel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.

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Lei, Li. "Hardware/Software Interface Assurance with Conformance Checking." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2323.

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Hardware/Software (HW/SW) interfaces are pervasive in modern computer systems. Most of HW/SW interfaces are implemented by devices and their device drivers. Unfortunately, HW/SW interfaces are unreliable and insecure due to their intrinsic complexity and error-prone nature. Moreover, assuring HW/SW interface reliability and security is challenging. First, at the post-silicon validation stage, HW/SW integration validation is largely an ad-hoc and time-consuming process. Second, at the system deployment stage, transient hardware failures and malicious attacks make HW/SW interfaces vulnerable even after intensive testing and validation. In this dissertation, we present a comprehensive solution for HW/SW interface assurance over the system life cycle. This solution is composited of two major parts. First, our solution provides a systematic HW/SW co-validation framework which validates hardware and software together; Second, based on the co-validation framework, we design two schemes for assuring HW/SW interfaces over the system life cycle: (1) post-silicon HW/SW co-validation at the post-silicon validation stage; (2) HW/SW co-monitoring at the system deployment stage. Our HW/SW co-validation framework employs a key technique, conformance checking which checks the interface conformance between the device and its reference model. Furthermore, property checking is carried out to verify system properties over the interactions between the reference model and the driver. Based on the conformance between the reference model and the device, properties hold on the reference model/driver interface also hold on the device/driver interface. Conformance checking discovers inconsistencies between the device and its reference model thereby validating device interface implementations of both sides. Property checking detects both device and driver violations of HW/SW interface protocols. By detecting device and driver errors, our co-validation approach provides a systematic and ecient way to validate HW/SW interfaces. We developed two software tools which implement the two assurance schemes: DCC (Device Conformance Checker), a co-validation framework for post-silicon HW/SW integration validation; and CoMon (HW/SW Co-monitoring), a runtime verication framework for detecting bugs and malicious attacks across HW/SW interfaces. The two software tools lead to discovery of 42 bugs from four industry hardware devices, the device drivers, and their reference models. The results have demonstrated the signicance of our approach in HW/SW interface assurance of industry applications.

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Li, Min. "Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/29129.

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With the advances of very large scale integration (VLSI) technology, the feature size has been shrinking steadily together with the increase in the design complexity of logic circuits. As a result, the efforts taken for designing, testing, and debugging digital systems have increased tremendously. Although the electronic design automation (EDA) algorithms have been studied extensively to accelerate such processes, some computational intensive applications still take long execution times. This is especially the case for testing and validation. In order tomeet the time-to-market constraints and also to come up with a bug-free design or product, the work presented in this dissertation studies the acceleration of EDA algorithms on Graphics Processing Units (GPUs). This dissertation concentrates on a subset of EDA algorithms related to testing and validation. In particular, within the area of testing, fault simulation, diagnostic simulation and reliability analysis are explored. We also investigated the approaches to parallelize state justification on GPUs, which is one of the most difficult problems in the validation area. Firstly, we present an efficient parallel fault simulator, FSimGP2, which exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA Compute Unified Device Architecture (CUDA). A novel three-dimensional parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. The experimental results demonstrate a speedup of up to 4Ã compared to another GPU-based fault simulator. Then, another GPU based simulator is used to tackle an even more computation-intensive task, diagnostic fault simulation. The simulator is based on a two-stage framework which exploits high computation efficiency on the GPU. We introduce a fault pair based approach to alleviate the limited memory capacity on GPUs. Also, multi-fault-signature and dynamic load balancing techniques are introduced for the best usage of computing resources on-board. With continuously feature size scaling and advent of innovative nano-scale devices, the reliability analysis of the digital systems becomes more important nowadays. However, the computational cost to accurately analyze a large digital system is very high. We proposes an high performance reliability analysis tool on GPUs. To achieve highmemory bandwidth on GPUs, two algorithms for simulation scheduling and memory arrangement are proposed. Experimental results demonstrate that the parallel analysis tool is efficient, reliable and scalable. In the area of design validation, we investigate state justification. By employing the swarm intelligence and the power of parallelism on GPUs, we are able to efficiently find a trace that could help us reach the corner cases during the validation of a digital system. In summary, the work presented in this dissertation demonstrates that several applications in the area of digital design testing and validation can be successfully rearchitected to achieve maximal performance on GPUs and obtain significant speedups. The proposed algorithms based on GPU parallelism collectively aim to contribute to improving the performance of EDA tools in Computer aided design (CAD) community on GPUs and other many-core platforms.
Ph. D.

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Books on the topic "Hardware testing"

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Wunderlich, Hans-Joachim, ed. Models in Hardware Testing. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-3282-9.

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Digital hardware testing: Transistor-level fault modeling and testing. Boston: Artech House, 1992.

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Barner, Sharon, Ian Harris, Daniel Kroening, and Orna Raz, eds. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19583-9.

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Biere, Armin, Amir Nahir, and Tanja Vos, eds. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-39611-3.

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Piterman, Nir, ed. Hardware and Software: Verification and Testing. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-26287-1.

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Yorav, Karen, ed. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77966-7.

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Chockler, Hana, and Alan J. Hu, eds. Hardware and Software: Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01702-5.

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Strichman, Ofer, and Rachel Tzoref-Brill, eds. Hardware and Software: Verification and Testing. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70389-3.

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Ur, Shmuel, Eyal Bin, and Yaron Wolfsthal, eds. Hardware and Software, Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11678779.

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Bin, Eyal, Avi Ziv, and Shmuel Ur, eds. Hardware and Software, Verification and Testing. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-70889-6.

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Book chapters on the topic "Hardware testing"

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He, Ji, and Kenneth J. Turner. "Protocol-Inspired Hardware Testing." In IFIP Advances in Information and Communication Technology, 131–47. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-0-387-35567-2_9.

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Scalzo, Bert. "Benchmarking Hardware Options." In Database Benchmarking and Stress Testing, 135–45. Berkeley, CA: Apress, 2018. http://dx.doi.org/10.1007/978-1-4842-4008-3_6.

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Di Carlo, Stefano, and Paolo Prinetto. "Models in Memory Testing." In Models in Hardware Testing, 157–85. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_6.

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Figueras, Joan, Rosa Rodríguez-Montañés, and Daniel Arumí. "Open Defects in Nanometer Technologies." In Models in Hardware Testing, 1–31. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_1.

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Renovell, Michel, Florence Azais, Joan Figueras, Rosa Rodríguez-Montañés, and Daniel Arumí. "Models for Bridging Defects." In Models in Hardware Testing, 33–70. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_2.

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Reddy, Sudhakar M. "Models for Delay Faults." In Models in Hardware Testing, 71–103. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_3.

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Becker, Bernd, and Ilia Polian. "Fault Modeling for Simulation and ATPG." In Models in Hardware Testing, 105–31. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_4.

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Wunderlich, Hans-Joachim, and Stefan Holst. "Generalized Fault Modeling for Logic Diagnosis." In Models in Hardware Testing, 133–55. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_5.

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Girard, Patrick, and Hans-Joachim Wunderlich. "Models for Power-Aware Testing." In Models in Hardware Testing, 187–215. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_7.

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Arlat, Jean, and Yves Crouzet. "Physical Fault Models and Fault Tolerance." In Models in Hardware Testing, 217–55. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-90-481-3282-9_8.

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Conference papers on the topic "Hardware testing"

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Rath, Arjun Kumar, Debanjalee Roy, Dama Hari Teja, and Gutha Bharath Kumar. "Embedded Hardware Testing Using Bootloader." In 2020 International Conference on Smart Electronics and Communication (ICOSEC). IEEE, 2020. http://dx.doi.org/10.1109/icosec49089.2020.9215327.

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Majzoobi, M., F. Koushanfar, and M. Potkonjak. "Testing Techniques for Hardware Security." In 2008 IEEE International Test Conference. IEEE, 2008. http://dx.doi.org/10.1109/test.2008.4700636.

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Ozger, Erol, and Tim A. Drouven. "Hardware in the Loop Simulation for Micro Air Vehicles." In AIAA Flight Testing Conference. Reston, Virginia: American Institute of Aeronautics and Astronautics, 2016. http://dx.doi.org/10.2514/6.2016-3977.

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Schroeder, Kurt, and Joseph Robenson. "Improving Hardware-In-The-Loop Testing." In 2005 U.S. Air Force T&E Days. Reston, Virigina: American Institute of Aeronautics and Astronautics, 2005. http://dx.doi.org/10.2514/6.2005-7610.

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Zlotnick, Aviad, and Orna Raz. "Hardware-less testing for RAS software." In SYSTOR 2009: The Israeli Experimental Systems Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1534530.1534553.

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George-Andrei, Ursan, Plopa Olga, and Ursan Maria. "Testing Stand Using Hardware Description Languages." In 2021 International Conference on Electromechanical and Energy Systems (SIELMEN). IEEE, 2021. http://dx.doi.org/10.1109/sielmen53755.2021.9600334.

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Dupuis, Sophie, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, and Bruno Rouzeyre. "A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans." In 2014 IEEE 20th International On-Line Testing Symposium (IOLTS). IEEE, 2014. http://dx.doi.org/10.1109/iolts.2014.6873671.

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Samimi, Mohammad Saleh, Ehsan Aerabi, Zahra Kazemi, Mahdi Fazeli, and Ahmad Patooghy. "Hardware enlightening: No where to hide your Hardware Trojans!" In 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2016. http://dx.doi.org/10.1109/iolts.2016.7604712.

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Sunar, Berk. "Rise of the hardware Trojans." In 2011 IEEE 17th International On-Line Testing Symposium (IOLTS 2011). IEEE, 2011. http://dx.doi.org/10.1109/iolts.2011.5993826.

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KRANTZ, FRANK. "A new approach to testing space hardware." In 2nd Space Logistics Symposium. Reston, Virigina: American Institute of Aeronautics and Astronautics, 1988. http://dx.doi.org/10.2514/6.1988-4719.

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Reports on the topic "Hardware testing"

1

Goebel, J. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters. Office of Scientific and Technical Information (OSTI), February 2004. http://dx.doi.org/10.2172/826764.

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2

Murakami, Kei. Hardware-In-The-Loop Testing of Distributed Electronic Systems. Warrendale, PA: SAE International, May 2005. http://dx.doi.org/10.4271/2005-08-0080.

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3

McIntosh, John, and Klaehn Burkes. Power Hardware-in-the-Loop Testing of Distribution Solid State Transformers. Office of Scientific and Technical Information (OSTI), October 2018. http://dx.doi.org/10.2172/1476257.

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4

Burkholder, R. J., Robert J. Mariano, I. J. Gupta, and P. Schniter. Hardware-in-the-loop testing of wireless systems in realistic environments. Office of Scientific and Technical Information (OSTI), June 2006. http://dx.doi.org/10.2172/889418.

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5

Littlejohn, Bryce, Yiwen Chu, and Liv Wiik. Hardware Testing of the BaBar Drift Chamber Electronics Upgrade (SULI paper). Office of Scientific and Technical Information (OSTI), January 2006. http://dx.doi.org/10.2172/877992.

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6

Schkoda, Ryan, Curtiss Fox, Ramtin Hadidi, Vahan Gevorgian, Robb Wallen, and Scott Lambert. Hardware-in-the-Loop Testing of Utility-Scale Wind Turbine Generators. Office of Scientific and Technical Information (OSTI), January 2016. http://dx.doi.org/10.2172/1237305.

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7

Schoder, K., J. Langston, M. Steurer, S. Azongha, M. Sloderbeck, T. Chiocchio, C. Edrington, A. Farrell, J. Vaidya, and K. Yost. Hardware-in-the-Loop Testing of a High-Speed Generator Excitation Controller. Fort Belvoir, VA: Defense Technical Information Center, January 2010. http://dx.doi.org/10.21236/ada522750.

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8

Shenker, Steven, Rosana Yamasaki, and Tobias Kreuzinger. Testing of ABS Systems for 2-Wheelers via Hardware-in-the-Loop Technology. Warrendale, PA: SAE International, October 2013. http://dx.doi.org/10.4271/2013-32-9175.

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9

Stamp, Jason E., Derek H. Hart, and Bryan Richardson. Integration of Dynamic Simulation for Infrastructure and Full Hardware Testing Capability into SCEPTRE. Office of Scientific and Technical Information (OSTI), January 2016. http://dx.doi.org/10.2172/1599533.

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10

Trask, Richard P., and Robert A. Weller. Cyclic Fatigue Testing of Surface Mooring Hardware for the Arabian Sea Mixed Layer Dynamics Experiment. Fort Belvoir, VA: Defense Technical Information Center, December 1995. http://dx.doi.org/10.21236/ada304902.

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