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Vanak, Salim K. "Complete functional testing of hardware descriptions." Thesis, University of Sheffield, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.251380.
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Rask, Ulf, and Pontus Mannestig. "Improvement of hardware basic testing : Identification and development of a scripted automation tool that will support hardware basic testing." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik och datavetenskap, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-3392.
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In the ever-increasing development pace, circuits and hardware are no exception. Hardware designs grow and circuits gets more complex at the same time as the market pressure lowers the expected time-to-market. In this rush, verification methods often lag behind. Hardware manufacturers must be aware of the importance of total verification if they want to avoid quality flaws and broken deadlines which in the long run will lead to delayed time-to-market, bad publicity and a decreasing market share. This paper discusses how a basic testing team may use an automated test environment in order to establish intellectual control regarding the testing and verification in a large hardware project. Company-specific factors that influence the design of an automated test environment are analyzed and a suggestion of a suitable environment is made. A prototype of the environment is constructed so that the project results may be evaluated in the real world. The thesis support the academic field in stating that large chips are hard to verify and that script-automation tools are one way to make verification of larger chips possible. Hardware verification should be made without complicated and untested software so that the debugging process only has the hardware to deal with. The thesis also indicates that an automated test tool increases the test rate, provides better test coverage and make regression testing feasible.
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Stern, Christopher. "Hardware-in-the-Loop rammeverk for UAV testing." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for teknisk kybernetikk, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13236.
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I denne rapporten presenteres et rammeverk for Hardware in the Loop Simulation (HILS) i forbindelse med utvikling av Unmanned Aerial Vehicle (UAV) styresystemer. Oppgaven er utført som masteroppgave ved Teknisk Kybernetikk, NTNU.Rammeverket er utviklet i Windows 7 og baserer seg på dynamisk simulator programmert i MATLAB/Simulink og Flight Gear er brukt for visuell fremstilling av flyet. Resultatet består av tre deler som til sammen kompletterer en fullstendig HIL simulator. Oppgaven avgrenser seg til det datatekniske omkring utviklingen av HIL. Det vil si at den matematiske bakgrunnen for flymodeller og simuleringen ikke er utledet.Kapittel 2 gir en innføring i begreper og maskinvare utviklet for Odin Recce UAV. Resultatet er deretter presentert i tre deler.I kapittel 3 er oppbyggingen av et driverbibliotek for avlesing av joystick gjennomgått i detalj for språkene: C/C++, Java, MATLAB og Simulink. En grafisk bakkestasjon for logging av data og styring av modellen utviklet i MATLAB i kapittel 4.Tilsvarende systemer er beskrevet og analysert som basis for videre utvikling som siste av resultatet tilhørende kapittel 5. Her også testprosedyrer og feilkilder redegjort for.Oppgaven presenterer en generell fremgangsmåte for HIL simulering. Rammeverket er kodet med lavest mulig kobling og høy kohesjon for at løsningen skal kunne gjenbrukes senere.Ved å tilpasse den dynamiske modellen til ønsket fysisk system kan en legge til reguleringssløyfer og kontrollsystem med mulighet for å påtrykke eventuelle feilsituasjoner brukeren får visuell tilbakemelding på flyets oppførsel via Flight Gear og bakkestasjonen gjør det også mulig å logge sanntidsdata.Prosjektet er en del av utviklingen omkring Odin Recce D6 UAV, men denne modellen er ikke brukt spesifikt i utviklingen. Mer informasjon om Odin er på www.odin.aero.
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Day, Steven M. "A Graphical Approach to Testing Real-Time Embedded Devices." DigitalCommons@CalPoly, 2009. https://digitalcommons.calpoly.edu/theses/114.
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Software Testing is both a vital and expensive part of the software development lifecycle. Improving the testing process has the potential for large returns. Current testing methodologies used to test real-time embedded devices are examined and the weaknesses in them are exposed. This leads to the introduction of a new graphical testing methodology based on flowcharts. The new approach is both a visual test creation program and an automated execution engine that together frame a new way of testing. The new methodology incorporates flow-based diagrams, visual layouts, and simple execution rules to improve upon traditional testing approaches. The new methodology is evaluated against other methodologies and is shown to provide significant improvements in the area of software testing.
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Orre, Martin. "Hardware Synthesis of Automated Electrical Fault Testing in Trucks." Thesis, KTH, Mikro- och nanosystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-168246.
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In modern trucks there is a number of control units, which tasks are varying; control of the engine, brakes, gearbox, etc. In order to ensure that these devices work properly, they must be thoroughly tested under normal conditions but also when they are exposed to stresses such as electrical faults (short circuit, breaks, etc.). A breakout box, BOB, is a type of test equipment used to stress test a controller by inducing electrical fault on its cables. It is done manually and is time consuming. The aim of this thesis is to develop an ABOB (Automated BreakOut Box). It should be placed in the driver's cab. It was designed in three different versions. Electrical faults are simulated. They along with a test program verify that no serious events occur for the vehicle. Literature studies of earlier works with automated electrical faults were made initially as a background for the selection of the automation method. The faults that have been implemented for the prototype of the ABOB is short circuit with di_erent supply voltages (including earth) and breakage. This report describes the development from a simple functional model to prototype with a focus on the hardware. The ABOB can run automatically without human interaction except at boot time. The ignition needs only to be switched on and the device can work in the evening and at night. The results were that the implemented ABOB could simulate the given electrical faults with verification. The automation method proved feasible. The work has been done in cooperation with Anna Bladh. This report takes up the hardware of the prototype for the three versions. Anna's report describes the software in the System design of automated test equipment for electrical control units into trucks.I moderna lastbilar sitter ett flertal styrenheter, vars uppgifter varierar; styrning av motor, bromsar, växellåda osv. För att säkra att dessa enheter fungerar som de ska måste de testas noggrant - dels under normala förhållanden men också då de utsätts för påfrestningar såsom elektriska fel (kortslutning, avbrott osv.). En breakout box, BOB, ar en typ av testutrustning som används för att stress testa en styrenhet genom att inducera elektriska fel på dess kablage. Det görs manuellt och ar tidskrävande. Syftet med det här examensarbetet är att ta fram en ABOB (Automatiserad BreakOut Box). Den ska placeras i förarhytten. Under arbetets gång designades ABOB:en i tre olika utföranden. Elektriska fel simuleras. De tillsammans med ett här framtaget testprogram verifierar att inga händelser inträffar för fordonet. Litteraturstudier av tidigare arbeten med automatiserade elektriska fel gjordes inledningsvis som bakgrund för valet av automatiseringsmetod. Felen som har implementerats för ABOB-prototypen ar kortslutning med annan matningsspänning (inklusive jord) och avbrott. Denna rapport beskriver utvecklingen från en enkel funktionsmodell till färdig prototyp med fokus på hårdvaran. ABOB:n kan köras automatiskt utan att tillsyn erfordras utom vid uppstarten. Tändningen behöver bara slas på och enheten kan arbeta kvälls- och nattetid. Resultaten blev att den implementerade ABOB:en kunde simulera de givna elektriska felen med verifiering. Den framtagna automatiseringsmetoden visade sig genomförbar. Arbetet har skett i samarbete med Anna Bladh. Den här rapporten tar upp prototypens hårdvara för de tre versionerna. Annas rapport beskriver mjukvaran i System design of automated test equipment for electrical control units in trucks.
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Davis, Richard Christopher. "Functional testing of ASICs designed with hardware description languages." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36606.
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Belsick, Charlotte Ann. "Space Vehicle Testing." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/888.
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Requirement verification and validation is a critical component of building and delivering space vehicles with testing as the preferred method. This Master’s Project presents the space vehicle test process from planning through test design and execution. It starts with an overview of the requirements, validation, and verification. The four different verification methods are explained including examples as to what can go wrong if the verification is done incorrectly. Since the focus of this project is on test, test verification is emphasized. The philosophy behind testing, including the “why” and the methods, is presented. The different levels of testing, the test objectives, and the typical tests are discussed in detail. Descriptions of the different types of tests are provided including configurations and test challenges. While most individuals focus on hardware only, software is an integral part of any space product. As such, software testing, including mistakes and examples, is also presented. Since testing is often not performed flawlessly the first time, sections on anomalies, including determining root cause, corrective action, and retest is included. A brief discussion of defect detection in test is presented.
The project is actually presented in total in the Appendix as a Power Point document.
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Patel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.
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Lei, Li. "Hardware/Software Interface Assurance with Conformance Checking." PDXScholar, 2015. https://pdxscholar.library.pdx.edu/open_access_etds/2323.
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Hardware/Software (HW/SW) interfaces are pervasive in modern computer systems. Most of HW/SW interfaces are implemented by devices and their device drivers. Unfortunately, HW/SW interfaces are unreliable and insecure due to their intrinsic complexity and error-prone nature. Moreover, assuring HW/SW interface reliability and security is challenging. First, at the post-silicon validation stage, HW/SW integration validation is largely an ad-hoc and time-consuming process. Second, at the system deployment stage, transient hardware failures and malicious attacks make HW/SW interfaces vulnerable even after intensive testing and validation. In this dissertation, we present a comprehensive solution for HW/SW interface assurance over the system life cycle. This solution is composited of two major parts. First, our solution provides a systematic HW/SW co-validation framework which validates hardware and software together; Second, based on the co-validation framework, we design two schemes for assuring HW/SW interfaces over the system life cycle: (1) post-silicon HW/SW co-validation at the post-silicon validation stage; (2) HW/SW co-monitoring at the system deployment stage. Our HW/SW co-validation framework employs a key technique, conformance checking which checks the interface conformance between the device and its reference model. Furthermore, property checking is carried out to verify system properties over the interactions between the reference model and the driver. Based on the conformance between the reference model and the device, properties hold on the reference model/driver interface also hold on the device/driver interface. Conformance checking discovers inconsistencies between the device and its reference model thereby validating device interface implementations of both sides. Property checking detects both device and driver violations of HW/SW interface protocols. By detecting device and driver errors, our co-validation approach provides a systematic and ecient way to validate HW/SW interfaces. We developed two software tools which implement the two assurance schemes: DCC (Device Conformance Checker), a co-validation framework for post-silicon HW/SW integration validation; and CoMon (HW/SW Co-monitoring), a runtime verication framework for detecting bugs and malicious attacks across HW/SW interfaces. The two software tools lead to discovery of 42 bugs from four industry hardware devices, the device drivers, and their reference models. The results have demonstrated the signicance of our approach in HW/SW interface assurance of industry applications.
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Li, Min. "Acceleration of Hardware Testing and Validation Algorithms using Graphics Processing Units." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/29129.
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With the advances of very large scale integration (VLSI) technology, the feature size has been shrinking steadily together with the increase in the design complexity of logic circuits. As a result, the efforts taken for designing, testing, and debugging digital systems have increased tremendously. Although the electronic design automation (EDA) algorithms have been studied extensively to accelerate such processes, some computational intensive applications still take long execution times. This is especially the case for testing and validation. In order tomeet the time-to-market constraints and also to come up with a bug-free design or product, the work presented in this dissertation studies the acceleration of EDA algorithms on Graphics Processing Units (GPUs). This dissertation concentrates on a subset of EDA algorithms related to testing and validation. In particular, within the area of testing, fault simulation, diagnostic simulation and reliability analysis are explored. We also investigated the approaches to parallelize state justification on GPUs, which is one of the most difficult problems in the validation area.
Firstly, we present an efficient parallel fault simulator, FSimGP2, which exploits the high degree of parallelism supported by a state-of-the-art graphic processing unit (GPU) with the NVIDIA Compute Unified Device Architecture (CUDA). A novel three-dimensional parallel fault simulation technique is proposed to achieve extremely high computation efficiency on the GPU. The experimental results demonstrate a speedup of up to 4Ã compared to another GPU-based fault simulator.
Then, another GPU based simulator is used to tackle an even more computation-intensive task, diagnostic fault simulation. The simulator is based on a two-stage framework which exploits high computation efficiency on the GPU. We introduce a fault pair based approach to alleviate the limited memory capacity on GPUs. Also, multi-fault-signature and dynamic load balancing techniques are introduced for the best usage of computing resources on-board.
With continuously feature size scaling and advent of innovative nano-scale devices, the reliability analysis of the digital systems becomes more important nowadays. However, the computational cost to accurately analyze a large digital system is very high. We proposes an high performance reliability analysis tool on GPUs. To achieve highmemory bandwidth on GPUs, two algorithms for simulation scheduling and memory arrangement are proposed. Experimental results demonstrate that the parallel analysis tool is efficient, reliable and scalable.
In the area of design validation, we investigate state justification. By employing the swarm intelligence and the power of parallelism on GPUs, we are able to efficiently find a trace that could help us reach the corner cases during the validation of a digital system.
In summary, the work presented in this dissertation demonstrates that several applications in the area of digital design testing and validation can be successfully rearchitected to achieve maximal performance on GPUs and obtain significant speedups. The proposed algorithms based on GPU parallelism collectively aim to contribute to improving the performance of EDA tools in Computer aided design (CAD) community on GPUs and other many-core platforms.Ph. D.
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Williams, Steve. "Advanced Hardware-in-the-Loop Testing Assures RF Communication System Success." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/604299.
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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, CaliforniaRF Communication (COMMS) systems where receivers and transmitters are in motion must be proven rigorously over an array of natural RF link perturbations such as Carrier Doppler shift, Signal Doppler shift, delay, path loss and noise. These perturbations play significant roles in COMMS systems involving satellites, aircraft, UAVs, missiles, targets and ground stations. In these applications, COMMS system devices must also be tested against increasingly sophisticated intentional and unintentional interference, which must result in negligible impact on quality of service. Field testing and use of traditional test and measurement equipment will need to be substantially augmented with physics-compliant channel emulation equipment that broadens the scope, depth and coverage of such tests, while decreasing R&D and test costs and driving in quality. This paper describes dynamic link emulation driven by advanced antenna and motion modeling, detailed propagation models and link budget methods for realistic, nominal and worst-case hardware-in-the-loop test and verification.
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Krug, Margrit Reni. "Aumento da testabilidade do hardware com auxilio de técnicas de teste de software." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12672.
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O projeto, seja ele de software ou hardware, envolve uma série de atividades que, apesar das técnicas, ferramentas e métodos empregados, não estão livres de erros que podem levar ao mau funcionamento do produto final. Estes erros podem ocorrer durante a especificação do projeto, como também em estágios finais do desenvolvimento ou no processo de manufatura. A fim de minimizar prejuízos é necessário garantir a qualidade do sistema a partir da verificação do projeto, da validação de protótipo e do teste de fabricação. Por muito tempo o teste de hardware e o teste de software foram estudados como disciplinas completamente independentes. Porém, similaridades entre o desenvolvimento de software e o projeto de hardware já foram exploradas com sucesso em adaptações de técnicas originalmente desenvolvidas para um sendo utilizadas por outro. Um exemplo é a cobertura de código, que foi inicialmente desenvolvida para o teste de software, e agora é comumente utilizada na verificação de hardware. Visto que dispositivos são descritos em linguagem de descrição de hardware, e estas possuem características semelhantes às linguagens de programação, parece uma boa alternativa valer-se desta semelhança para utilizar os métodos propostos pela engenharia de software para garantir a qualidade do hardware desenvolvido. Utilizar tais métodos para gerar padrões de teste para dispositivos de hardware descritos em HDL (Hardware Description Language) e identificar nestas descrições características que, alteradas, aumentem a testabilidade dos mesmos, são os principais objetivos desta tese.Both software and hardware designs require several tasks to increase reliability and ensure high quality of the final system. Although different techniques, tools and methods can be applied, error free products are difficult to be achieved. Errors may occur on design specification, on development stages and also during manufacturing process. To increase system quality and minimize costs it is mandatory to perform design verification, prototype validation and manufacturing test. For a long time hardware and software tests were studied as disciplines completely apart. However, similarities between software development and hardware design have already been explored successfully by adapting techniques originally developed for one of them, and applying to the other. For instance, code coverage concept and methods were firstly developed for software testing, but nowadays are commonly used in hardware verification. Due to the high similarity observed between software programming languages and hardware description languages (HDL), it seems to be a valuable approach applying software engineering techniques to help ensuring a high quality hardware device. Therefore, the main purpose of this thesis is to use such techniques to extract test patterns from HDL descriptions of hardware devices and to identify at these descriptions means to increase hardware testability.
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Stepp, Ronald K. "Electronic combat hardware-in-the-loop testing in an open air environment." Thesis, Monterey, California. Naval Postgraduate School, 1994. http://hdl.handle.net/10945/28154.
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Approved for public release; distribution is unlimitedThis thesis evaluates the usefulness of open air hardware-in-the-loop testing. This evaluation is based upon the comparison of two indoor hardware-in- the-loop facilities to an outdoor hardware-in-the-loop facility. In addition to the comparison of the facilities, this thesis presents feedback from three sources who have hardware-in-the-loop test experience at both indoor and outdoor facilities. Based on the research conducted, the conclusion of this thesis is that the established electronic combat test process should be formally modified to include open air hardware-in-the-loop testing. Electronic combat hardware-in- the-loop testing
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Meirelles, Paulo Roberto Miranda. "Teste integrado de software e hardware : reusando casos de teste de software em teste de microprocessadores." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2008. http://hdl.handle.net/10183/25520.
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Sistemas embarcados estão mais complexos e são cada vez mais utilizados em contextos que exigem muitos recursos computacionais. Isso significa que o hardware embarcado pode ser composto por vários processadores, memórias, partes reconfiguráveis e ASIPs integrados em um único silício. Adicionalmente, o software embarcados pode conter muitas rotinas de programação executadas sob restrição de processamento e memória. Esse cenário estabelece uma forte dependência entre o hardware e o software embarcado. Portanto, o teste de um sistema embarcado compreende o teste do hardware e do software. Neste contexto, a reutilização de procedimentos e estruturas de teste é um caminho para se reduzir o tempo de desenvolvimento e execução dos testes. Neste trabalho é apresentado um método de teste integrado de hardware e software. Nesse método, casos de teste desenvolvidos para testar o software embarcado também são usados para testar o seu processador. Comparou-se os custos e cobertura de falhas do método proposto com técnicas de auto-teste funcional. Os resultados experimentais demonstraram que foi possível reduzir os custos de aplicação e geração do teste do sistema usando um método de teste integrado de software e hardware.Embedded Systems are more complexity. Nowadays, they are used in context that requires computational resources. This means an embedded hardware may be compound of several processors, memories, reconfigurable parts, and ASICs integrated in a single die. Additionally, an embedded software has a lot of programming procedures, which is under processing and memory constraints. This scenario provides a stronger connection between hardware and software. Therefore, the test of an embedded system is the test of both, hardware and software. In this context, reuse of testing structures and procedures is one way to reduce the test development time and execution. This work presents an integrated test of software and software method. In this method, test cases developed to test the embedded software are also used to test its processor. We compared the costs and fault coverage of our proposed method with techniques of functional self-test. The experimental results show that it is possible to reduce the implementation and test generation costs using an integrated test of software and hardware.
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Sarica, Serhad. "Uml-based Functional System Testing." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612943/index.pdf.
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Effectiveness of system testing, in specific phases such as design verification, requirements validation, test planning and generation, system integration and system testing are considered. Software as well as hardware test issues are reviewed. Metrics related to system testing are specified. The current system testing processes in a large Turkish military electronic systems manufacturer are reviewed, specific problems are identified and UML-based behavioral testing is proposed as an improved process. The current process and the proposed process are compared in terms of test coverage, test effectiveness and test effort metrics.
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Grungxu, Lungile Leonard. "Aspect of a hardware-in-the-loop integrated test system." Thesis, Stellenbosch : Stellenbosch University, 2003. http://hdl.handle.net/10019.1/53292.
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Thesis (MScEng)--University of Stellenbosch, 2003.ENGLISH ABSTRACT: A multiprocessor hardware-in-the-Ioop operating system was developed for the Integrated Test System (ITS) and is aimed at implementing the ITS as a space emulation vehicle. The thesis contains a study of satellite orbits, Kepler elements, geomagnetic fields and communication protocol between the processors. The system structure consists of an orbit generator, a core-operating system and is presented with a study of the satellite sensors. In implementing the orbit propagator, there was a need to pay special attention to the Halving algorithm, the Newton Raphson method and the True Solution. These algorithms were used to calculate the true anomaly angle as a function of eccentric anomaly. The communications protocol was tested and all the errors, with their solutions, have been discussed. A concept of a geomagnetic field emulator has also been included in the hardware-in-theloop operating system. The evaluation of those aspects of the system and the conclusion are presented together with recommendations.
AFRIKAANSE OPSOMMING: 'n multiprosesseerder Hardeware in die lus bedryfstelsel is ontwikkel vir 'n Geintegreerde Toets Stelsel (ITS) en poog om die ITS te implementeer as 'n ruimte emulasie stelsel. Die tesis behels die studie van sateliet wentelbane, Kepler wentelbaan elemente, geomagnetiese velde en kommunikasie protokolle tussen die prosesseerders. Die stelsel struktuur betaal uit 'n wentelbaan propageerder, 'n kern bedryfstelsel en 'n studie van satelliet instrumentasie. As 'n deel van die implementering van die wentelbaan propageerder is die halveer algoritme, Newton-Raphson algoritme en die ware oplossing as numeriese oplossings ondersoek. Die kommunikasie protokol is getoets en foute ondersoek en word bespreek. 'n konsep vir 'n Geomagnetiese veld emulasie word die hardeware in die lus stelsel ingesluit. Die stelsel word ge-ewalueer en die gevolgtrekkings en aanbevelings gemaak.
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Eriksson, Jens. "Evaluation of Hardware Test Methods for VLSI Systems." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-239.
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The increasing complexity and decreasing technology feature sizes of electronic designs has caused the challenge of testing to grow over the last decades. The purpose of this thesis was to evaluate different hardware test methods/approaches based on their applicability in a complex SoC design. Among the aspects that were investigated are test implementation effort, test efficiency and the performance penalties implicated by the test.
This report starts out by presenting a general introduction to the basics of hardware testing. It then moves on to review available standards and methodologies. In the end one of the more interesting methods is investigated through a case study. The method that was chosen for the case study has been implemented on a DSP, and is rather new and not as prolific as many of the standards discussed in the report. This type of method appears to show promising results when compared to more traditional ones.
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Valea, Emanuele. "Security Techniques for Test Infrastructures." Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS042.
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Les infrastructures de test sont essentielles pour l'industrie moderne des circuits intégrés. La nécessité de détecter les défauts de fabrication et de prévenir les défaillances des systèmes sur le terrain, rend leur présence inévitable dans chaque circuit intégré et ses sous-modules. Malheureusement, les infrastructures de test représentent également une menace pour la sécurité en raison de la contrôlabilité et de l'observabilité accrues qu'elles offrent généralement sur les circuits internes. Dans cette thèse, nous présentons une analyse complète des menaces existantes et des contre-mesures respectives, en fournissant également une classification et une taxonomie de l'état de l'art. En outre, nous proposons de nouvelles solutions de sécurité, basées sur la cryptographie légère, pour la conception d'infrastructures de test. Toutes les contre-mesures proposées appartiennent à la catégorie des solutions dit de scan encryption et leur but est de garantir la confidentialité des données et l'authentification des utilisateurs. Chaque solution proposée est évaluée en termes de coûts de mise en œuvre et de capacités de sécurité. Les travaux qui ont été réalisés et qui sont présentés dans cette thèse, indiquent que la scan encryption est une solution prometteuse pour garantir une conception sécurisée des infrastructures de testTest infrastructures are crucial to the modern Integrated Circuits (ICs) industry. The necessity of detecting manufacturing defects and preventing system failures in the field, makes their presence inevitable in every IC and its sub-modules. Unfortunately, test infrastructures also represent a security threat due to the augmented controllability and observability on the IC internals that they typically provide. In this thesis, we present a comprehensive analysis of the existing threats and the respective countermeasures, also providing a classification and a taxonomy of the state-of-the-art. Furthermore, we propose new security solutions, based on lightweight cryptography, for the design of test infrastructures. All proposed countermeasures belong to the category of scan encryption solutions and their purpose is to guarantee data confidentiality and user authentication. Each proposed solution is evaluated in terms of implementation costs and security capabilities. The works that have been carried out and are presented in this thesis, indicate that scan encryption is a promising solution for granting a secure design of test infrastructures
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Schwendtner, Daniel Thomas. "Development of a thermal vacuum system for application in space hardware environmental testing." Thesis, Montana State University, 2012. http://etd.lib.montana.edu/etd/2012/schwendtner/SchwendtnerD0512.pdf.
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Since 2001 the Space Science and Engineering Lab (SSEL) at Montana State University has designed and built a variety of space hardware, as well as developed the facilities necessary for environmental testing of flight hardware. In late 2005, the SSEL began developing a system to simulate the vacuum environment of near-space which would allow for rudimentary outgassing testing as well as thermal testing of electronics and spacecraft components. To truly test hardware and validate hardware analysis and design, the ability to cycle between the expected temperature extremes in a vacuum environment was essential. The usage and operation of thermal vacuum systems was investigated, requirements for a thermal vacuum system were defined, and possible design options were considered. A Finite Element Analysis (FEA) was performed to predict the heat load in Watts on the system when a 40 kg nanosatellite (50 cm x 50 cm x 60 cm) was cycled between -40°C and +80°C at rates of temperature change from 1°C/min to 5°C/min. Additional research, analysis, and design was performed on a thermal shroud surrounding the same nanosatellite and operating under identical conditions. Radiation heat transfer between the satellite on the shroud's inside and the vacuum chamber on the shroud's outside was calculated using the radiation network approach. The LU decomposition method was used to solve the resulting set of simultaneous equations. From the results, a design was selected for the system base plate on which the nanosatellite rested, with the capability of sinking or sourcing 833 W of heat power. Similarly, the thermal shroud was designed to sink or source up to 704 W through the shroud body, and up to 229 W through the shroud top. Testing was performed to validate both the FEA model and the physical hardware. Temperature measurements were taken during system testing to validate the design, and as a means to compare the FEA model of the base plate and the radiation heat transfer calculations with the performance of the system hardware. The results indicated that the system functioned as designed, that it met the design requirements, and that it was capable of completely and safely testing satellites and other space hardware.
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Bergkvist, Johannes. "Testing degradation in a complex vehicle electrical system using Hardware-In-the-Loop." Thesis, Linköping University, Vehicular Systems, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16549.
Full textAbstract:
Functionality in the automotive industry is becoming more complex, withcomplex communication networks between control systems. Information isshared among many control systems and extensive testing ensures high quality.
Degradations testing, that has the objective to test functionality with some faultpresent, is performed on single control systems, but is not frequently performed on the entire electrical system. There is a wish for testing degradation automatically on the complete electrical system in a so called Hardware-In-the-Loop laboratory.
A technique is needed to perform these tests on a regular basis.Problems with testing degradation in complex communication systems will bedescribed. Methods and solutions to tackle these problems are suggested, thatfinally end up with two independent test strategies. One strategy is suited to test degradation on new functionality. The other strategy is to investigate effects in the entire electrical system. Both strategies have been implemented in a Hardware-In-the-Loop laboratory and evaluated.
21
Chakraborty, Rajat Subhra. "Hardware Security through Design Obfuscation." Cleveland, Ohio : Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.
Full textAbstract:
Thesis (Doctor of Philosophy)--Case Western Reserve University, 2010Department of EECS - Computer Engineering Title from PDF (viewed on 2010-05-25) Includes abstract Includes bibliographical references and appendices Available online via the OhioLINK ETD Center
22
Kujiraoka, Scott R. "USING COMMERCIAL-OFF-THE-SHELF (COTS) PRODUCTS IN THE DESIGN OF MISSILE FLIGHT-QUALIFIED HARDWARE." International Foundation for Telemetering, 2001. http://hdl.handle.net/10150/607685.
Full textAbstract:
International Telemetering Conference Proceedings / October 22-25, 2001 / Riviera Hotel and Convention Center, Las Vegas, NevadaDuring these times of acquisition reform in the federal government, various missile systems are being forced into using Commercial-off-the-Shelf (COTS) products in the design of their subsystems. However one problem that this presents is the lack of configuration management. There is a concern that the manufacturer will modify the product without informing the end user. This may have a severe effect on the performance of an already flight qualified subsystem. An example of how one program is dealing with this issue will be discussed.
23
Shanyour, Basim. "Testing and Security Considerations in Presence of Process Variations." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1804.
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Process variations is one of the most challenging phenomena in deep submicron. Delay fault testing becomes more complicated because gate delays are not fixed but instead, they are statistical quantities due to the variations in the transistor characteristics. On the other hand, testing for hardware Trojan is also challenging in the presence of process variations because it can easily mask the impact of the inserted Trojan. This work consists of two parts. In the first part, an approach to detect ultra-low-power no-payload Trojans by analyzing IDDT waveforms at each gate in the presence of process variations is presented. The approach uses a novel ATPG to insert a small number of current sensors to analyze the behavior of individual gates at the IDDT waveform. The second part focuses on identifying a test set that maximizes the defect coverage for path delay fault. The proposed approach utilizes Monte-Carlo simulation efficiently and uses a machine-learning algorithm to select a small test set with high detect coverage.
24
Misselhorn, Werner Ekhard. "Verification of hardware-in-the-loop as a valid testing method for suspension development." Diss., Pretoria : [s.n.], 2004. http://upetd.up.ac.za/thesis/available/etd-07282005-082527.
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Butler, Michael P. "Test methods and custom hardware for functional testing of a high speed GaAs DRAM." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA274859.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, September 1993.Thesis advisor(s): Douglas J. Fouts. "September 1993." Includes bibliographical references. Also available online.
26
Moats, Michael L. "Automation of hardware-in-the-loop testing of control systems for unmanned air vehicles." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA284833.
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Nowocin, John Kendall. "Microgrid risk reduction for design and validation testing using controller hardware in the loop." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111906.
Full textAbstract:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 83-84).
As electric power customers look for reductions in the cost of energy, increases in the level of service reliability, and reductions in greenhouse gas emissions a common solution is a microgrid. These microgrids are smaller power systems where distributed energy resources are used to power local electric load(s). This work demonstrates an improved approach to planning microgrids via satellite imagery and has a case study in applied to India, the contribution of an anonymized real world test feeder to the power systems community, transition of geospatial information to a digital twin for an analysis of microgrid availability, and the process of developing a controller hardware in the loop platform to integrate physical equipment controllers from manufacturers and the development, testing, and validation of models by applying a general framework. The controller hardware in the loop platform (CHIL) can achieve the testing capabilities for microgrid controllers as more functions are required. CHIL is one method to validate microgrid controller performance before equipment is installed. Microgrids promise to improve the reliability, resiliency, and efficiency of the nation's aging but critical power distribution systems. Models of common power systems equipment were developed to achieve realistic interactions with the microgrid controller under test. The CHIL testbed that was built at MIT Lincoln Laboratory is described, and the equipment models developed are openly available. This testbed was able to test microgrid controllers under a variety of scenarios, including islanding, short-circuit analysis, and cyber attack. The effort resulted in the successful demonstration of HIL simulation technology at two Technical Symposiums organized by the Mass Clean Energy Center (CEC) for utility distribution system engineers, project developers, systems integrators, equipment vendors, academia, regulators, City of Boston officials, and Commonwealth officials. Actual microgrid controller hardware was integrated along with actual commercial generator and inverter controller hardware in the microgrid feeder that is becoming the IEEE reference standard.
by John Kendall Nowocin.
Ph. D.
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Quadrino, Meghan Kathleen. "Testing the attitude determination and control of a CubeSat with hardware-in-the-loop." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91382.
Full textAbstract:
Thesis: S.M., Massachusetts Institute of Technology, Department of Aeronautics and Astronautics, 2014.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 175-180).
This thesis presents a methodology for testing the attitude determination and control of a CubeSat within a constrained environment. This approach first evaluates the concept of operations of the satellite mission, then takes into account the limitations of the test environment, formulates test plans that can validate algorithms with hardware-in-the-loop, and presents a model by which these tests can be evaluated. The Microsized Microwave Atmospheric Satellite (MicroMAS), a dual-spinner 3U CubeSat, is used as a case study to demonstrate both the overall methodology and the validation model. Laboratory experiments were performed with a one-degree-of-freedom rotation test set-up inside of a Helmholtz Cage magnetic field simulator. The theoretical development of the control algorithms and design choices are discussed. A software model of the controller, hardware, and test environment was used to evaluate the results from these experimental tests. The results showed that, using the designed control system, the satellite model is able to successfully detumble itself, achieve a desired angular rotation, and compensate for the momentum introduced by a rotating payload. The test data are analyzed and show that the control system is able to meet the mission pointing requirements of maintaining within 1 degree (3[sigma]) deviation from the nominal LVLH attitude after its slew maneuver, before payload spin-up. During its science operation mode, the tests showed a pointing deviation from nominal attitude of about 2.2 degrees (3[sigma]). The details of the constraints and limitations of the test environment and their impacts are discussed.
by Meghan Kathleen Quadrino.
S.M.
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Coteli, Mert Burkay. "Testing Effectiveness And Effort In Software Product Lines." Master's thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615345/index.pdf.
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Software product lines (SPL) aim to decrease the total software development cost by the help of reusability and variability. However, the increasing number of variations for the delivery types of products would result in increasing cost of the verification and validation process. Total testing cost of development can also be decreased by reusing test cases and scripts. The main objective of this study is to increase testing effectiveness while minimizing testing effort. Four different cases consisting of Aselsan&rsquos SPL projects have been studied. Firstly, FIG Basis path method was applied at the functional testing phase, and an increase on the testing effectiveness value has been observed. FIG basis path method is a test case sequence generation technique using the feature tree of the software component. This method would be preferable to improve testing effectiveness on the functional verification phase. The second study was on testing effort estimation. There are two testing approaches for SPL projects, namely infrastructure based and product focused testing. These two techniques have been compared in terms of testing effort. It was a study that gives an idea to test managers about the selection of the proper testing technique. Thirdly, reusability techniques were evaluated. Reusability of testing artifacts can be used to decrease the total testing effort. Two reusability techniques for testing artifacts were compared in terms of the number of test cases. Proper technique would be chosen to decrease testing effort. Finally, selection of a reference application on platform tests was proposed and software products were grouped according to the redundancy values. Then, testing effectiveness values were evaluated for each test grouping.
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Wennberg, Per, and Viktor Danielson. "Evaluation of a Testing Process to Plan and Implement an Improved Test System : A Case Study, Evaluation and Implementation in Lab-VIEW/TestStand." Thesis, Linköpings universitet, Programvara och system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-130770.
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In order to ensure the quality of a product, the provider of the product must performcomplete testing of the product. This fact increases the demands on the test systems usedto conduct the testing, the system needs to be reliable.When developing new software for a company, sometimes a requirements specificationcreated at the beginning of the project is not enough. Details of the desired implementationmay get lost when working with a general requirements specification.This thesis presents a case study of how a certain company work with their test systems.The aim of the case study was to find where the largest points of improvements could bemade in a new test system, which was to be implemented during this thesis work. Theimplementation of this new system was done in LabVIEW in conjunction with TestStandand this process is covered in this thesis.The performed case study revealed that the employees at the company found robustnessand usability to be the key factors in a new test system. During and after the implementationof the new system, it was evaluated regarding these two metrics, this process isalso covered in this thesis.
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Mahanti, Kritee. "Hardware-in-the-loop simulation and testing of the ADCS of the Beyond Atlas CubeSat." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-292413.
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Beyond Atlas, a company based in Danderyd, Sweden is working on a Low Earth Orbit (LEO) 3U-CubeSat (Cube Satellite) exploration mission. As part of their maiden mission, they aim to validate the navigation, propulsion, and communication techniques of a CubeSat while it performs orbital maneuvers to collect photographs of space debris. This study briefly introduces the Beyond Atlas mission and its CubeSat design. The thesis work then mainly focuses on the details of the Attitude Determination and Control System (ADCS) peripherals and software onboard the CubeSat. It describes the Attitude Determination peripherals such as the sun sensor, star tracker, magnetometer, and gyroscope that will be onboard the CubeSat, followed by the description of the Attitude Control peripherals, namely, the magnetorquer and the reaction wheel. Subsequently, it discusses the hardware’s configuration and interface techniques with the flight computer that specifically caters to the satellite’s attitude determination and control aspect. Finally, it reports a Hardware-in-the-loop (HIL) testing methodology, and the corresponding results obtained from the unit testing of the peripherals and the operational testing (Detumbling and Pointing) of the ADCS of the Beyond Atlas CubeSat. Based on the testing results, the report concludes that the selected hardware for the Beyond Atlas mission, when integrated, can perform the principal functionalities.Beyond Atlas baserat i Danderyd, Sverige är ett företag som arbetar med ett rymdutforsknings projekt. Som en del av deras jungfruuppdrag används en 3UCubeSat för att validera navigering, framdrivning och kommunikationsningar medan den utför banmanövrer för relativnavigation och tar bilder av rymdskräp. Denna studie introducerar kort Beyond Atlas uppdraget och dess CubeSat-design. Rapporten fokuserar sedan huvudsakligen på detaljerna i ADCS kringutrustning och programvara ombord på CubeSat. Den beskriver attitydkännande utrustning som solsensorer, startracker, magnetometer och rategyro som finns ombord, följt av beskrivningen av attitydst yrenheter, nämligen magnetorquer och reaktionshjul. Därefter diskuteras hårdvarans konfiguration och gränssnitt med navigationsdatorn som dedikerat utför satellitens attitydbestämning och attitydkontroll ADCS. Slutligen rapporterar studien testmetodik av inledande validerings-tester (Detumbling and Pointing) av ADCS i Beyond Atlas CubeSat. Baserat på testresultaten drar rapporten slutsatsen att den valda hårdvaran för satelliten kan utföra de primära navigationsfunktionerna.
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Medisetti, Praveen. "REAL TIME SIMULATION AND HARDWARE-IN-LOOP TESTING OF A HYBRID ELECTRIC VEHICLE CONTROL SYSTEM." University of Akron / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=akron1170439524.
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Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.
Full textAbstract:
BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system.
In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit.Ph. D.
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Chandorkar, Chaitrali Santosh. "Data Driven Feed Forward Adaptive Testing." PDXScholar, 2013. https://pdxscholar.library.pdx.edu/open_access_etds/1049.
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Test cost is a critical component in the overall cost of the product. Test cost varies in direct proportion with test time. This thesis introduces a data driven feed forward adaptive technique for reducing test time at wafer sort while maintaining the product defect level. Test data from first insertion of wafer is statistically analyzed to make a decision about adaptive test flow at subsequent insertions.
The data driven feed forward technique uses a statistical screen to analyze test data from first probe of wafer and provides recommendations for test elimination at second insertions. At the second insertion dies are subjected to only the optimum number of tests for a reduced test flow. This technique is applicable only for the products which are tested at two or more insertions.
The statistical screen identifies the dies for reduced test flow based upon correlation of tests across insertions. The tests which are repeated at both the insertions and are highly correlated are the candidates of elimination at second insertion.
The feed forward technique is applied to a mixed signal analog product and figures of merit are evaluated. Application of technique to the production data shows that there is an average 55% test time reduction when a single site is tested per touchdown and up to 10% when 16 sites are tested in parallel per touchdown.
35
Sevcik, Keith Wayne Oh Paul Yu. "A hardware-in-the-loop testing facility for unmanned aerial vehicle sensor suites and control algorithms /." Philadelphia, Pa. : Drexel University, 2010. http://hdl.handle.net/1860/3262.
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Sarala, Devi Krishna. "Hardware and software integration and testing for the automation of bright-field microscopy for tuberculosis detection." Master's thesis, University of Cape Town, 2011. http://hdl.handle.net/11427/11360.
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Automated microscopy for the detection of tuberculosis (TB) in sputum smears would reduce the load on technicians, especially in countries with a high TB burden. This dissertation reports on the development and testing of an automated system built around a conventional microscope for the detection of TB in Ziehl-Neelsen (ZN) stained sputum smears. Microscope auto-focusing, image analysis and stage movement were integrated. Images were captured at 40x magnification.
37
Björklund, Fredrik, and Elin Karlström. "Enabling Testing of Lateral Active Safety Functions in a Multi-rate Hardware in the Loop Environment." Thesis, Linköpings universitet, Fordonssystem, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-139076.
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As the development of vehicles moves towards shorter development time, new ways of verifying the vehicle performance is needed in order to begin the verification process at an earlier stage. A great extent of this development regards active safety, which is a collection name for systems that help both avoid accidents and minimize the effects of a collision, e.g brake assist and steering control systems. Development of these active safety functions requires extensive testing and verification in order to guarantee the performance of the functions in different situations. One way of testing these functions is to include them in a Hardware in the Loop simulation, where the involved hardware from the real vehicle are included in the simulation loop. This master thesis investigates the possibility to test lateral active safety functions in a hardware in the loop simulation environment consisting of multiple subsystems working on different frequencies. The subsystems are all dependent of the output from other subsystems, forming an algebraic loop between them. Simulation using multiple hardware and subsystems working on different frequencies introduces latency in the simulation. The effect of the latency is investigated and proposed solutions are presented. In order to enable testing of lateral active safety functions, a steering model which enables the servo motor to steer the vehicle is integrated in the simulation environment and validated.
38
Senbayrak, Ziya. "Effects Of Spl Domain Engineering On Testing Cost And Maintainability." Master's thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615495/index.pdf.
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A software product line (SPL) consists of a set of software-intensive systems sharing a common, managed set of features that satisfy the specific needs of a particular market segment or mission and that are developed from a common set of core assets in a prescribed way. Together with testing of final deliverable products developed within the SPL, called Integration Testing, particularly important in this context is the way individual hardware as well as software components in an SPL are tested and certified for usage within the SPL. This study investigates specific approaches and techniques proposed in the literature for unit testing in the SPL context. Problems inherent to this issue were studied and possible solutions aiming towards systematic and effective testing of hardware as well as software units in SPLs have been proposed. The specific problems of SPL testing in ASELSAN were investigated in the light of these possible solutions and their applicability as well as their benefits were quantitatively assessed.
39
Sharma, Carthik. "SUSTAINABLE FAULT-HANDLING OF RECONFIGURABLE LOGIC USING THROUGHPUT-DRIVEN ASSESSMENT." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3559.
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A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect's role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Computer Engineering PhD
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Guthrie, Thomas G. "Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2005. http://library.nps.navy.mil/uhtbin/hyperion/05Mar%5FGuthrie.pdf.
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Root, Eric. "A Re-Configurable Hardware-in-the-Loop Flight Simulator." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1090939388.
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Cintura, Manuel. "An Embedded Data Logger for In-Vehicle Testing." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23841/.
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This thesis describes an embedded data logger project, composed of software part (in C++ language) and hardware part (Raspberry Pi). It is illustrated the whole procedure from the start of the project with requirements to the end with the experimental results and validation phase. The device is able to acquire, in a synchronous way, videos, CAN and Serial logs from the vehicle under test.
43
Gafurov, Salimzhan A., Viktor M. Reshetov, Vera A. Salmina, and Heikki Handroos. "Multi-operated HIL Test Bench for Testing Underwater Robot’s Buoyancy Variation System." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-200590.
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Nowadays underwater gliders have become to play a vital role in ocean exploration and allow to obtain the valuable information about underwater environment. The traditional approach to the development of such vehicles requires a thorough design of each subsystem and conducting a number of expensive full scale tests for validation the accuracy of connections between these subsystems. However, present requirements to cost-effective development of underwater vehicles need the development of a reliable sampling and testing platform that allows the conducting a preliminary design of components and systems (hardware and software) of the vehicle, its simulation and finally testing and verification of missions. This paper describes the development of the HIL test bench for underwater applications. Paper discuses some advantages of HIL methodology provides a brief overview of buoyancy variation systems. In this paper we focused on hydraulic part of the developed test bench and its architecture, environment and tools. Some obtained results of several buoyancy variation systems testing are described in this paper. These results have allowed us to estimate the most efficient design of the buoyancy variation system. The main contribution of this work is to present a powerful tool for engineers to find hidden errors in underwater gliders development process and to improve the integration between glider’s subsystems by gaining insights into their operation and dynamics.
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Bolien, Mario. "Hybrid testing of an aerial refuelling drogue." Thesis, University of Bath, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.761036.
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Hybrid testing is an emerging technique for system emulation that uses a transfer system composed of actuators and sensors to couple physical tests of a critical component or substructure to a numerical simulation of the remainder of a system and its complete operating environment. The realisation of modern real-time hybrid tests for multi-body contact-impact problems often proves infeasible due to (i) hardware with bandwidth limitations and (ii) the unavailability of control schemes that provide satisfactory force and position tracking in the presence of sharp non-linearities or discontinuities. Where this is the case, the possibility of employing a pseudo-dynamic technique remains, enabling tests to be conducted on an enlarged time scale thus relaxing bothbandwidth and response time constraints and providing inherent loop stability. Exploiting the pseudo-dynamic technique, this thesis presents the development of Robotic Pseudo-Dynamic Testing (RPsDT), a dedicated method that specifically targets the realisation of hybrid tests for multi-body contact-impact problems using commercial off- the shelve (COTS) industrial robotic manipulators. The RPsDT method is evaluated in on-ground studies of air-to-air refuelling (AAR) maneuvers with probe-hose-drogue systems where the critical contact and coupling phase is tested pseudo-dynamicallywith full-scale refuelling hardware while the flight regime is emulated in simulation. It is shown that the RPsDT method can faithfully reproduce the dominant contact impact phenomena between probe and drogue while minor discrepancies result from the absence of rate-dependant damping in the force feedback measurements. In combination with full-speed robot controlled contact tests, reliable estimates for impact forces, strain distributions and drogue responses to off-centre hits are obtained providing extensive improvements over current predictive capabilities for the in-flight behaviour of refuelling hardware and it is concluded that the technique shows great promise for industrial applications.
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Zeltner, Wolff Johannes. "Development of software for MALTE, a system for automated testing of line current supervision andinterference monitoring devices." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-243639.
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The aim of the project is to develop software to automatically test line current supervision and interference monitoring devices for Bombardier trains. The software, called MALTE, it to replace the manual testing done by an engineer, thereby freeing up the tester to do other tasks, and increasing the test rigorousness. The test software, written in LabView, was developed in tandem with a hardware rack, with interfaces to the train hardware enabling communication between the two, to set test conditions and simulate the environment encountered by the hardware when on the train. When completed, MALTE was found to be an order of magnitude faster than a test engineer performing the tests, meaning a large save in time and cost for the engineering team.
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Zhou, Zhuohang, and Martin Nilsson. "Design and Implementation of Angular Vibration Testing Equipment." Thesis, Blekinge Tekniska Högskola, Institutionen för maskinteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-16822.
Full textAbstract:
This thesis is done by two students from Blekinge Institute of Technology as an end of the master of engineering program with emphasis on applied mechanics. The thesis is done in cooperation with Axis Communications AB in Lund which develop surveillance cameras. The task was to design and implement an Angular Vibration Testing Equipment. Axis needs this to test their surveillance cameras for angular vibrations. These vibrations occur usually on cameras located on poles placed at roads and at train stations. The thesis has been carried out in three different phases where the first phase handled a deeper understanding of the problem, planning and investigating of related works. Axis has a solution for smaller cameras called Shakespeare MK I and this was used as an inspiration for us. The second phase included concept generation and concept evaluation. This has been done with brainstorming, workshop and concept scoring. At the last phase a prototype was built and tested and a detailed design was made. Two versions of the prototype were made and they showed that the concept works well. The project resulted in a working prototype that can transform linear motion to rotation around two axes. A drawing and a cost calculation were made for the final concept. The final construction is still not completely optimized and has improvement and adjustment possibilities that might be needed.
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Rao, Sanat R. "A hierarchical approach to effective test generation for VHDL behavioral models." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-08042009-040513/.
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Nilsson, Andreas. "Debug Interface for 56000 DSP." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-9196.
Full textAbstract:
The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.
The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.
In the project 4 blocks has been designed:
The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.
The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.
A text terminal program for Linux has also been programmed for handling the PC side communication.
The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.
The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.
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Goulkhah, Mohammad (Monty). "Waveform relaxation based hardware-in-the-loop simulation." Cigre Canada, 2014. http://hdl.handle.net/1993/31012.
Full textAbstract:
This thesis introduces an alternative potentially low cost solution for hardware-in-the-loop (HIL) simulation based on the waveform relaxation (WR) method. The WR tech-nique is extended so that, without the need for a real-time simulator, the behaviour of an actual piece of physical hardware can nevertheless be tested as though it were connected to a large external electrical network. This is achieved by simulating the external network on an off-line electromagnetic transients (EMT) simulation program, and utilizing iterative exchange of waveforms between the simulation and the hardware by means of a spe-cialized Real-Time Player/Recorder (RTPR) interface device. The approach is referred to as waveform relaxation based hardware-in-the-loop (WR-HIL) simulation.
To make the method possible, the thesis introduces several new innovations for stabi-lizing and accelerating the WR-HIL algorithm. It is shown that the classical WR shows poor or no convergence when at least one of the subsystems is an actual device. The noise and analog-digital converters’ quantization errors and other hardware disturbances can affect the waveforms and cause the WR to diverge. Therefore, the application of the WR method in performing HIL simulation is not straightforward and the classical WR need to be modified accordingly.
Three convergence techniques are proposed to improve the WR-HIL simulation con-vergence. Each technique is evaluated by an experimental example. The stability of the WR-HIL simulation is studied and a stabilization technique is proposed to provide suffi-cient conditions for the simulation stability.
The approach is also extended to include the optimization of the parameters of power system controllers located in geographically distant places. The WR-HIL simulation technique is presented with several examples. At the end of the thesis, suggestions for the future work are presented.February 2016
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Soverini, Davide. "Development of testing procedures for the πLUP read-out board." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/17044/.
Full textAbstract:
Durante i prossimi anni, un gran numero di laboratori saranno impegnati in un programma di upgrade dei principali esperimenti al Large Hadron Collider (LHC), chiamato upgrade Fase-II. L’Istituto Nazionale di Fisica Nucleare (INFN) e il gruppo A Toroidal
LHC Apparatus (ATLAS) di Bologna hanno sviluppato un prototipo di una nuova scheda chiamata PIxel detector high Luminosity UPgrade (PILUP), la quale é una possibile candidata per il rinnovamento del sistema Data AQuisition (DAQ) di ATLAS. Le principali caratteristiche di questa scheda sono il processore installato (dual-core ARM), la enorme larghezza di banda di comunicazione (fino a 60 Gbps tramite fibre ottiche) e la comunicazione con il PC tramite bus PCIe dedicato di seconda generazione.
Durante il mio lavoro di tesi, ho disegnato e sviluppato un sistema di test pensato per valutare i componenti della scheda e una procedura di test automatizzata, controllata da remoto da un programma software, per valutare la qualitá delle connessioni veloci.
I test dimostrano che la PiLUP soddisfa tutti i requisiti in termini di affidabilitá della trasmissione dati con alcune precisazioni.
Sebbene la PiLUP é stata progettata per soddisfare un compito specifico, é altamente versatile e potrebbe adattarsi a diverse applicazioni: la piú importante é la capacitá di gestire la comunicazione con la scheda principale dell’upgrade DAQ di ATLAS, la Front-End LInk eXchange (FELIX), utilizzando diversi protocolli di comunicazione (GigaBit Transceiver e Full-Mode). Questo é stato il primo passo della collaborazione internazionale
con il gruppo FELIX iniziato nel luglio 2017: i laboratori e gli istituti americani, olandesi, italiani, oltre al CERN, sono
coinvolti in questa partnership, collaborando a soluzioni di nuove schede di lettura.
Infine, un’altra applicazione della PiLUP é di utilizzarla come emulatore di diversi dispositivi, come il nuovo chip di lettura RD53A.