Relevant bibliographies by topics / Hardware Write Blocker Device

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Hardware Write Blocker Device'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "Hardware Write Blocker Device"

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Meffert, Christopher S., Ibrahim Baggili, and Frank Breitinger. "Deleting collected digital evidence by exploiting a widely adopted hardware write blocker." Digital Investigation 18 (August 2016): S87—S96. http://dx.doi.org/10.1016/j.diin.2016.04.004.

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Raychaudhuri, Kumarshankar, and M. George Christopher. "An Empirical study to determine the role of file-system in modification of hash value." International Journal of Cybersecurity Intelligence and Cybercrime 3, no. 1 (February 28, 2020): 24–41. http://dx.doi.org/10.52306/03010320nptv7468.

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In digital forensics, maintaining the integrity of digital exhibits is an essential aspect of the entire investigation and examination process, which is established using the technique of hashing. Lack of knowledge, while handling digital exhibits, might lead to unintentional alteration of computed hash, rendering the exhibit unacceptable in the court of Law. The hash value of a physical drive does not solely depend upon the data files present in it but also its file-system. Therefore, any change to the file-system might result in the change of the disk hash, even when the data files within it remain untouched. In this paper, our objective is to study the role of file-system in modification of the hash value. We examine and analyse the changes in the file-system of a NTFS formatted USB storage device, which leads to modification in its hash value when the device is plugged-in to the computer system without using write-blocker. The outcome of this research would justify the importance of write blockers while handling digital exhibits and also substantiate that the alteration in hash value of a storage device might not be an indication that data within the device has been tampered with.
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White, Marvin H., Yu (Richard) Wang, Stephen J. Wrazien, and Yijie (Sandy) Zhao. "ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY." International Journal of High Speed Electronics and Systems 16, no. 02 (June 2006): 479–501. http://dx.doi.org/10.1142/s0129156406003801.

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This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.
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Zand, Ramtin, Arman Roohi, and Ronald F. DeMara. "Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 9 (September 2017): 2394–401. http://dx.doi.org/10.1109/tvlsi.2017.2699579.

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Maia, Rafael de Oliveira, Francisco Assis da Silva, Mário Augusto Pazoti, Leandro Luiz de Almeida, and Danillo Roberto Pereira. "DESENVOLVIMENTO DE UM DISPOSITIVO PARA APOIO AO ENSINO DE COMPUTAÇÃO E ROBÓTICA." Colloquium Exactarum 6, no. 2 (August 29, 2014): 71–85. http://dx.doi.org/10.5747/ce.2014.v06.n2.e077.

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In this work we proposed the development of an alternative device as a motivating element to learn computer science and robotics using the Raspberry PI and Arduino boards. The connections of all hardware used to build the device called Betabot are presented and are also reported the technologies used for programming the Betabot. An environment for writing programs to run at Betabot was developed. With this environment it is possible to write programs in the Python programming language, using libraries with functions specific to the device. With the Betabot using a webcam and through image processing search for patterns like faces, circles, squares and colors. The device also has functions to move servos and motors, and capture values returned by some kindsof sensors connected to communication ports. From this work, it was possible to develop a device that is easy to be manipulated and programmed, which can be used to support the teaching of computer science and robotics.
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Zang, Jie, Xiao Li Wang, and Zhong Hua Yan. "Design of a USB OTG Mass Storage Module Based on LM3S9B90." Advanced Materials Research 588-589 (November 2012): 735–38. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.735.

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This paper introduces the method of design a USB On-The-Go (OTG) mass storage module according to USB 2.0 specification, which bases on embedded systems LM3S9B90. This module’s hardware system and software system is described, focusing on the implementation of USB host system. The module realizes USB OTG function, not only can realize functions of read and write USB mass storage devices, but also can exchange data with USB host as a USB mass storage device, can be used as an extension of USB system and has good application value.
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Guillemenet, Y., L. Torres, G. Sassatelli, and N. Bruchon. "On the Use of Magnetic RAMs in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–9. http://dx.doi.org/10.1155/2008/723950.

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This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.
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Cui, Zhou Juan, and Liao Lin Hu. "Design of SDH Positive/Zero/Negative Justification Circuits Based on FPGA." Advanced Materials Research 748 (August 2013): 874–78. http://dx.doi.org/10.4028/www.scientific.net/amr.748.874.

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A successful design which used FPGA to do Positive/Zero/Negative Justification for adapting E1 (2.048Mbit/s) to SDH C-12 is presented. Gray code is adopted to realize the sampling of write pointer in reading clock domain and induct frequency doubling technology to deduct/insert reading clock, and a positioning counting device is set to complete the positioning insert of specified bytes. Asynchronous FIFO and Ping-Pong operation technique are both adopted. The design realizes stimulation, placement and routing under Quartus II 9.0 circumstances. It is a reusable hardware module which increases performance when compared to existing solutions.
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Chakraborty, Indranil, Amogh Agrawal, Akhilesh Jaiswal, Gopalakrishnan Srinivasan, and Kaushik Roy. "In situ unsupervised learning using stochastic switching in magneto-electric magnetic tunnel junctions." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2164 (December 23, 2019): 20190157. http://dx.doi.org/10.1098/rsta.2019.0157.

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Spiking neural networks (SNNs) offer a bio-plausible and potentially power-efficient alternative to conventional deep learning. Although there has been progress towards implementing SNN functionalities in custom CMOS-based hardware using beyond Von Neumann architectures, the power-efficiency of the human brain has remained elusive. This has necessitated investigations of novel material systems which can efficiently mimic the functional units of SNNs, such as neurons and synapses. In this paper, we present a magnetoelectric–magnetic tunnel junction (ME-MTJ) device as a synapse. We arrange these synapses in a crossbar fashion and perform in situ unsupervised learning. We leverage the capacitive nature of write-ports in ME-MTJs, wherein by applying appropriately shaped voltage pulses across the write-port, the ME-MTJ can be switched in a probabilistic manner. We further exploit the sigmoidal switching characteristics of ME-MTJ to tune the synapses to follow the well-known spike timing-dependent plasticity (STDP) rule in a stochastic fashion. Finally, we use the stochastic STDP rule in ME-MTJ synapses to simulate a two-layered SNN to perform image classification tasks on a handwritten digit dataset. Thus, the capacitive write-port and the decoupled-nature of read-write path of ME-MTJs allow us to construct a transistor-less crossbar, suitable for energy-efficient implementation of in situ learning in SNNs. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.
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Ma, Jun, Jiang Chun Ren, Zhi Ying Wang, Jiang Jiang Wu, Yong Cheng, and Song Zhu Mei. "Implementing Efficient Management and Security of Removable Storage by FVM." Applied Mechanics and Materials 197 (September 2012): 467–72. http://dx.doi.org/10.4028/www.scientific.net/amm.197.467.

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The security usage and management of removable storage devices has become a vital problem for enterprises and individuals. However, the required strict security policies for preventing unauthorized access to sensitive data raise the decrease of usability and flexibility. The main problem rests on the binding between security and application domains which stifles the initiative of the devices on themselves. This paper presents TRS, an efficient active architecture that binds a feather-weight virtual machine (FVM) to the removable storage device. It is designed based on an inside-bound smart card as well as the chip operation system (COS) which builds a trust channel between the FVM and the device. The FVM is set up by a trust chain and provides isolated usage environment for process accessing the device which prevents the obtained data from leakage. Finally, we implement a USB flash disk we call as UTrustDisk based on the hardware structure of Amordisk which is a security product of Nationz Technologies Inc. The results show the average overhead of read and write is 7.5% and 11.5%.
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Dissertations / Theses on the topic "Hardware Write Blocker Device"

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Bengtsson, Johnny. "Forensisk hårddiskkloning och undersökning av hårddiskskrivskydd." Thesis, Linköping University, Department of Science and Technology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2378.

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Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd bedöms ha tillräckligt pålitliga skyddsprinciper, vilket motiveras av dess oberoende från både hårdvara och operativsystem.

Vidare undersöks hårdvaruskrivskyddet Image MASSter(TM) Drive Lock från Intelligent Computer Solutions (ICS). Några egentliga slutsatser gick inte dra av kretskonstruktionen, bortsett från att den är uppbyggd kring en FPGA (Xilinx Spartan-II, XC2S15) med tillhörande PROM (XC17S15APC).

En egenutvecklad idé till autenticieringsmetod för hårddiskkloner föreslås som ett tillägg till arbetet. Principen bygger på att komplettera hårddiskklonen med unik information om hårddisk såväl kloningsomständigheter, vilka sammanflätas genom XOR-operation av komponenternas hashsummor.Autenticieringsmetoden kan vid sjösättning möjligen öka rättsäkerheten för både utredarna och den som står misstänkt vid en brottsutredning.

Arbetet är till stora delar utfört vid och på uppdrag av Statens kriminaltekniska laboratorium (SKL) i Linköping.

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Book chapters on the topic "Hardware Write Blocker Device"

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Hughes, Ciaran, Joshua Isaacson, Anastasia Perry, Ranbel F. Sun, and Jessica Turner. "What Is a Qubit?" In Quantum Computing for the Quantum Curious, 7–16. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-61601-4_2.

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AbstractIn classical computers, information is represented as the binary digits 0 or 1. These are called bits. For example, the number 1 in an 8-bit binary representation is written as 00000001. The number 2 is represented as 00000010. We place extra zeros in front to write every number with 8-bits total, which is called one byte. In fact, every classical computer translates these bits into the human readable information on your electronic device. The document you read or video you watch is encoded in the computer binary language in terms of these 1’s and 0’s. Computer hardware understands the 1-bit as an electrical current flowing through a wire (in a transistor) while the 0-bit is the absence of an electrical current in a wire. These electrical signals can be thought of as “on” (the 1-bit) or “off” (the 0-bit). Your computer then decodes the classical 1 or 0 bits into words or videos, etc.
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Christou, Ioannis T., Sofoklis Efremidis, and Aikaterini Roukounaki. "A CASE Tool for Java Mobile Computing Applications." In Advancing the Next-Generation of Mobile Computing, 212–25. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0119-2.ch014.

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The market for applications developed for mobile devices is growing as the hardware capabilities increase while costs drop. At the same time, the inability to write code once becomes a noticeable problem resulting in the time consuming task of porting an application to a variety of mobile devices, which is true for languages like Java that have been designed to be portable across a range of hardware platforms. As a result, porting a Java application written for one device to another is often a tedious and time-consuming task for developers. This paper presents an intelligent CASE tool that assists the porting of Java mobile applications by automatically generating Java code fragments for the target SDK. SeqFinder automatically generates all minimal method invocation sequences that lead to an object of a specific type, thus relieving the programmer of manually searching the manufacturer-provided SDK Java archives. However, this tool is not applicable only to the Java ME platform and has been used as a fast type-browser for J2SE/J2EE applications.
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Conference papers on the topic "Hardware Write Blocker Device"

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Rebello Januário, Leonardo, Gustavo Henrique Müller, Alex Luciano Roesler Rese, Rudimar Luís Scaranto Dazzi, and Thiago Felski Pereira. "Máquina de Turing Analógica para Ensino de Linguagens Formais e Autômatos." In Computer on the Beach. São José: Universidade do Vale do Itajaí, 2021. http://dx.doi.org/10.14210/cotb.v12.p531-533.

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The article describes the development of a practical device for teachingin the area of Computer Theory. In the study, an adaptationof the Turing Machine is presented, using hardware and softwareintegration to interpret Formal Languages. Simulating an Automaton,sensors and motors are used to move the device head to the leftand right and to read and write the input tape. The developmentof the mechanism is described in two parts, the first includes thehardware that consists of the construction and adaptation of theTuring Machine, the second the implementation of the software andcommunication part between both. The developed device, allowsthe interpretation of a binary alphabet (0, 1), where an input word isaccepted, and as an output result, such device rejected or acceptedthe word.
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Journal articles
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