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Journal articles on the topic 'High-k Dielectric Material'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Susarla, Sandhya, Thierry Tsafack, Peter Samora Owuor, et al. "High-K dielectric sulfur-selenium alloys." Science Advances 5, no. 5 (2019): eaau9785. http://dx.doi.org/10.1126/sciadv.aau9785.

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Upcoming advancements in flexible technology require mechanically compliant dielectric materials. Current dielectrics have either high dielectric constant, K (e.g., metal oxides) or good flexibility (e.g., polymers). Here, we achieve a golden mean of these properties and obtain a lightweight, viscoelastic, high-K dielectric material by combining two nonpolar, brittle constituents, namely, sulfur (S) and selenium (Se). This S-Se alloy retains polymer-like mechanical flexibility along with a dielectric strength (40 kV/mm) and a high dielectric constant (K = 74 at 1 MHz) similar to those of estab

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2

Ghule, B., and M. Laad. "Polymer Composites with Improved Dielectric Properties: A Review." Ukrainian Journal of Physics 66, no. 2 (2021): 166. http://dx.doi.org/10.15407/ujpe66.2.166.

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Materials exhibiting high dielectric constant (k) values find applications in capacitors, gate dielectrics, dielectric elastomers, energy storage device, while materials with low dielectric constant are required in electronic packaging and other such applications. Traditionally, high k value materials are associated with high dielectric losses, frequency-dependent dielectric behavior, and high loading of a filler. Materials with low k possess a low thermal conductivity. This creates the new challenges in the development of dielectric materials in both kinds of applications. Use of high dielect

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3

Dixit, Ankita, and Navneet Gupta. "Simulations of the CNFETs using different high-k gate dielectrics." Bulletin of Electrical Engineering and Informatics 9, no. 3 (2020): 943–49. http://dx.doi.org/10.11591/eei.v9i3.1784.

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In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2.

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4

Ankita, Dixit, and Gupta Navneet. "Simulations of the CNFETs using different high-k gate dielectrics." Bulletin of Electrical Engineering and Informatics 9, no. 3 (2020): 943–49. https://doi.org/10.11591/eei.v9i3.1784.

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In this paper we presented the analysis of carbon nanotube field effect transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49 nm and the CNFETs have been fabricated with the CNT diameter of ~1.5 nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO

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5

Hall, Stephe, Octavian Buiu, Ivona Z. Mitrovic, Yi Lu, and William M. Davey. "Review and perspective of high-k dielectrics on silicon." Journal of Telecommunications and Information Technology, no. 2 (June 25, 2023): 33–43. http://dx.doi.org/10.26636/jtit.2007.2.806.

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The paper reviews recent work in the area of high-k dielectrics for application as the gate oxide in advanced MOSFETs. Following a review of relevant dielectric physics, we discuss challenges and issues relating to characterization of the dielectrics, which are compounded by electron trapping phenomena in the microsecond regime. Nearly all practical methods of preparation result in a thin interfacial layer generally of the form SiOx or a mixed oxide between Si and the high-k so that the extraction of the dielectric constant is complicated and values must be qualified by error analysis. The dis

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6

Dąbrowski, Jaroslaw, Seiichi Miyazaki, S. Inumiya, et al. "The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics." Materials Science Forum 608 (December 2008): 55–109. http://dx.doi.org/10.4028/www.scientific.net/msf.608.55.

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Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents

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7

Shukla, Prabhat, and Swapnali Makdey. "Simulation of Silicon Nanowire Field Effect Transistor for Different High k Dielectric Material." International Journal of Scientific Engineering and Research 5, no. 2 (2017): 10–12. https://doi.org/10.70729/ijser151218.

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8

Shimoga, Ganesh, and Sang-Youn Kim. "High-k Polymer Nanocomposite Materials for Technological Applications." Applied Sciences 10, no. 12 (2020): 4249. http://dx.doi.org/10.3390/app10124249.

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Understanding the properties of small molecules or monomers is decidedly important. The efforts of synthetic chemists and material engineers must be appreciated because of their knowledge of how utilize the properties of synthetic fragments in constructing long-chain macromolecules. Scientists active in this area of macromolecular science have shared their knowledge of catalysts, monomers and a variety of designed nanoparticles in synthetic techniques that create all sorts of nanocomposite polymer stuffs. Such materials are now an integral part of the contemporary world. Polymer nanocomposites

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9

Misra, Durga. "Advancing Science and Technology of High-k Dielectric at ECS." ECS Meeting Abstracts MA2022-01, no. 18 (2022): 1039. http://dx.doi.org/10.1149/ma2022-01181039mtgabs.

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Historically SiO2 was the main driver as the transistor gate dielectric in CMOS technology. Once the thickness of SiO2 reached the onset of direct tunneling region (<1.5 nm) HfO2 -based high-k insulators were introduced to suppress the direct-tunneling leakage current. ECS started a symposium on Physics and Technology of High-k Gate Dielectrics in 2002 describing the evolution of dielectric science in nanoelectronics. In recent years transistor has transformed from a planar device to a three-dimensional device to a gate all around device. The electrical performance in these devices depends

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10

SU, WEITAO, QIUHUI ZHUANG, DEXUAN HUO, and BIN LI. "DIELECTRIC AND INTERFACE STABILITY OF LaSmO3 FILMS." Surface Review and Letters 19, no. 06 (2012): 1250064. http://dx.doi.org/10.1142/s0218625x12500643.

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The continuous downscaling of metal oxide semiconductor field effect transistors (MOSFET) on silicon, germanium, GaAs , etc. still demands the creation of new high-k dielectrics with even better material performance. In this research, a new ternary high-k dielectric film, LaSmO3 , is deposited using electron-beam evaporation. The structure and high temperature interfacial thermal stabilities are investigated by X-ray diffraction (XRD), X-ray photon electronic spectra (XPS), infrared attenuated total reflection (ATR) and time of flight second ion mass spectroscopy (ToF-SIMS). The band gap and b

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11

Muhamad, Amri Ismail, Mazwan Mohd Zaini Khairil, and Ismahadi Syono Mohd. "Graphene field-effect transistor simulation with TCAD on top-gate dielectric influences." TELKOMNIKA Telecommunication, Computing, Electronics and Control 17, no. 4 (2019): 1845–52. https://doi.org/10.12928/TELKOMNIKA.v17i4.12760.

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This paper presents the influence of top-gate dielectric material for graphene field-effect transistor (GFET) using TCAD simulation. Apart from silicon-based dielectric that is typically used for top-gate structure, other high-dielectric constant (high-k) dielectric materials namely aluminum oxide and hafnium oxide are also involved in the analysis deliberately to improve the electrical properties of the GFET. The unique GFET current-voltage characteristics against several top-gate dielectric thicknesses are also investigated to guide the wafer fabrication engineers during the process optimiza

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12

Modes, Christina, Stefan Malkmus, and Frieder Gora. "High K Low Loss Dielectrics Co-Fireable with LTCC." Active and Passive Electronic Components 25, no. 2 (2002): 141–45. http://dx.doi.org/10.1080/08827510212346.

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Rapid growth in the application of LTCC technology for RF wireless is clearly driven by the trend of miniaturization and mobile communication systems. This technology provides the possibility of integration of passive components in a cost effective way. Heraeus has implemented compatible high permitivity and low loss dielectrics with NPO performance into modified Heraeus CT700 low temperature co-fired ceramic tape system. The majority of commercially available microwave dielectrics show increasing firing temperatures>200 °Cwhich make them incompatible with Ag metallizations or show high die

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13

Ameer, F. Roslan, Salehuddin F., S. M. Zain A., E. Kaharudin K., and Ahmad I. "Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material." Indonesian Journal of Electrical Engineering and Computer Science (IJEECS) 18, no. 2 (2020): 724–30. https://doi.org/10.11591/ijeecs.v18.i2.pp724-730.

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In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized

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14

Vimala, Palanichamy, and N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer." Journal of Nano Research 56 (February 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.

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In this paper, a comparative analysis of the Tri-gate MOSFET device structure with respect to Single Material Gate (SMG) Tri-gate MOSFET, Double Material Gate (DMG) Tri-gate MOSFET and Triple Material Gate (TMG) Tri-gate MOSFET with & without Hafnium dioxide as high-K dielectric material is employed using Silvaco TCAD Atlas Tool. It shows a compact model and better DC, AC performance for triple material gate structures and yields a high drive current of the device for TMG Tri-gate MOSFET with high-k dielectrics and shows a better electrical characteristics in comparison with other device s

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15

Sreenivasa Rao, Devireddy, Malluri Sirisha, Deepthi Tumkur Srinivas Murthy, Nayana Dunthur Krishne Gowda, Bukya Balaji, and Padakanti Kiran Kumar. "Design and optimization of high electron mobility transistor with high-k dielectric material integration." International Journal of Electrical and Computer Engineering (IJECE) 14, no. 4 (2024): 3855. http://dx.doi.org/10.11591/ijece.v14i4.pp3855-3862.

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We have developed and simulated a high electron mobility transistor (HEMT) operating in the 5 nm regime. This HEMT uses hafnium oxide (HfO2), a high-k dielectric material, to create an undoped region (UR) beneath the gate. While the gate and undoped regions share equal thickness, the channel length differs. This innovative undoped under the gate dielectric HEMT design mitigates the maximum electric field (V) within the channel area, leading to a significant increase in drain current. The utilization of a high-k dielectric in the HEMT structure results in a saturated Ion current that is 60% hig

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16

Sreenivasa, Rao Devireddy, Malluri Sirisha, Srinivas Murthy Deepthi Tumkur, Krishne Gowda Nayana Dunthur, Bukya Balaji, and Kumar Padakanti Kiran. "Design and optimization of high electron mobility transistor with high-k dielectric material integration." Design and optimization of high electron mobility transistor with high-k dielectric material integration 14, no. 4 (2024): 3855–62. https://doi.org/10.11591/ijece.v14i4.pp3855-3862.

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We have developed and simulated a high electron mobility transistor (HEMT) operating in the 5 nm regime. This HEMT uses hafnium oxide (HfO2), a high-k dielectric material, to create an undoped region (UR) beneath the gate. While the gate and undoped regions share equal thickness, the channel length differs. This innovative undoped under the gate dielectric HEMT design mitigates the maximum electric field (V) within the channel area, leading to a significant increase in drain current. The utilization of a high-k dielectric in the HEMT structure results in a sa

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17

Kumar, Rajesh, and Rajesh Mehra. "Impact Analysis of DGMOSFET using High-k Dielectric material." International Journal of Engineering Trends and Technology 34, no. 4 (2016): 179–83. http://dx.doi.org/10.14445/22315381/ijett-v34p237.

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18

Lin, Yu-Hsien, and Jay-Chi Chou. "Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials." Journal of Nanomaterials 2015 (2015): 1–6. http://dx.doi.org/10.1155/2015/782786.

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We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using different high-k gate dielectric materials such as silicon nitride (Si3N4) and aluminum oxide (Al2O3) at low temperature process (<300°C) and compared them with low temperature silicon dioxide (SiO2). The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process

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19

Cava, R. J., J. J. Krajewski, Y. L. Qin, and H. W. Zandbergen. "Bismuth titanium indium antimony oxide: A low-temperature-coefficient, high-K dielectric material." Journal of Materials Research 15, no. 12 (2000): 2672–76. http://dx.doi.org/10.1557/jmr.2000.0384.

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The 1 MHz dielectric properties for mixed-phase polycrystalline ceramics in the system Bi4Ti3O12–Bi(InxSb1x)O3 were reported. In the vicinity of ambient temperature, the dielectric constants for the Sb and In end-members were approximately 430 and 160, respectively, and the temperature coefficients of dielectric constant (TCKs) were approximately -7600 and +430 ppm/deg. At an overall composition of Bi4Ti3O12:Bi(In0.37Sb0.63)O3 a dielectric constant of 144 and a low TCK were found. Powder x-ray diffraction and electron microscopy analyses indicated that the optimal composition contained three m

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20

De Gendt, Stefan. "(Dielectric Science & Technology Thomas Callinan Award) Materials and Processes As Enablers for Moore Moore and Beyond Moore Technologies." ECS Meeting Abstracts MA2022-01, no. 18 (2022): 1036. http://dx.doi.org/10.1149/ma2022-01181036mtgabs.

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In this presentation, an overview will be presented of historic and recent developments achieved w.r.t. materials and processes that enabled continued performance scaling of CMOS and beyond CMOS applications. Starting from early high-k work. For decades, thermal oxidation of crystalline Silicon into SiO2 has been the gate oxide material in CMOS technology. Miniaturization for performance improvement, required the gate dielectric to decrease in thickness to support the required increase in capacitance (per unit area) and drive current (per device width). Early 2000, the thickness scaled below 1

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21

Gowthami, Y., B.Balaji, and K. Srinivasa Rao. "Qualitative Analysis & Advancement of Asymmetric Recessed Gates with Dual Floating Material GaN HEMT for Quantum Electronics." Journal of Integrated Circuits and Systems 18, no. 1 (2023): 1–8. http://dx.doi.org/10.29292/jics.v18i1.657.

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The Impact of Aluminium nitride (AlN) Spacer, Gallium Nitride (GaN) Cap Layer, Front Pi Gate (FG) and Back Pi Gate(BG), High K dielectric material such as Hafnium dioxide(HfO2), Aluminium Oxide (Al2O3), Silicon nitride (Si3N4) on Aluminium Galium Nitride/ Gallium Nitride (AlGaN/GaN), Heterojunction High Electron Mobility Transistor (HEMT) of 6nm(nanometer) technology is simulated and extracted the results using the Silvaco Atlas TCAD tool. The importance of High K dielectric materials like Al2O3 and Si3N4 are studied for the proposal of GaN HEMT. AlN, GaN Cap Layers, and High K Dielectric mate

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22

Zhang, Jiacheng, Zi Wang, Guoqing Jiang, Huachao Wei, Zongxi Zhang, and Junwen Ren. "Enhanced Thermal Conductivity and Dielectric Properties of Epoxy Composites with Fluorinated Graphene Nanofillers." Nanomaterials 13, no. 16 (2023): 2322. http://dx.doi.org/10.3390/nano13162322.

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The demand for high-performance dielectrics has increased due to the rapid development of modern electric power and electronic technology. Composite dielectrics, which can overcome the limitations of traditional single polymers in thermal conductivity, dielectric properties and mechanical performance, have received considerable attention. In this study, we report a multifunctional nanocomposite material fabricated by blending fluorinated graphene (F-graphene) with epoxy resin. The F-graphene/epoxy composite exhibited a high thermal conductivity of 0.3304 W·m−1·K−1 at a low filler loading of 1.

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23

Li, Rui, Jian Zhong Pei, Yan Wei Li, Xin Shi, and Qun Le Du. "Preparation, Morphology and Dielectric Properties of Polyamide-6/Poly(Vinylidene Fluoride) Blends." Advanced Materials Research 496 (March 2012): 263–67. http://dx.doi.org/10.4028/www.scientific.net/amr.496.263.

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A novel all-polymeric material with high dielectric constant (k) has been developed by blending poly (vinylidene fluoride) (PVDF) with polyamide-6 (PA6). The dependence of the dielectric properties on frequency and polymer volume fraction was investigated. When the volume fraction of PA6 is 20%, the dielectric property is better than others. The SEM investigations suggest that the enhanced dielectric behavior originates from significant interfacial interactions of polymer-polymer. The XRD demonstrate that the PA6 and PVDF affect the crystalline behavior of each component. Furthermore, the stab

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24

F. Roslan, Ameer, F. Salehuddin, A. S. M. Zain, K. E. Kaharudin, and I. Ahmad. "Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material." Indonesian Journal of Electrical Engineering and Computer Science 18, no. 2 (2020): 724. http://dx.doi.org/10.11591/ijeecs.v18.i2.pp724-730.

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<p><span>In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device charact

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25

Abdul Hamid, Nur Farahin, Rozana A. M. Osman, Mohd Sobri Idris, and Mohd Rosydi Zakaria. "Review on Preparation and Properties of High-K Dielectric Material Based on Lanthanum Doped Barium Titanate." Materials Science Forum 819 (June 2015): 173–78. http://dx.doi.org/10.4028/www.scientific.net/msf.819.173.

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Lanthanum doped barium titanate (BaTiO3) were studied for high-K dielectric and exhibit a relaxor ferroelectric properties and it can be prepared by using various method. Relaxor ferroelectric offers a wide temperature and frequency range of application for materials with high dielectric constant for microelectronic application. This paper reviews the preparation methods, the important features, advantages and limitation for the lanthanum doped barium titanate. Thus, the phase purity and mixture selected also been review on the second part of the article. The article concludes with a brief dis

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26

Xu, Toby, Coskun Tekes, and F. Degertekin. "CMUTs with high-K atomic layer deposition dielectric material insulation layer." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 61, no. 12 (2014): 2121–31. http://dx.doi.org/10.1109/tuffc.2014.006481.

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Phani, A. R., D. Di Claudio, M. Passacantando, and S. Santucci. "GeO2 based high k dielectric material synthesized by sol–gel process." Journal of Non-Crystalline Solids 353, no. 5-7 (2007): 692–96. http://dx.doi.org/10.1016/j.jnoncrysol.2006.10.040.

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Bikshalu, K., V. S. K. Reddy, P. C. S. Reddy, and K. V. Rao. "High-performance Carbon Nanotube Field Effect Transistors with High k Dielectric Gate Material." Materials Today: Proceedings 2, no. 9 (2015): 4457–62. http://dx.doi.org/10.1016/j.matpr.2015.10.048.

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Hakkee, Jung, and Kim Byungon. "Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 5 (2021): 3882–89. https://doi.org/10.11591/ijece.v11i5.pp3882-3889.

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The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO 2 /highk dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second deriva

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Gupta, Prateek, Dr Avnish Kumar Upadhyay, Dr Chandan Kumar Jha, Anuj Gupta, and Lakshay Gupta. "Performance Analysis and Comparison of Different High-K Materials Used as Gate Dielectrics in DH-TMSG MOSFET." International Journal for Research in Applied Science and Engineering Technology 10, no. 12 (2022): 1870–89. http://dx.doi.org/10.22214/ijraset.2022.48089.

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Abstract: To overcome SCEs and provide better packing density and performance a device called Double Halo Triple Material Surround Gate MOSFET is introduced. The device is designed by the combination of gate engineering and channel engineering. The device uses a surround gate MOSFET with triple material gate employing gate material engineering which improves the gate transport efficiency by modifying electric field pattern and surface potential along channel, resulting in higher carrier transport efficiency and SCEs. To extend the use of CMOS technology beyond 14 nm node technology, new device

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Rathee, Kanta, Mukesh Kumar, and B. P. Malik. "The Structural and Electrical Properties of Ta₂O₅ Thin Films Prepared by DC Sputtering Method." Key Engineering Materials 500 (January 2012): 317–21. http://dx.doi.org/10.4028/www.scientific.net/kem.500.317.

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Recently both, electrical and material properties of tantalum oxide (Ta2O5) have been found to be useful for microelectronics and optoelectronics devices. The need of higher permittivity of dielectric material attracts more attention towards the tantalum oxide thin films. To ensure good electrical performance of the resulting device DC sputtering technique has been used for depositing Ta2O5 films. In the present work, the potential of Ta2O5 thin films as a high K dielectric for CMOS devices has been studied. Physical characteristics of the Ta2O5 dielectrics were investigated with x-ray diffrac

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Kou, Yujia, Wenying Zhou, Li Xu, et al. "Surface modification of GO by PDA for dielectric material with well-suppressed dielectric loss." High Performance Polymers 31, no. 9-10 (2019): 1183–94. http://dx.doi.org/10.1177/0954008319837744.

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To suppress the high dielectric loss of graphene oxide (GO)/poly(vinylidene fluoride) (PVDF) while maintaining high dielectric constant (high- k) near the percolation threshold, in this study, GO nanosheets coated with polydopamine (PDA) were integrated into PVDF to investigate the effects of the PDA shell and its concentrations on the dielectric properties of the nanocomposites. The results indicate that the dissipation factor and conductivity of the GO@PDA/PVDF are significantly suppressed to very low values compared with the pristine GO/PVDF composites, attributable to the PDA interlayer be

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Okamoto, Daichi, Yoko Shibasaki, Daisuke Shibata, and Tadahiko Hanada. "New Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and High Reliability." International Symposium on Microelectronics 2018, no. 1 (2018): 000466–69. http://dx.doi.org/10.4071/2380-4505-2018.1.000466.

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Abstract This paper presents an advanced ultra-thin photosensitive dielectric Film (PDM) newly developed with high resolution, low CTE and low residual stress for next-generation high-density redistribution layer (RDL), 2.5D interposer, and high-density fan-out package applications. For high-density RDL, photosensitive dielectric materials need to have low CTE to achieve high package reliability. The CTE of the material is 30–35ppm/K. While maintaining the low CTE, we successfully demonstrated the minimum micro-via diameter of 3um in the 5um thickness. Curing temperature of the PDM is 180°C ×

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Liu, Chong, and Xiao Li Fan. "Methods to Improve Properties of Gate Dielectrics in Metal-Oxide-Semiconductor." Advanced Materials Research 463-464 (February 2012): 1341–45. http://dx.doi.org/10.4028/www.scientific.net/amr.463-464.1341.

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This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we

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Baivier, Clara, Imen Hammami, Ratiba Benzerga, Manuel P. F. Graça, and Luís C. Costa. "Barium Titanate/Gadolinium Ferrite: A New Material Composite to Store Energy." Nanomaterials 13, no. 13 (2023): 1955. http://dx.doi.org/10.3390/nano13131955.

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This work investigates the dielectric properties of barium titanate/gadolinium ferrite ceramic composites, with different concentrations of each material. Our objective was to increase the storage ability of this material, finding a compromise between high permittivity and low dielectric losses. A two-step sintering procedure was used in the preparation of the composites to attain the desired results. Their morphological, structural and electrical properties were tested using scanning electron microscopy, X-Ray powder diffraction and impedance spectroscopy, respectively. Dielectric characteriz

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Fanciulli, Marco, Michele Perego, Caroline Bonafos, A. Mouti, S. Schamm, and G. Benassayag. "Nanocrystals in High-k Dielectric Stacks for Non-Volatile Memory Applications." Advances in Science and Technology 51 (October 2006): 156–66. http://dx.doi.org/10.4028/www.scientific.net/ast.51.156.

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The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tu

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Varsamis, Christos-Platon E. "Determination of the Complex Refractive Index of Materials via Infrared Measurements." Applied Spectroscopy 56, no. 8 (2002): 1107–13. http://dx.doi.org/10.1366/000370202760249873.

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In this work, methods are presented for obtaining the real, n, and imaginary, k, parts of the complex refractive index of materials considered as semi-infinite and finite from infrared reflectance, R( ν), and/or transmittance, T( ν), spectra. In semi-infinite samples, with negligible T( ν), only R( ν) is measured, and n and k can derive from the Kramers–Kronig (K–K) transformation or the modeling of the dielectric function of the material. In finite samples, the interference fringes due to multiple internal reflections can significantly alter the measured spectra. It was demonstrated that when

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Jacob, Reenu, and Jayakumari Isac. "Dielectric Response and Transport Properties of Pb2Sr2CaCu2O9 [Lead Strontium Calcium Copper Oxide]." Reports in Advances of Physical Sciences 01, no. 02 (2017): 1750003. http://dx.doi.org/10.1142/s2424942417500037.

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High dielectric permittivity, good mechanical properties and excellent thermal stability are highly desired qualities for the dielectric materials used in embedded capacitors and energy-storage devices. This study reports the temperature dependence and very low loss factor of Pb2Sr2CaCu2O9 ceramics. X-ray diffraction (XRD) and scanning electron microscope (SEM) are used to analyze the sample. The dielectric properties of the material prepared has been investigated in the frequency range 42–1[Formula: see text]MHz and in the temperature range 303–873[Formula: see text]K. The result reveals that

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Mukherjee, Mainak, Niloy Ghosh, Papiya Debnath, A. Sarkar, and MANASH CHANDA. "Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications." Journal of Integrated Circuits and Systems 19, no. 1 (2024): 1–7. http://dx.doi.org/10.29292/jics.v19i1.796.

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In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by incr

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Driss Bouguenna, Abbès Beloufa, Khaled Hebali, and Sajad Ahmad Loan. "Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator." International Journal of Nanoelectronics and Materials (IJNeaM) 16, no. 3 (2024): 607–20. http://dx.doi.org/10.58915/ijneam.v16i3.1325.

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This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other

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Shearer, Alexander, Jung-Soo Ko, Krishna C. Saraswat, Eric Pop, and Stacey F. Bent. "The Impact of ALD Precursor Choice on Nucleation and Growth of Dielectrics on 2D Materials." ECS Meeting Abstracts MA2024-01, no. 12 (2024): 999. http://dx.doi.org/10.1149/ma2024-0112999mtgabs.

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Recently, atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) have received significant attention due to their unique optical and electrical properties, lending themselves to exciting applications such as microelectronics, sensing, catalysis, photonics, and more. The properties of TMDs can be acutely impacted by their environment due to their atomic thinness. For instance, in a TMD-based transistor with a high-k dielectric surrounding the TMD semiconductor, the dielectric could dope the channel via charge transfer; it can improve charge carrier mobility by screening th

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Kanagathara, N., S. Sankar, L. Saravanan, V. Natarajan, and S. Elangovan. "Dielectric and Impedance Spectroscopic Investigation of (3-Nitrophenol) -2,4,6-Triamino-1,3,5- Triazine: An Organic Crystalline Material." Advances in Condensed Matter Physics 2022 (September 5, 2022): 1–8. http://dx.doi.org/10.1155/2022/6002025.

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This article presents the investigation of dielectric and impedance spectroscopic properties of an organic product of 3-nitrophenol -2,4,6-tri amino-1,3,5- triazine (3NPTAT) single crystal, synthesized from melamine and m-nitrophenol. Comprehensive dielectric studies and charge transportation properties of the grown 3NPTAT crystal are given. The dielectric characteristics of the specimen were carried out in the frequency range of 50 Hz and 5 MHz at different temperatures, namely, 313 K, 333 K, 353 K, and 373 K. From the spectra, it was observed that the slowdown occurs at low temperatures, and

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Jiang, J., O. O. Awadelkarim, D. O. Lee, P. Roman, and J. Ruzyllo. "On the capacitance of metal/high-k dielectric material stack/silicon structures." Solid-State Electronics 46, no. 11 (2002): 1991–95. http://dx.doi.org/10.1016/s0038-1101(02)00167-3.

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Duguey, Sonia, Richard Lebourgeois, and Jean Marc Heintz. "Sintering of High K LTCC Compatible Dielectrics." Materials Science Forum 534-536 (January 2007): 1501–4. http://dx.doi.org/10.4028/www.scientific.net/msf.534-536.1501.

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This study deals with the co-sintering of copper oxide added ANT with alumina tapes and silver ink. AgNb1/2Ta1/2O3 (refered ANT 22) was synthesized using niobium oxide with fine and large grain size to examine the effect of the granulometry on the tape casting. The resulting multilayers were co-fired between 850 and 900°C. Phase identification was investigated by XRD. Energy Dispersive Spectroscopy was performed to study the interdiffusion between the layers. Permittivity and dielectric losses were measured at 50 kHz for both tape cast samples and bullk material. No interdiffusion was observed

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Saha, Priyanka, Rudra Sankar Dhar, Swagat Nanda, Kuleen Kumar, and Moath Alathbah. "The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length." Nanomaterials 13, no. 23 (2023): 3008. http://dx.doi.org/10.3390/nano13233008.

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The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold curre

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Lu, Jiadong, Songli Zhang, Leizhi Zhang, Chenxi Wang, and Chunying Min. "Preparation and Properties of Hollow Glass Microspheres/Dicyclopentadiene Phenol Epoxy Resin Composite Materials." Materials 16, no. 10 (2023): 3768. http://dx.doi.org/10.3390/ma16103768.

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With the development of the integrated circuit and chip industry, electronic products and their components are becoming increasingly miniaturized, high-frequency, and low-loss. These demand higher requirements for the dielectric properties and other aspects of epoxy resins to develop a novel epoxy resin system that meets the needs of current development. This paper employs ethyl phenylacetate cured dicyclopentadiene phenol (DCPD) epoxy resin as the matrix and incorporates KH550 coupling-agent-treated SiO2 hollow glass microspheres to produce composite materials with low dielectric, high heat r

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Usman, Muhammad, Cheng-Hua Lee, Dung-Shing Hung, et al. "Intrinsic low dielectric behaviour of a highly thermally stable Sr-based metal–organic framework for interlayer dielectric materials." J. Mater. Chem. C 2, no. 19 (2014): 3762–68. http://dx.doi.org/10.1039/c4tc00149d.

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A Sr-based metal–organic framework exhibits an intrinsic low dielectric constant after removing the water molecules. A low dielectric constant and high thermal stability make this compound a candidate for use as a low-k material.

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48

CAYMAX, M., S. DE GENDT, W. VANDERVORST, et al. "ISSUES, ACHIEVEMENTS AND CHALLENGES TOWARDS INTEGRATION OF HIGH-k DIELECTRICS." International Journal of High Speed Electronics and Systems 12, no. 02 (2002): 295–304. http://dx.doi.org/10.1142/s0129156402001253.

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Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al 2 O 3, ZrO 2 and HfO 2 as well as their mixtures. Very promising results have been reported world-wide. Here, however, we show that there are a number of issues related to materials and electrical characteristics as well as to processing which are not always recognized and that necessitate more work to find solutions. Among these are problems with density

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Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was ob

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50

Hakkee, Jung. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 240–48. https://doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was ob

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