Dissertations / Theses on the topic 'High-k material'
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Chen, B. P. T. "Deposition and material characterisation of alternative high-K gate oxides." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.597522.
Full textWang, Jiahui. "High-K Material Based Leaky-wave Antenna Design, Implementation, and Manufacture." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1347582062.
Full textLi, Wenmei. "CHARACTERIZATION OF HIGH-K GATE STACKS IN METAL-OXIDE-SEMICONDUCTOR CAPACITORS." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20010202-100109.
Full textThe purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-k dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterization methodologies were established to evaluate high-k dielectrics at various processing levels, which, in part, determine the final characteristics of an advanced gate-stack device. Material systems that were investigated include: Al-O, Hf-Si-O, Zr-Si-O, Ti-O, Ta-O and Sr-Ti-O. Various physical and electrical characterization techniques were used to establish fundamental understandings of the materials selected, thin-film growth/deposition processes, and gate-stack structures. General conclusions for stable and unstable gate-dielectric materials have been establishedregarding the presence of a problematic interfacial layer at the Si/dielectric interface, graded dielectric layers, and the stability of gate electrodes on high-k dielectrics.The nanometer-scale chemistry of a gate-stack capacitor whose expected structure is Si/SiOxNy/Ta2O5/TiN/Al was studied by high-resolution electron-energy-loss spectroscopy in a scanning transmission electron microscope. Elemental profiles with near-atomic-level resolution for Si, Ti, N, Al, and O demonstrate that the device structure deviates drastically from the expectation and is chemically complex.It is concluded that the graded distribution of certain elements across the gate-stack capacitor completely precludes a band-structure model that assumes abrupt interfaces and chemically discrete layers. This study impacted on subsequent interpretations of flatband voltage extractions and electrical degradation following backside metallization/postmetallization annealing for capacitors whose dielectric-stack was based on Ta-O.Detailed and extensive electrical characterizations of Pt/SiOx/Sr-Ti-O/Si MOS capacitors were carried out to investigate reliability issues in a bi-layer gate dielectric. Based on these studies, models are proposed to describe the carrier transport and dielectric degradation for a Sr-Ti-O capacitor. It is concluded that conduction is dominated by Frenkel-Poole emission from mid-gap trap levels. The trap barrier height is estimated to be 1.51eV. A model based on the atomic and electronic structure of oxygen vacancies can account for the reported leakage-current characteristics. In addition, it is tentatively proposed that anode-hole injection and hole trapping control the dielectric degradation under gate injection.
Xu, Toby Ge. "Material and array design for CMUT based volumetric intravascular and intracardiac ultrasound imaging." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54861.
Full textGuerrero, Enriquez Rubén Dario. "Etude des filtres miniatures LTCC High K en bandes L&S." Thesis, Brest, 2016. http://www.theses.fr/2016BRES0036/document.
Full textIn current communication systems, whether terrestrial or spatial, whether fixed or mobile, there is a real interest in developing high performance miniature RF front-ends. This is applied in particular to filter devices, in which the size and the quality factors are clearly in conflict. For low frequency bands around the GHz, the wavelengths remain significant, making it difficult the miniaturization efforts. On the other hand, we must also ensure that these filters will be easily interconnected with other other system components, including active devices.For all these reasons, the development of multilayer filter structures using high permittivity substrates (Er = 68) in an LTCC approach is consolidated as an interesting alternative. It may lead to a significant footprint reduction without decreasing the electrical performances.As part of this work, two multilayer filter structures have been developed to meet the given specifications in L and S bands, given by a space manufacturer. These filters have as main features a high rejection level and low losses in the passband. To meet the specifications, a vertically stacked SIW filter and a short-circuited stubs filter in a stripline configuration were studied. The SIW filter is characterized by a high quality factor, which results in low insertion loss and good flatness. The stubs filter allows in contrast to reduce the footprint but at the price of impacting the electrical performance. In both cases we take advantage of the flexibility offered by the LTCC technology as it finally provides an additional freedom degree compared to a conventional planar approach. For the SIW filter, the topological architecture was studied and designed in detail, to be able to arrange and synthetize couplings between twelve cavities. In a similar way, for the stub filter a synthesis that takes profit of all the offered freedom degrees was developed.Given the filters complexity, especially due to the high order and the implementation of “electrical walls" based on specific vias patterns, a close attention must be paid during the simulation and optimization phase. In addition, the high permittivity substrate does not allow to conceive 50-Ohms lines. Finally, access transitions constitute a challenging task, especially for the SIW case.This thesis was co-funded by CNES (Centre National d'Etudes Spatiales) and Thales Alenia Space, and was accompanied by an R&T project funded by CNES. The German foundry Via Electronic was responsible for the filters fabrication
Tewg, Jun-Yen. "Zirconium-doped tantalum oxide high-k gate dielectric films." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1346.
Full textHan, Lei. "Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices." UKnowledge, 2015. http://uknowledge.uky.edu/ece_etds/69.
Full textGenevès, Thomas. "Elaboration et caractérisation de couches ultra-minces de silicate de baryum en tant qu'oxyde de grille alternatif." Phd thesis, Université de Bourgogne, 2008. http://tel.archives-ouvertes.fr/tel-00359449.
Full textSun, Xiao. "Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors." Thesis, Yale University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3578458.
Full textAs the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology.
In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT).
By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed.
The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.
Mutas, Sergej [Verfasser]. "Analysis of high-k materials with Local Electrode Atom Probe / Sergej Mutas." Aachen : Shaker, 2012. http://d-nb.info/1066198276/34.
Full textLontsi, Fomena Mireille. "Etude théorique de la diffusion de l'oxygène dans des oxydes diélectriques$bRessource électronique." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2008. http://tel.archives-ouvertes.fr/tel-00402631.
Full textKirsch, Paul Daniel. "Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3034557.
Full textMudanai, Sivakumar Panneerselvam. "Gate current modeling through high-k materials and compact modeling of gate capacitance." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3038191.
Full textCheng, Cheng-Wei Ph D. Massachusetts Institute of Technology. "In-situ deposition of high-k dielectrics on III-V compound semiconductor in MOCVD system." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/59216.
Full textIncludes bibliographical references (p. 164-168).
In situ deposition of high-k materials to passivate the GaAs in metal organic chemical vapor deposition (MOCVD) system was well demonstrated. Both atomic layer deposition (ALD) and chemical vapor deposition (CVD) methods were applied in this research. The CVD aluminum nitride (AIN) was first selected to be in situ deposited on GaAs surface by using trimethlyaluminum(TMA) and dimethylhydrazine (DMHy). However, the frequency dispersion of Capacitance-Voltage (C-V) curves for in situ AIN/GaAs samples are always large because of the existence of high interfacial defect state density (Dit) due to the nitridization of the GaAs surface during the AIN deposition. In order to avoid the surface reaction, in situ ALD of aluminum oxide (A1₂O₃) on GaAs in MOCVD system was proposed. Isopropanol (IPA) was chosen as the oxygen source for A1₂O₃ ALD and the mechanism was investigated. Pure A120 3 thin film was obtained and no arsenic or gallium oxide was observed at the interface. Both frequency dispersion of C-V curve and the Di, of oxide/p-GaAs interface are low for this process. In situ CVD A1₂O₃ on GaAs was also performed. Gallium oxide (Ga₂O₃) was observed at the interface. The Ga₂O₃ was enriched in the A1₂O₃ above the interface during the deposition process and a possible mechanism was proposed. This layer reduces the frequency dispersion of the C-V characteristics and lowers the Dit of n-type GaAs sample. After the in situ method had been successfully established, ex situ experiments was also performed to compare the results with in situ process in the same MOCVD system. Annealing native oxide covered GaAs samples in Arsine (AsH 3) prior to ALD A1₂O₃ results in C-V characteristics of the treated samples that resemble the superior C-V characteristics of p-type GaAs. Besides, both TMA and IPA show self-cleaning effect on removing the native oxide in ex situ process. The discrepancy in the C-V characteristics was observed in in situ p- and n-type GaAs samples. Finally, the entire Dit energy distributions of interfaces from different processes were determined by conductance frequency method with temperature-variation C-V measurement. The existence of Ga₂O₃ at interface was found to be the possible source to lower the density of mid-gap defect state. From the C-V simulation, the mid-gap defect states are acceptor-like (Gallium Vacancies) and the source to cause high frequency dispersion of the C-V curves for n-type substrate. The relation between the interfacial defect state distribution and the processes was correlated.
by Cheng-Wei Cheng.
Ph.D.
Li, Haoxiang. "Angle-Resolved Photoemission Spectroscopy Study of High Temperature Superconductor Cuprate, and Potential High Temperature Superconductors K-Doped p-Terphenyl and Trilayer Nickelate." Thesis, University of Colorado at Boulder, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10642070.
Full textThe macroscopic quantum phenomenology of superconductivity has attracted broad interest from both scientific research and applications. Many exotic physics found in the first high $T_C$ superconductor family cuprate remain unsolved even after 30 years of intense study. Angle-Resolved Photoemission Spectroscopy (ARPES) provides the direct probe to the major information of the electronic interactions, which plays the key role in these exotic physics including high $T_C$ superconductivity. ARPES is also the best tool to study the electronic structure in materials that potentially hold high $T_C$ superconductivity, providing insight for materials research and design. In this thesis, we present the ARPES study of the cuprate high $T_C$ superconductor Pb doped Bi$_2$Sr$_2$CaCu$_2$O$_{8+\delta}$, and potential high $T_C$ superconductors K doped \textit{p}-terphenyl, and trilayer nickelate La$_4$Ni$_3$O$_{10}$. For Pb doped Bi2212, our study focuses on the key part of the electronic interactions---the self-energies. With the development of a novel 2-dimensional analysis technique, we present the first quantitative extraction of the fully causal complex self-energies. The extracted information reveals a conversion of the diffusive strange-metal correlations into a coherent highly renormalized state at low temperature followed by the enhancement of the number of states for pairing. We then further show how this can lead to a strong positive feedback effect that can stabilize and strengthen superconducting pairing. In K doped \textit{p}-terphenyl, we discover low energy spectral gaps that persist up to 120 K, consistent with potential Meissner effect signal from previous studies. Among a few potential origins for these gaps, we argue that the electron pairing scenario is most likely. For La$_4$Ni$_3$O$_{10}$, we present the Fermiology and electron dynamics of this material, and they show certain similarities to the cuprate electronic structure, as well as a few unique features.
Gao, Yong. "Deposition, stabilization and characterization of zirconium oxide and hafnium oxide thin films for high k gate dielectrics." Diss., The University of Arizona, 2004. http://hdl.handle.net/10150/290136.
Full textReddy, Raj. "A study of high-K dielectric materials in conjunction with a multilayer thick-film system." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43280.
Full textMaster of Science
Vieluf, Maik. "Hochauflösende Rutherford-Streuspektrometrie zur Untersuchung von ZrO2-Schichtwachstum im Anfangsstadium." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2010. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-38113.
Full textThis thesis originated from a cooperation between Research Center Dresden-Rossendorf and Qimonda Dresden GmbH & Co. OHG. By means of High Resolution Rutherford Backscattering Spectrometry (HR-RBS) the diffusion behaviour and layer growth of ZrO2 on SiO2 and TiN in the initial regime were investigated. The analysis of concentration profiles in ultrathin layers and interfaces was the focus of this work, made possible by the excellent depth resolution of less than 0.3 nm near the surface. For the first time a two-dimensional position sensitive semiconductor detector was implemented and characterized in the setup of the HR-RBS for the improvement of the quality of the measurement results. Furthermore, a measurement procedure was put into operation that allowed the reduction of ion induced damage. Through the optimization of the experimental conditions and the development of a program package for the support of the analyst, an efficient measurement procedure could be routinely ensured. At the time of a binary collision between the incident ion and the target element with a small impact factor, the charge state changes frequently, especially due to the abruptly decreasing ion velocity of the projectile and the overlapping of the electron clouds. For HR-RBS with an energy-separating dipole magnet, the charge state distribution of the scattered ions must be known for the interpretation of the measured spectra. For the first time a significant dependence of the charge state distribution of the scattered C ions on the layer thickness as well as atomic number of the detected target elements, here from the fourth subgroup, was emonstrated. This new knowledge allowed systematic investigations of the ZrO2 layer growth in the initial regime. The ZrO2 layers were produced by means of the atomic layer deposition (ALD). Based on the evidence for agglomeration of ZrO2 on SiO2 a method was introduced, which takes local thickness variations into account during the simulation of the HR-RBS spectra. An accurate statement about the ZrO2/SiO2 interface was possible due to the extraction of the thickness variation by the atomic force microscopy (AFM). The boundary surface is sharp except for a small intermediate ZrSiO4 layer and no diffusion of Zr atoms in SiO2 could be detected. A quite different behaviour could be derived from high resolution spectra for the growth of ZrO2 on TiN. Measurements of the surface topography of the TiN layer revealed non negligible values for the surface roughness. A program was developed to capture the influence of the surface roughness on the shape of the high resolution spectrum. This software uses AFM measurements to extract an energy distribution from calculated path length differences for ions scattered at the sample surface. Diffusion of Zr into polycrystalline TiN was demonstrated for the first time taking into account the effect of the surface roughness on the shape of the spectra. This observation indicates that already after the first ALD reaction cycle a small part of the deposited Zr atoms diffuses into the TiN layer up to a depth of 3 nm. Such preliminary results suggest grain boundary diffusion
Sreenivasan, Raghavasimhan. "Metal-gate/high-k dielectric stack engineering by atomic layer deposition : materials issues and electrical properties /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Full textGuiraud, Alexandre. "Intégration de matériaux à forte permittivité diélectrique dans les mémoires non volatile avancées." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4763/document.
Full textThe work of this thesis is on integration of high dielectric constant materials (High-k) as dielectric interpoly in Flash non volatile memories. The objective is to determine which High-k materials are suitable as interpoly dielectric in place of the ONO stack currently used. A range of High-k materials have been studied by electrical characterizations (I-V, C-V, breakdown statistics…) and physical characterizations (TEM, EDX, XPS…) in order to select those with the best properties for an interpoly dielectric. The difficulties in integration of High-k materials in a Flash memory process flow have been taken in account and solutions have been proposed
Tse, Koon-Yiu. "High-K gate oxides and metal gate materials for future complementary metal-oxide-semiconductor field-effect transistors." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611979.
Full textXia, Zhanbo. "Materials and Device Engineering for High Performance β-Ga2O3-based Electronics." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587688595358557.
Full textNiu, Gang. "Epitaxy of crystalline oxides for functional materials integration on silicon." Phd thesis, Ecole Centrale de Lyon, 2010. http://tel.archives-ouvertes.fr/tel-00601689.
Full textCARUSO, FRANCESCO. "Study of electrical conduction and defects in high-permittivity metal oxides: experiments and simulation." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/382298.
Full textOriginally investigated in the electronic manufacturing to replace the SiO2 insulating layer, metal oxides are now extensively used as insulating or active layers in a multitude of electronics devices. It is known that the electrical properties are strongly correlated to atomic defects, which generate localized electronic states inside the band gap that act as charge traps. Therefore, the understanding of the physical mechanisms and the role of defects governing the charge transport in metal oxide stacks is of utmost importance for the optimization of nano-electronic devices. However, the charge transport and role of defects in metal oxides is still under debate and a complete and self-consistent understanding over large thickness, temperature and voltage regimes is not reached. In this thesis I investigated the conduction mechanisms in metal-insulator-metal (MIM) capacitors incorporating three model materials Al2O3, HfO2 and Al-doped-HfO2 (AlHfO) deposited by atomic layer deposition (ALD), in three different thicknesses 5, 10, and 20 nm. Furthermore, Hf-based oxides deposited using either water or ozone as ALD oxygen source, as well as AlHfO at two Al concentrations (5% and 17%) were analyzed. The aim of this study is to identify the charge traps properties of each material and investigate the path that electrons take within metal oxide dielectrics under applied electric field. Moreover, the impact of different manufacturing processes and film thicknesses on the material properties is discussed. Traps properties are extracted from experimental current-voltage characteristics of MIM capacitors, over a broad temperature and voltage regime, using a comprehensive charge transport model implemented in the Ginestra® (Applied Materials, Inc.) simulation software. Defects in Al2O3 are characterized by a thermal ionization energy ET≈3.5 eV below the dielectric conduction band minimum (CBM) and a relaxation energy EREL≈1 eV, in agreement with the ab-initio calculations of oxygen vacancies reported in literature. Two kinds of defects are identified in each 10 and 20 nm-thick Hf-based oxide, characterized by ET≈1.8eV for "shallow" traps, and ET≈3eV for "deep" traps. The use of water as oxygen source during the oxide ALD introduces fixed positive charges in the oxide. The introduction of Al atoms in HfO2 increases the oxide energy band gap, without significantly impacting on the density and properties of defects. The analysis allowed to identify the location of traps most involved in the conduction and the dominant transport mechanism in 20 nm-thick oxides, at each applied electric field. Despite the different properties, in each material transient displacement currents occur at low electric fields, originating from electron trapping and emission at traps near the metal/oxide interface. The transport of electrons through the oxide occurs only at higher electric fields, in two different ways. If a large density of traps is energetically located near the electrodes Fermi level (as in HfO2), the electrons tunnel from trap to trap until they reach the anode. Otherwise, when traps are closer to the conduction band (as in Al2O3 and AlHfO), the electrons tunnel from the cathode into one trap and then into the oxide conduction band, interacting only with traps near the cathode. These findings may have profound implications for the functional optimization of future nano-electronics devices. Furthermore, since in metal oxides trapping, defects generation and breakdown processes are strongly related, results can provide new insight in the breakdown process of metal oxides, impacting on device reliability.
Baristiran, Kaynak Canan [Verfasser], and Bernd [Akademischer Betreuer] Tillack. "Characterization of Perovskite-like High k Dielectric Materials for Metal-Insulator-Metal Capacitors / Canan Baristiran Kaynak. Betreuer: Bernd Tillack." Berlin : Universitätsbibliothek der Technischen Universität Berlin, 2013. http://d-nb.info/1031280227/34.
Full textWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Full textThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Uppal, Hasan Javed. "Nanoscale performance, degradation and defect analysis of mos devices using high-k dielectric materials as gate stacks by atomic force microscopy." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.509394.
Full textTao, Liang. "Atomic-scale calculations of interfacial structures and their properties in electronic materials." The Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=osu1127163029.
Full textWang, J. B., and 王俊彬. "The Study of High-K material La2O3." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/75206457477114214117.
Full text國立交通大學
電子工程系
88
In recent years, there are large amounts of research and development of high K material for the reason of the scaling down and burst improvement of memory technology. The high K technology has reached a colossal success, just like BaSrTiO3 (BST, K=200), Ta2O5 (K=30~75), etc. But, there are several kind weaknesses of these developed high-K materials. One of them is the interfacial diffusion between the interface of the high K material and Si. For eliminating this effect, high K La2O3 gate dielectrics has been developed by using a process of direct thermal oxidization of deposited La. Using this high K material as the gate dielectric, MOSFETs and MOS capacitors have been fabricated. From the measurement of capacitance, the 33Å La2O3 has a K value of 27 that has an equivalent oxide thickness of 4.8 Å when considering the quantum correction. This high K is further evidenced from MOSFETs’ high current drive and high charge-to-breakdown comparable with SiO2 are obtained that demonstrates excellent reliability. Good dielectric integrity is evidenced from the low leakage current density of 0.06A/cm2 at -1V, high effective breakdown field of 13.5 MV/cm, low interface density of 3x1010ev-1cm-2. The achieved low equivalent oxide thickness is due to the high thermodynamic stability on Si and also stable for hydrogen annealing up to 550ºC.
陳彥廷. "The Integrated Investigation of High-k Material Al2O3." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/21493788954482447540.
Full textLu, C. H., and 呂承翰. "High-K material Al2O3 thin films as device insulators." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/29648442156745189807.
Full text國立交通大學
電子工程系
87
The scaling limit for gate oxide in VLSI is determined by the direct tunneling leakage current. Further device performance improvement can be obtained using a higher dielectric constant material. We have studied the aluminum oxide (Al2O3) as an alternative gate dielectric. In this thesis we report a very simple process to fabricate aluminum oxide (Al2O3) gate dielectric with K (~8 to 9.8) greater than the K of Si3N4. Aluminum oxide (Al2O3) is formed by directed oxidation from thermally evaporated Al. The 4.8nm aluminum oxide (Al2O3) has ~7 orders lower leakage current than equivalent 2.1nm SiO2. Good aluminum oxide (Al2O3)/ Si interface was evidenced by the low interface density of 5*1011 /cm2-ev and compatiable electron effective mobility with thermal SiO2. Good reliability is measured from the small SILC after constant current and constant voltage stress.
Yu, Chia-Chen, and 尤嘉正. "Simulation of MOSFET and Flash devices with High-K Material." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/79612221877414131488.
Full textShie, Wen-Bin, and 謝文斌. "The Interface Investigation of High-K Material Al2O3 on Si Substrate." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/rj66zh.
Full text國立交通大學
電子工程系所
92
Aluminum oxide (Al2O3) is one of the potential high-k materials. It has the higher dielectric constant (8~10), higher barrier height ( 2.9eV for electrons , and 4.3eV for holes ), and excellent thermal stability. In the thesis, physical, electrical and reliability characteristics of Al2O3 film with NH3 surface treatment and Post Deposition Annealing (PDA) in the O2 and N2 ambient were studied. The PDA can effectively reduce surface roughness. The PDA and NH3 surface treatments both can improve the C-V curves. Moreover, the lower leakage current is observed in NH3 surface treatment samples. The reliabilities can be improved by the NH3 surface treatment after PDA in a N2 ambient. The conduction mechanism in the Al2O3 thin film is dominated by the Schottky emission. To sum up, the characteristics of Al2O3 gate dielectrics with NH3 surface treatment and subsequent PDA treatment described above are effectively improved. This novel NH3 and PDA treatment provides an alternative for post metal-oxide deposition treatment in nanoscale device application.
Hsu, Shiou-Hau, and 許修豪. "Investigation of High-K Material HfO2 on Metal-Insulator-Metal Capacitor." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/04957264503747184756.
Full text國立交通大學
電子工程系所
94
Abstract Continuous down-scaling of the size of metal–insulator–metal (MIM) capacitors is required to reduce chip size and the cost of analog and RF ICs. The use of a high-k dielectric is the only way to achieve this goal, since decreasing the dielectric thickness to achieve high capacitance density degrades the leakage current. Metal-insulator- metal (MIM) capacitors are fabricated using sputtered HfO2 with Ta for top and bottom electrodes. A very high density of 25.67fF/um2 has been measured in metal–insulator–metal (MIM) capacitors which use high-k HfO2 the dielectric. The characteristics the MIM capacitors show the leakage current densities around 3.5×10-7 A/ cm2
Chen, Chi-Lin, and 陳麒麟. "Preparation of high–k material hafnium silicate by sol-gel method." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/43499511255535387204.
Full text國立高雄大學
應用化學系碩士班
96
In present study, the hafnium oxide and hafnium silicate films with different silicon/hafnium ratios were prepared on silicon substrate by sol-gel method. The thin films were high temperature annealed by furnace annealing or rapid thermal annealing (RTA). In order to investigate the thickness effects of hafnium oxide and hafnium silicate, one to five layers of thin films were deposited by repetitive spin-on process. Then, a Metal-Insulator-Semiconductor (MIS) structure was constructed for electrical properties analysis. The experiment results showed that both the one layer thickness and crystallization temperature of film increased with the ratios of silicon/hafnium, regardless of annealing conditions. The binding energy of film surface was studied by X-ray photoelectron spectroscopy (XPS) analyses and indicated that the signal position of Hf4f, Si2p and O1s shifted to a higher binding energy by increasing the silicon/hafnium ratio or the annealing temperature. Otherwise, the XPS results of the hafnium silicate thin films, after annealed by RTA, suggested a possible occurrence of phase separation. For electrical property measurement, upper electrode was deposited on top of high-k film and then post-annealed to improve the electrode/film interface properties. We found that post-annealing reduced the leakage current of films to be 10-8~10-9 A/cm and also suppressed their flat band voltage shift. In conclusion, most properties of the thin films were observed to be better by RTA process than by furnace process.
Chen, Shih-Chang, and 陳世璋. "The Interface Investigation of High-K Material HfO2 on Si Substrate." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/15185369275557096826.
Full text國立交通大學
電子工程系
91
According to the scalling rules, aggressive scaling has led to silicon dioxide (SiO2) gate dielectrics as ultra thin in state-of-the-art CMOS technologies. As a consequence, static leakage power due to direct tunneling through the gate oxide has been increasing at an exponential rate. As technology roadmaps call for sub-10Å gate oxides within the next five years, a variety of alternative high-k materials are being investigated as possible replacements for SiO2. The higher dielectric constants in these materials allow the use of physically thicker films, potentially reducing the tunneling current while maintaining the gate capacitance needed for scaled device operation. Hafnium oxide ( HfO2 ) is the most potential high-k material. It has the higher dielectric constant , higher barrier height ( 1.6eV for electrons , and 3.4eV for holes ), and excellent stability. In our experiments, the variation of leakage current , hump in C-V curves, interfacial layer increasing, and electron trapping are observed and investigated in un-surface treatment HfO2 samples. The rapid thermal oxide ( RTO ) and NH3 surface treatments both can improve the C-V curves. Moreover, the lower leakage current is observed in NH3 surface treatment samples. The results of stress induces leakage current ( SILC ) measurements show the severe electron trapping under the high electric field stress. The reliabilities can be improved by the RTO surface treatment, and the dielectric breakdown much depends on the quality of the interfacial layer. The conduction mechanism in the HfO2 thin film is dominated by the Frenkel-Poole emission.
Zhao, Han 1982. "A study of electrical and material characteristics of III-V MOSFETs and TFETs with high-[kappa] gate dielectrics." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2184.
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YU, SHENG-WANG, and 余聲旺. "Property of high k ceramic material and fabrication of trick film capacitor." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/15639755702394732797.
Full textChou, Tung-huan, and 周棟煥. "Low Temperature Polycrystalline Silicon Thin-Film Flash Memory with High-k Material." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/81042257150324009588.
Full text國立交通大學
電子物理系所
94
In this thesis, we proposed the fabrication of low temperature polycrystallize silicon thin film with nonvolatile flash memory as named the SONOS-type poly-Si-TFT memories. In addition, the different high-k materials of trapping layer were used in this experiment, including the HfO2, Hf-silicate and Zr-silicate. We also analyze the electrical properties and the reliability of the SONOS-type poly-Si-TFT memories. It was demonstrated that the fabricated memories exhibit good performance. First, the large memory window was shown in the device with three different trapping layers. Second, these samples would have the high program/erase speed (1ms/10ms). Third, all the three samples can be operated up to 108 s with only 30% charge loss for the data retention performance under room temperature operation. However, the data retention for the sample with Hf-silicate trapping layer can be operated up to 108 s with only 10% charge loss. Fourth, our devices also have long retention time (>106s for 20% charge loss) and negligible read/write disturbances. Fifth, the 2-bit operation has been successfully demonstrated in these devices with different trapping layers. We also discuss the electrical characteristics of SONOS-type poly-Si-TFT memories with different tunneling oxide thickness. The device with thicker tunneling oxide thickness would have better data retention performance than the sample with thinner tunneling oxide thickness. In addition, our device with thicker tunneling oxide thickness would have good program/erase speed as well as the device with thinner tunneling oxide thickness. However the gate and drain disturbance are still problems in low temperature poly-crystallize silicon thin film flash memories. After NH3 plasma treatment, the performances of data retention and disturbance would be improved for our SONOS-type poly-Si-TFT memories. This is because the hydrogen atoms of NH3 can terminate dangling bonds and replace the weak bonds in the grain boundaries and SiO2/poly-Si interface and thus reduce the trap states in the poly-Si channel. Thus, both the performance and reliability of poly-Si TFTs were also improved. As long as the drain and gate disturbance can be reduced, this TFT flash memories are very promising for the future flash memory application.
Huang, Ching-Chien, and 黃靖謙. "The Investigation of Metal-Insulator-Metal Capacitor Applying High-k Dielectrics Material." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/66095805506307248591.
Full text國立交通大學
電子工程系所
97
According to International Technology Roadmap for Semiconductor (ITRS), continuous increasing the capacitance density is required to scale down the device size and the cost of Metal-Insulator-Metal (MIM) capacitors which are widely for Analog, RF and DRAM functions. However, they often occupy a large fraction of circuit area. To meet these requirements, high dielectric constant (k) materials provide the only solution since decreasing the dielectric thickness (tk) degrades both the leakage current and ΔC/C performance. To achieve this goal, the only choice is to increase the k value of the dielectrics, which have evolved from SiON (k~4-7), Al2O3 (k=10), HfO2 (k~22), Ta2O5 (k~25) to Nb2O5 (k~40). To further achieve the properties of MIM such as low leakage current, low voltage coefficient of capacitance and low temperature coefficient of capacitance. Thus, we have developed novel process and high-k dielectric materials, such as TiNiO (k~30-40), TiPO (k~26-32) and SrTiO3 (k>50) to achieve this technology. To further improve the small bandgap (EG) of these dielectrics, we apply the higher work-function Pt (5.7 eV) and Ir (5.3 eV) top electrode are used to give better device performance. Although SrTiO3 has large dielectric (k~50-200), the small conduction band offset (ΔEc) and bandgap leading to larger leakage current is a larger drawback. Besides, SrTiO3 shows its higher k values by forming nano-crystals, which is only practicable at a higher process temperature > 450oC. Furthermore, the high voltage coefficient of capacitance of SrTiO3 is also an important issue. Because Ta2O5 has very low voltage coefficient of capacitance and can considerably suppressed the leakage current, the overall electrical characteristics of MIM device could be improved by doping Ta2O5 into SrTiO3 MIM capacitor. Otherwise, we have developed a plasma treatment on dielectric to repair the defect of the dielectric to improve leakage current, voltage coefficient of capacitance and temperature coefficient of capacitance at the same time. Therefore, not only high capacitance and low leakage current, but also small voltage/temperature dependence of capacitance are obtained under limited thermal budget for back-end-integration. In addition to the measurement of capacitance at low frequency and the leakage current, the measurement of the S-parameters to investigated the characteristics of the MIM capacitors at RF regime are also demonstrated. By using the simulation software, the capacitance density of MIM capacitors at different frequencies was extracted. Besides, the related factors such as understandings of the mechanism of conductivity, the voltage/temperature dependence of capacitances, barrier height, and interfacial layer were investigated, and these are also useful in the development of advanced MIM capacitors.
Lin, Ching-Lian, and 林慶廉. "Surface passivation of c-Si and HIT solar cells with high-k material." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/95779232098036805251.
Full text國立清華大學
電子工程研究所
102
Over 85% of the solar cells currently produced are based on crystalline silicon wafers. The efficiency of silicon solar cells is significantly affected by electronic recombination losses at the wafer surfaces. A surface passivation layer can be used to reduce electronic recombination losses. In this study, we used Atomic Layer chemical Deposition (ALD) to deposit high-k material as a passivation layer. At first we deposited different high-k materials on c-Si solar cells. We tried different passivation conditions, such as without high-k passivation, with Al2O3 in the front side, with Al2O3 on both sides, and with HfO2 on both sides. The result showed that cell with HfO2 on both sides achieved the highest efficiency of 15.542%. We also deposited HfO2 on HIT solar cells as surface passivation layer. Different passivation conditions such as without HfO2 passivation, with HfO2 on IP side, with HfO2 on IN side, and with HfO2 on both sides are used. HIT solar cell having passivation with HfO2 (8Å) on both sides achieved the highest efficiency. The highest efficiency obtained for HIT cell with HfO2 passivation was 11.68%, with a Voc of 0.61 V, Jsc of 31.276 mA/cm2 and FF of 0.612.
Huang, Jheng-Yu, and 黃證宇. "The Effect of Ternary Material (Zr, Y, and O) High-k Gate Dielectrics." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/27598816189012526266.
Full text國立臺灣師範大學
機電科技研究所
100
In this study, zirconium (Zr) was doped into the Y2O3 layer through co-sputtering before rapid thermal annealing (RTA) at 550 ℃, 700 ℃, and 850 ℃and Al electrode formation. Two structures were formed: Al/ZrN/Y2O3/Y2O3+Zr/p-Si and Al/ZrN/Y2O3+Zr/Y2O3/p-Si. When Zr was doped on the upper layer, the crystallization was more significant than when Zr was doped on the bottom layer, as shown in the X-ray diffraction (XRD) diagram. This result showed that Zr can suppress oxygen diffusion. Additionally, the atomic force microscopy (AFM) data also showed that the surface roughness was worse when Zr was doped on the upper layer. With regard to electrical properties, the overall leakage increased when Zr was doped on the upper layer (i.e. Al/ZrN/Y2O3+Zr/Y2O3/p-Si). Finally, regarding the Schottky emission mechanism, we compared and analyzed the samples of the same DC power and same annealing temperature. We found that the barrier height was higher when Zr was doped on the bottom layer (i.e. Al/ZrN/Y2O3/Y2O3+Zr/p-Si). The higher barrier height may be the dominant factor to result in a lower leakage current.
Chen, Yueh-Feng, and 陳岳鋒. "Study of Pd Nanocrystal Embedded in High-k Material for Nonvolatile Memory Application." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/12211158549442810532.
Full text逢甲大學
電子工程所
99
The Pd metal deposited on tunneling oxide can form nanocrystals by a subsequent annealing process. In this thesis, silicon oxide and hafnium aluminum oxide with different doped of aluminum were used as tunneling oxides, and applied on metal oxide semiconductor (MOS) capacitor and thin film transistor device. We focus on the effect of high temperature annealing on the electrical characteristic of MOS structure with different tunneling oxide, and the memory characteristic of TFT device. For MOS structure, the worse memory characteristics mainly are due to leakage current paths and shallow traps in tunneling oxide around Pd nanocrystals. The different expansion coefficients between Pd metal and silicon oxide/hafnium aluminum oxide induce defects in tunneling oxide and worsen the memory characteristic. Hafnium aluminum oxide as tunneling oxide of MOS structure can attain better memory characteristics as compared with the ones with SiO2 or HfO2 tunneling oxide. For TFT memory device, a memory characteristic can be obtained. However, the poor quality at the interfaces between tunneling oxide and Si substrate results in the reliability problems.
HSIEH, CHI-WEN, and 謝啟文. "In-situ Monitoring the Etching Process of High-K Material by Modulation Ellipsometer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/49215270794215308198.
Full textWang, Yanzhen. "Investigation of electrical and material characteristics of high-k / III-V MOS devices and SiOx ReRAMs." 2013. http://hdl.handle.net/2152/21961.
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Li, Ming-Han, and 李明翰. "Au Nanocrystal MOS Charge Storage Device By Using High-K Material As Tunneling Layer." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/67629614972670025679.
Full text國立臺灣大學
電子工程學研究所
94
The Au nanocrystal charge storage device by using High-K material as tunneling layer will be investigated in both C-V and Retention measurement to realize how the charge is programmed, erased and leaked. The tunneling layer material, such as HfO2 and HfSiO2, will be examined by XRD, IV, and CV measurement after different temperature annealing. The crystallization phenomenon is observed in HfO2 at high temperature. This phenomenon will decrease the performance of our device. In order to avoid crystallization, we use chemical redundant deposition to fabricate Au nano-dots. Because this process can be done in room temperature, we can keep HfO2 away from high temperature process. Owing to the high permittivity, HfO2 can be thicker than SiO2 in the same equivalent oxide thickness (EOT) and reduce the leakage current from Au nano-dots to silicon substrate. Thus, the retention of device by using HfO2 as tunneling layer is two times better than that by using SiO2 as tunneling layer. Another way to avoid crystallization is to change tunneling layer from HfO2 to HfSiO2. The crystallization phenomenon is not observed in HfSiO2 after high temperature annealing. At last, we are able to fabricate different density of Au dots in devices by using HfSiO2 as tunneling layer by controlling the deposition time. In this way, we can examine the relationship between the stored charge and the density of Au nano-dots.
Ye, Jia-hao, and 葉嘉豪. "Processing and Modeling of Integrated Passive Capacitor by High-K Material for RF Application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/92967789638949632203.
Full text國立雲林科技大學
光學電子工程研究所
97
In this research, we fabricate passive device capacitor with thin film fabrication technology. In this thesis, first part is fabrication and discuss MIM( Metal-Insulator- Metal ) capacitor of BST( Barium Strontium Titanate ). First, we used thermal evaporation method to deposit nickel(Ni) and copper(Cu) on quartz substrate, next deposit BST thin film with sputter method and hot temperature annealing. Finally, we used thermal evaporation method to deposit metal layers of nickel(Ni), copper(Cu) and nickel(Ni) respectively, then the MIM capacitor is achieved. Measuring the S-parameters with vector network analyzer(VNA) to get the different dielectric constant and capacitance, these parameters changing depend on frequency(1MHz ~6GHz), finally the physical equivalent model of MIM capacitor is been extracted. Based on the experimental results, we found dielectric constant on 1GHz are 15.4, 15.5 and 11.6 of no annealing, annealing 500℃ and 600℃ respectively, dielectric constant reduce when frequency increase. Then build up precise one port MIM capacitor equivalent circuit model by Agilent ADS according to comparison between measure and model data. Second part is fabrication and discuss IDC( Interdigital Capacitor ) of BST( Barium Strontium Titanate ). Fabrication process of IDC is the same of MIM Capacitor, but no bottom electrode, Measuring the S-parameters after finish IDC Capacitor with vector network analyzer(VNA) to get the different capacitance with changing device parameters on the frequency range (10MHz ~20GHz), finally extract physical equivalent model. Based on the experimental results, we found IDC16 capacitance on 1GHz are 599fF, 586 fF, 573 fF and 586 fF of no annealing, annealing 500℃, 600℃ and 700℃ respectively, these shown a unobvious difference. When finger numbers are 5, 7 and 9, IDC capacitance are 393fF, 586fF and 670fF respectively. When finger length are 1 and 2mm, IDC capacitance are 419fF and 468fF respectively. When finger width are 0.1 and 0.2mm, IDC capacitance are 551fF and 671fF respectively. Then build up precise two port IDC capacitor equivalent model in Agilent ADS according to the comparison between measure and model data. Third part is fabrication and discuss the CPW( Coplanar Waveguide ) of BST( Barium Strontium Titanate ), fabrication process of CPW is the same of IDC Capacitor. The purpose of CPW experiment is to extract dielectric constant of dielectric material. Based on the experimental results, dielectric constant is in the range of 4~7.5, approach the dielectric constant of quartz substrate, so equations are not precise on thin film fabrication technology, but get precise on thick film fabrication technology.
Fong-Chi, Shih, and 石豐綺. "Study on LTPS-TFT Flash Memory using High-k Material as Charge Trapping Layer." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/07856442760214408383.
Full text國立交通大學
電子工程系所
96
In this thesis, electrical characteristic and Reliability of low temperature poly- silicon thin film transistor nonvolatile flash memory have studied, including programming/erasing speed, retention, endurance, retention after cycling and programming disturbances. First, three kinds of high-k materials, SiNx, Al2O3 and Hf-silicate, respectively, were applied for charge trapping layer of n-channel TFT memories. The fabricated memory devices show great retention and disturbance characteristics, attributed to the thick tunneling oxide. Among these three materials, Al2O3 performs best. Then, the same three kinds of materials as mentioned above were applied for p-channel TFT flash memories. The p-channel memory devices show better programming speed, programming voltage and data retention ability than n-channel ones, result in the lowering of power dissipation. Among all p-channel memory devices, Al2O3 performs best, also. Last, the n-channel devices after NH3 plasma treatment show obviously improvement on endurance and data retention.
Yang, Tsung-Yuan, and 楊宗元. "The Study of Flash Memory with High-K Material and Nano-crystal Trapping Layer." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/44176968672899862260.
Full text國立交通大學
電子工程系所
94
In this thesis, first a tri-gate 55nm SONOS-type memories on SOI with HfSiOx nanocrystal trapping layers was proposed and demonstrated. We use CHE programming, FN programming, BTBHH erasing and FN erasing for the memory operation. Experimental results reveal that large memory windows, relative high P/E speed and good retention can achieve for SONOS-type memories and it is fully compatible to current CMOS technologies. In summary, tri-gate 55nm SONOS-type memories on SOI are the candidates used for the high density storage application. Then, a SONOS-type memories by using high-κ dielectric materials Lanthanum oxide trapping layers was proposed and demonstrated. We use CHE programming and BTBHH erasing for the memory operation. Experimental results reveal that large memory windows, relative high P/E speed and good retention can achieve for SONOS-type memories. In summary, La2O3 are the candidates used for the trapping layers for the SONOS-type memories and two-bit application. Finally, a SONOS-type memories by using high-κ dielectric materials Praseodymium oxide trapping layers was proposed and demonstrated. The SONOS-type Pr2O3 flash memories exhibit that they have large memory windows, relative high P/E speed but poor retention.
Chen, Yen-Ting. "A study of electrical and material characteristics of high-k / III-V MOSFETs and SiO2 RRAMs." 2012. http://hdl.handle.net/2152/19623.
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