Dissertations / Theses on the topic 'High-k materials'
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Sun, Xiao. "Characterization and Fabrication of High k dielectric-High Mobility Channel Transistors." Thesis, Yale University, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3578458.
Full textAs the conventional scaling of Si-based MOSFETs would bring negligible or even negative merits for IC's beyond the 7-nm CMOS technology node, many perceive the use of high-mobility channels to be one of the most likely principle changes, in order to achieve higher performance and lower power. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, InGaAs, GaSb, GaN...) to replace Si CMOS technology.
In this thesis, the distinct properties of the traps in the high-k dielectric/high-mobility substrate system is discussed, as well as the challenges to characterize and passivate them. By modifying certain conventional gate admittance methods, both the fast and slow traps in Ge MOS gate stacks is investigated. In addition, a novel ac-transconductance method originated at Yale is introduced and demonstrated with several advanced transistors provided by collaborating groups, such as ultra-thin-body & box SO1 MOSFETs (CEA-LETI), InGaAs MOSFETs (IMEC, UT Austin, Purdue), and GaN MOS-HEMT (MIT).
By use of the aforementioned characterization techniques, several effective passivation techniques on high mobility substrates (Ge, InGaAs, GaSb, GeSn, etc.) are evaluated, including a novel Ba sub-monolayer passivation of Ge surface. The key factors that need to be considered in passivating high mobility substrates are revealed.
The techniques that we have established for characterizing traps in advanced field-effect transistors, as well as the knowledge gained about these traps by the use of these techniques, have been applied to the study of ionizing radiation effects in high-mobility-channel transistors, because it is very important to understand such effects as these devices are likely to be exposed to radiation-harsh environments, such as in outer space, nuclear plants, and during X-ray or UHV lithography. In this thesis, the total ionizing dose (TD) radiation effects of InGaAs-based MOSFETs and GaN-based MOS-HEMT are studied, and the results help to reveal the underlying mechanisms and inspire ideas for minimizing the TID radiation effects.
Mutas, Sergej [Verfasser]. "Analysis of high-k materials with Local Electrode Atom Probe / Sergej Mutas." Aachen : Shaker, 2012. http://d-nb.info/1066198276/34.
Full textKirsch, Paul Daniel. "Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3034557.
Full textMudanai, Sivakumar Panneerselvam. "Gate current modeling through high-k materials and compact modeling of gate capacitance." Access restricted to users with UT Austin EID Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3038191.
Full textCheng, Cheng-Wei Ph D. Massachusetts Institute of Technology. "In-situ deposition of high-k dielectrics on III-V compound semiconductor in MOCVD system." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/59216.
Full textIncludes bibliographical references (p. 164-168).
In situ deposition of high-k materials to passivate the GaAs in metal organic chemical vapor deposition (MOCVD) system was well demonstrated. Both atomic layer deposition (ALD) and chemical vapor deposition (CVD) methods were applied in this research. The CVD aluminum nitride (AIN) was first selected to be in situ deposited on GaAs surface by using trimethlyaluminum(TMA) and dimethylhydrazine (DMHy). However, the frequency dispersion of Capacitance-Voltage (C-V) curves for in situ AIN/GaAs samples are always large because of the existence of high interfacial defect state density (Dit) due to the nitridization of the GaAs surface during the AIN deposition. In order to avoid the surface reaction, in situ ALD of aluminum oxide (A1₂O₃) on GaAs in MOCVD system was proposed. Isopropanol (IPA) was chosen as the oxygen source for A1₂O₃ ALD and the mechanism was investigated. Pure A120 3 thin film was obtained and no arsenic or gallium oxide was observed at the interface. Both frequency dispersion of C-V curve and the Di, of oxide/p-GaAs interface are low for this process. In situ CVD A1₂O₃ on GaAs was also performed. Gallium oxide (Ga₂O₃) was observed at the interface. The Ga₂O₃ was enriched in the A1₂O₃ above the interface during the deposition process and a possible mechanism was proposed. This layer reduces the frequency dispersion of the C-V characteristics and lowers the Dit of n-type GaAs sample. After the in situ method had been successfully established, ex situ experiments was also performed to compare the results with in situ process in the same MOCVD system. Annealing native oxide covered GaAs samples in Arsine (AsH 3) prior to ALD A1₂O₃ results in C-V characteristics of the treated samples that resemble the superior C-V characteristics of p-type GaAs. Besides, both TMA and IPA show self-cleaning effect on removing the native oxide in ex situ process. The discrepancy in the C-V characteristics was observed in in situ p- and n-type GaAs samples. Finally, the entire Dit energy distributions of interfaces from different processes were determined by conductance frequency method with temperature-variation C-V measurement. The existence of Ga₂O₃ at interface was found to be the possible source to lower the density of mid-gap defect state. From the C-V simulation, the mid-gap defect states are acceptor-like (Gallium Vacancies) and the source to cause high frequency dispersion of the C-V curves for n-type substrate. The relation between the interfacial defect state distribution and the processes was correlated.
by Cheng-Wei Cheng.
Ph.D.
Gao, Yong. "Deposition, stabilization and characterization of zirconium oxide and hafnium oxide thin films for high k gate dielectrics." Diss., The University of Arizona, 2004. http://hdl.handle.net/10150/290136.
Full textLi, Haoxiang. "Angle-Resolved Photoemission Spectroscopy Study of High Temperature Superconductor Cuprate, and Potential High Temperature Superconductors K-Doped p-Terphenyl and Trilayer Nickelate." Thesis, University of Colorado at Boulder, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10642070.
Full textThe macroscopic quantum phenomenology of superconductivity has attracted broad interest from both scientific research and applications. Many exotic physics found in the first high $T_C$ superconductor family cuprate remain unsolved even after 30 years of intense study. Angle-Resolved Photoemission Spectroscopy (ARPES) provides the direct probe to the major information of the electronic interactions, which plays the key role in these exotic physics including high $T_C$ superconductivity. ARPES is also the best tool to study the electronic structure in materials that potentially hold high $T_C$ superconductivity, providing insight for materials research and design. In this thesis, we present the ARPES study of the cuprate high $T_C$ superconductor Pb doped Bi$_2$Sr$_2$CaCu$_2$O$_{8+\delta}$, and potential high $T_C$ superconductors K doped \textit{p}-terphenyl, and trilayer nickelate La$_4$Ni$_3$O$_{10}$. For Pb doped Bi2212, our study focuses on the key part of the electronic interactions---the self-energies. With the development of a novel 2-dimensional analysis technique, we present the first quantitative extraction of the fully causal complex self-energies. The extracted information reveals a conversion of the diffusive strange-metal correlations into a coherent highly renormalized state at low temperature followed by the enhancement of the number of states for pairing. We then further show how this can lead to a strong positive feedback effect that can stabilize and strengthen superconducting pairing. In K doped \textit{p}-terphenyl, we discover low energy spectral gaps that persist up to 120 K, consistent with potential Meissner effect signal from previous studies. Among a few potential origins for these gaps, we argue that the electron pairing scenario is most likely. For La$_4$Ni$_3$O$_{10}$, we present the Fermiology and electron dynamics of this material, and they show certain similarities to the cuprate electronic structure, as well as a few unique features.
Reddy, Raj. "A study of high-K dielectric materials in conjunction with a multilayer thick-film system." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43280.
Full textMaster of Science
Sreenivasan, Raghavasimhan. "Metal-gate/high-k dielectric stack engineering by atomic layer deposition : materials issues and electrical properties /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Full textTse, Koon-Yiu. "High-K gate oxides and metal gate materials for future complementary metal-oxide-semiconductor field-effect transistors." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611979.
Full textXia, Zhanbo. "Materials and Device Engineering for High Performance β-Ga2O3-based Electronics." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587688595358557.
Full textBaristiran, Kaynak Canan [Verfasser], and Bernd [Akademischer Betreuer] Tillack. "Characterization of Perovskite-like High k Dielectric Materials for Metal-Insulator-Metal Capacitors / Canan Baristiran Kaynak. Betreuer: Bernd Tillack." Berlin : Universitätsbibliothek der Technischen Universität Berlin, 2013. http://d-nb.info/1031280227/34.
Full textGuiraud, Alexandre. "Intégration de matériaux à forte permittivité diélectrique dans les mémoires non volatile avancées." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4763/document.
Full textThe work of this thesis is on integration of high dielectric constant materials (High-k) as dielectric interpoly in Flash non volatile memories. The objective is to determine which High-k materials are suitable as interpoly dielectric in place of the ONO stack currently used. A range of High-k materials have been studied by electrical characterizations (I-V, C-V, breakdown statistics…) and physical characterizations (TEM, EDX, XPS…) in order to select those with the best properties for an interpoly dielectric. The difficulties in integration of High-k materials in a Flash memory process flow have been taken in account and solutions have been proposed
Niu, Gang. "Epitaxy of crystalline oxides for functional materials integration on silicon." Phd thesis, Ecole Centrale de Lyon, 2010. http://tel.archives-ouvertes.fr/tel-00601689.
Full textUppal, Hasan Javed. "Nanoscale performance, degradation and defect analysis of mos devices using high-k dielectric materials as gate stacks by atomic force microscopy." Thesis, University of Manchester, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.509394.
Full textWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Full textThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Han, Lei. "Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices." UKnowledge, 2015. http://uknowledge.uky.edu/ece_etds/69.
Full textTao, Liang. "Atomic-scale calculations of interfacial structures and their properties in electronic materials." The Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=osu1127163029.
Full textHossain, Md Tashfin Zayed. "Electrical characteristics of gallium nitride and silicon based metal-oxide-semiconductor (MOS) capacitors." Diss., Kansas State University, 2013. http://hdl.handle.net/2097/16942.
Full textDepartment of Chemical Engineering
James H. Edgar
The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.
Midy, Jean. ""Etude de la croissance du titanate de baryum et de strontium en couches minces et de ses propriétés électriques sur une large gamme de fréquence"." Phd thesis, Université de Valenciennes et du Hainaut-Cambresis, 2012. http://tel.archives-ouvertes.fr/tel-00739398.
Full textKUNIOSHI, CLARICE T. "Estudo do comportamento de erosao-oxidacao de materiais compositos de NiCr com WC e Crsub(3)Csub(2)." reponame:Repositório Institucional do IPEN, 2004. http://repositorio.ipen.br:8080/xmlui/handle/123456789/11239.
Full textMade available in DSpace on 2014-10-09T14:02:19Z (GMT). No. of bitstreams: 1 09819.pdf: 15341022 bytes, checksum: 089b1783177dd73c7433320bd2e0de7c (MD5)
Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
Tese (Doutoramento)
IPEN/T
Instituto de Pesquisas Energeticas e Nucleares - IPEN/CNEN-SP
FAPESP:98/05906-6
Xu, Toby Ge. "Material and array design for CMUT based volumetric intravascular and intracardiac ultrasound imaging." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54861.
Full textChen, B. P. T. "Deposition and material characterisation of alternative high-K gate oxides." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.597522.
Full textRenaudot, Raphaël. "Conception, fabrication de puces microfluidiques à géométrie programmable et reconfigurable reposant sur les principes d’électromouillage sur diélectrique et de diélectrophorèse liquide." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENY080/document.
Full textIn the field of lab-on-a-chip (LOC) systems, the channel geometry of a microfluidic chip is often specific to perform a given protocol. The chip geometry is hence defined at the design step, before the fabrication steps (generally time consuming and expensive) and cannot be thereafter modified. This fact becomes an issue when the geometry does not fit satisfactorily to the specifications and a new batch of fabrication has to be started, to size afresh the microfluidic chip. To overcome this inconvenient we propose to develop a new generation of microfluidic chips with a programmable and reconfigurable geometry. This concept is widely based on both digital microfluidic techniques, the electrowetting on dielectrics (EWOD) and the liquid dielectrophoresis (LDEP) actuations. The first investigation is focused on the microfluidic technique LDEP. First, an electromechanical model for liquids behaviours during a EWOD or LDEP actuation is established. This model is then used as a basis for the LDEP patterns design and fabrication. The LDEP patterns are tested to identify the geometries and dielectric layers stacks which give optimized LDEP actuations. By taking into account a broad parameters range, the study shows that, within a precise setup and specific conditions, the LDEP actuations can have equal performances at the minimum, or better performances than those reported in the overall scientific literature until now. Finally, a surface functionalization protocol by polymer spots (diameter size ranging from a few microns to several dozens of microns) utilizing the LDEP technology is described. This method is likely to compete directly with the standard functionalization tools. The second investigation is dealing with the programmable and reconfigurable geometry concept, thanks to microfluidic platforms which get together both EWOD and LDEP technologies on a same component. Firstly, the microfluidic platform in a single plate configuration allows providing master molds with a programmable geometry for the PDMS microfluidic chip fabrication. The results about this promising study lead to the processing of complex channels geometries, typically used in the microfluidic field. Secondly, the more exciting results are exposed about the programmable and reconfigurable microfluidic concept, by using advantageously the paraffin material. A specific protocol which takes advantages of LDEP and EWOD liquids displacements produces a lot of various and different microfluidic chips with complex channels shapes. For both applications, a single generic microfluidic platform can generate a wide number of different geometries, which can be modified partially or totally thereafter. The obtained results open up novel and promising work prospects, which one of them are approached on the fringe of the initial purposes. The first one belongs to the continuity of the programmable and reconfigurable by suggesting a low cost technology based on flexible Kapton substrate and inkjet printing of silver nanoparticules. The second one investigates the technologies compatibility between MEMS/NEMS resonating structures and LDEP metal structures (in polysilicon) at the submicronic scale
Wang, Jiahui. "High-K Material Based Leaky-wave Antenna Design, Implementation, and Manufacture." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1347582062.
Full textGarreau, Jonathan. "Étude de filtres hyperfréquence SIW et hybride-planaire SIW en technologie LTCC." Phd thesis, Université de Bretagne occidentale - Brest, 2012. http://tel.archives-ouvertes.fr/tel-00858068.
Full textLi, Wenmei. "CHARACTERIZATION OF HIGH-K GATE STACKS IN METAL-OXIDE-SEMICONDUCTOR CAPACITORS." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20010202-100109.
Full textThe purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-k dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterization methodologies were established to evaluate high-k dielectrics at various processing levels, which, in part, determine the final characteristics of an advanced gate-stack device. Material systems that were investigated include: Al-O, Hf-Si-O, Zr-Si-O, Ti-O, Ta-O and Sr-Ti-O. Various physical and electrical characterization techniques were used to establish fundamental understandings of the materials selected, thin-film growth/deposition processes, and gate-stack structures. General conclusions for stable and unstable gate-dielectric materials have been establishedregarding the presence of a problematic interfacial layer at the Si/dielectric interface, graded dielectric layers, and the stability of gate electrodes on high-k dielectrics.The nanometer-scale chemistry of a gate-stack capacitor whose expected structure is Si/SiOxNy/Ta2O5/TiN/Al was studied by high-resolution electron-energy-loss spectroscopy in a scanning transmission electron microscope. Elemental profiles with near-atomic-level resolution for Si, Ti, N, Al, and O demonstrate that the device structure deviates drastically from the expectation and is chemically complex.It is concluded that the graded distribution of certain elements across the gate-stack capacitor completely precludes a band-structure model that assumes abrupt interfaces and chemically discrete layers. This study impacted on subsequent interpretations of flatband voltage extractions and electrical degradation following backside metallization/postmetallization annealing for capacitors whose dielectric-stack was based on Ta-O.Detailed and extensive electrical characterizations of Pt/SiOx/Sr-Ti-O/Si MOS capacitors were carried out to investigate reliability issues in a bi-layer gate dielectric. Based on these studies, models are proposed to describe the carrier transport and dielectric degradation for a Sr-Ti-O capacitor. It is concluded that conduction is dominated by Frenkel-Poole emission from mid-gap trap levels. The trap barrier height is estimated to be 1.51eV. A model based on the atomic and electronic structure of oxygen vacancies can account for the reported leakage-current characteristics. In addition, it is tentatively proposed that anode-hole injection and hole trapping control the dielectric degradation under gate injection.
Bure, Taylor Rose. "Inelastic background analysis from lab-based HAXPES spectra for critical interfaces in nano-electronics." Electronic Thesis or Diss., Université Clermont Auvergne (2021-...), 2023. http://www.theses.fr/2023UCFA0125.
Full textThis work uses lab-scale hard X-ray photoelectron spectroscopy (HAXPES) in the perspective of inelastic background analysis (IBA) for applications in the metrology field in order to provide thickness measurements of technologically relevant materials in memory and power devices. We seek to meet the need for a method adapted for inline processes and routine analysis. The samples presented in this work were fabricated by pre-industrial processes and are representative of real device technology with concerns like complex interdiffusion properties and deeply buried active layers and interfaces. In this work, we evaluate the HAXPES-IBA technique executed with QUASES software by studying the free parameters, the operator contributions, and uncertainty in the depth distribution. We present a self-contained analysis by accessing high energy photoelectron spectra of elements from each sample layer recorded with a novel lab-scale HAXPES instrument (PHI Quantes) fitted with a Cr Kα photon source (hv = 5414.72 eV). First, highly controlled reference samples of known thicknesses (Al2O3 and HfO2 thin films) were studied to confirm the accuracy of the IBA method through validation against highly quantitative reference techniques. HAXPES-IBA thickness determinations of bilayer samples with a thick overlayer up to 25 nm and a buried layer of approximately 2.5 nm were found to be in excellent agreement with results from X-ray reflectivity (XRR) with fitting uncertainty of the IBA solution in the sub-nanometer range. The need to select the appropriate HAXPES excitation energy depending on total film thickness was demonstrated thanks to complimentary HAXPES measurements recorded with Ga Kα radiation (hv = 9251.74 eV). Finally, we apply the method to realistic technological samples. In the first study, we present thickness results from a sample class of Al2O3 films deposited over GaN by atomic layer deposition (ALD), representative of a recessed gate MOS channel High Electron Mobility Transistor (HEMT). Quantitative secondary ion mass spectrometry (SIMS) measurements compliment the IBA technique by confirming need for reference spectrum. In the second study, the HAXPES-IBA method is combined with ion sputtering to confirm the Ti/TiN overlayer thickness in a Ti/HfO2-based structure used for oxide resistive random access memory (OxRRAM) technology. We provide a critical summary of advances to reach for an accurate and reliable HAXPES-IBA method fully-integrated into inline process control
Bobba, Venkata Nagamalli Koteswara Rao. "High Fidelity Raman Chemical Imaging of Materials." Cleveland State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=csu1462806523.
Full textGuerrero, Enriquez Rubén Dario. "Etude des filtres miniatures LTCC High K en bandes L&S." Thesis, Brest, 2016. http://www.theses.fr/2016BRES0036/document.
Full textIn current communication systems, whether terrestrial or spatial, whether fixed or mobile, there is a real interest in developing high performance miniature RF front-ends. This is applied in particular to filter devices, in which the size and the quality factors are clearly in conflict. For low frequency bands around the GHz, the wavelengths remain significant, making it difficult the miniaturization efforts. On the other hand, we must also ensure that these filters will be easily interconnected with other other system components, including active devices.For all these reasons, the development of multilayer filter structures using high permittivity substrates (Er = 68) in an LTCC approach is consolidated as an interesting alternative. It may lead to a significant footprint reduction without decreasing the electrical performances.As part of this work, two multilayer filter structures have been developed to meet the given specifications in L and S bands, given by a space manufacturer. These filters have as main features a high rejection level and low losses in the passband. To meet the specifications, a vertically stacked SIW filter and a short-circuited stubs filter in a stripline configuration were studied. The SIW filter is characterized by a high quality factor, which results in low insertion loss and good flatness. The stubs filter allows in contrast to reduce the footprint but at the price of impacting the electrical performance. In both cases we take advantage of the flexibility offered by the LTCC technology as it finally provides an additional freedom degree compared to a conventional planar approach. For the SIW filter, the topological architecture was studied and designed in detail, to be able to arrange and synthetize couplings between twelve cavities. In a similar way, for the stub filter a synthesis that takes profit of all the offered freedom degrees was developed.Given the filters complexity, especially due to the high order and the implementation of “electrical walls" based on specific vias patterns, a close attention must be paid during the simulation and optimization phase. In addition, the high permittivity substrate does not allow to conceive 50-Ohms lines. Finally, access transitions constitute a challenging task, especially for the SIW case.This thesis was co-funded by CNES (Centre National d'Etudes Spatiales) and Thales Alenia Space, and was accompanied by an R&T project funded by CNES. The German foundry Via Electronic was responsible for the filters fabrication
Tewg, Jun-Yen. "Zirconium-doped tantalum oxide high-k gate dielectric films." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1346.
Full textCurtis, Nathaniel Carpenter Lynn. "Multilayer filter design with high k materials." 2009. http://etda.libraries.psu.edu/theses/approved/PSUonlyIndex/ETD-4358/index.html.
Full textTze-Chiang, Chen. "Optical and Electrical Propterties of High-k Dielectric Materials." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1407200615114300.
Full text賴妍心. "Nonvolatile Memory with High-k Dielectric Materials and Nanocrystals." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/44206378672516968607.
Full text國立交通大學
電子工程系所
96
In this thesis, we design various nonvolatile memories with several high-k material films as charge-trapping layers. The high-k layers replace the conventional silicon nitride trapping layer and silicon dioxide blocking layer in the SONOS structure. We modified the treatment during the process such that we can fabricate the nanocrystal flash memories. In particularly, we complete the source/drain and the tunnel oxide first. First, we present the SONOS-type flash memory that was fabricated using hafnium oxide (HfO2) film and hafnium silicate (HfSiOx) film as the trapping storage layer. The tunnel oxide are both 2nm. These HfO2 memories exhibit faster programming/erasing speeds due to the higher dielectric constant. Because of that the tunnel oxide is 2nm and higher field across the tunnel oxide in HfO2 case, the data retention of HfO2 case is worse than HfSiOx case. In particularly, no any high-temperature process is used in all deposited high-k film and these high-k memories depict unobvious window shift after 10K P/E cycles. Therefore, the quality of both high-k films are high potential for application. Then, we compare with the SONOS-type flash memories that was fabricated using hafnium oxide (HfO2) nanocrystals and CeO2 nanocrystals as trapping storage layer. We observe the CeO2 case depicts the better performance. Next, we use two high-k material films to replace the conventional SiO2 film as blocking layer and change the trapping storage layer with HfO2 film. We can use F-N program/ erase without a hitch by transferred the material. The high-k material include Al2O3 and HfAlOx case depicts the better performance due to its higher dielectric constant.
Lee, Ming-Ling, and 李明玲. "High-k and sensitive materials for bio-sensor applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/megv2z.
Full text國立交通大學
電子研究所
106
High-dielectric-constant (high-k) materials have recently been applied as ion sensing membrane. Compared with the traditional SiO2 sensing membrane, these high-dielectric materials have higher sensing performance. In this paper, the physical properties and sensing characteristics of some ne high-k materials were studied. First, consider zinc oxide (ZnO): Zinc oxide which is a transparent conductive oxide (TCO) has been demonstrated to be applicable to sensing membrane. Previous studies have shown that ZnO can be deposited by molecular beam epitaxy (MBE) to form a pH sensing film. This paper proves (1) ZnO film was deposited on the silicon substrate by RF sputtering and subjected to RTA annealing process. Then apply electrolyte-insulator-semiconductor structure (EIS) to form the pH sensing device, which provided a feasible application of optoelectronic devices integration. (2) Incorporation of titanium (Ti) into ZnO film during RF sputtering can significantly improve the surface characteristics of the film and improve sensing sensitivity. The device with ZnO sensing membrane is sensitive for bio sensing items has been demonstrated by the sensing characteristics (pH sensitivity, hysteresis, drift, and selectivity) of these films. Secondly, compare zinc oxide (ZnO) with Cerium dioxide (CeO2) : This paper proves (1) The pH sensitivity of CeO2 film which was deposited on the silicon substrate by RF sputtering and subjected to RTA annealing process is better than ZnO film. (2) To enhance the material quality and sensing performance, annealing treatment in N2 and O2 ambient has been incorporated. Results indicate that annealing treatment in O2 ambient exhibited a better sensitivity than N2 ambient, due to Oxygen in O2 ambient may cause stronger reflow and fill in the oxygen vacancy. Finally, discuss the antimony trioxide (Y2O3) and nickel dioxide (NiO2) : (1) Y2O3 with high dielectric constant、large conduction band offset、wide energy band gap and good dielectric thermal stability, is one of the potential materials for memory applications. This paper proves that a Ti-doped Y2O3 (Y2Ti2O5) dielectric on polycrystalline silicon followed by rapid thermal annealing results in improved characteristics including a higher effective dielectric constant, lower electron trapping rate, and larger breakdown voltage. (2) NiO2 with high dielectric constant and wide energy bandgap. In this study, we proposed a metal-oxide-high-k-oxide-silicon (MOHOS) memory device using NiO2 film as the charge trapping layer traditional floating gate memory, and applied RTA to improve electrical and physical properties, including a larger C-V hysteresis window, better data retention, and smaller charge loss compared to other annealed samples. This type of MOHOS memory device shows great promise for future memory applications. In the future, we will also study EIS sensor with Y2O3 or NiO2 sensing membrane.
Su, Hsuan-Hsiang, and 蘇煊翔. "Improvement on low-temperature deposited high-k materials by high-pressure treatment." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/6jvg9s.
Full text國立中山大學
光電工程研究所
97
In this study, high-pressure oxygen (O2 and O3) technologies were employed originally to effectively improve the properties of low-temperature-deposited metal oxide dielectric films. In this work, 5 nm ultra-thin HfO2 and ZrO2 films were deposited by sputtering method at room temperature. Then, the low temperature high-pressure oxygen treatments at 150 °C were used to replace the conventional high temperature annealing for HfO2 and ZrO2 improvement. From the experimental results, O3 produced by UV light illumination in O2 ambient has the superior passivation ability than O2, and it can further suppress leakage current density and improve capacitance characteristics. According to the XPS analyses, the absorption peaks of Hf-O and Zr-O bonding energies apparently raise and the quantity of oxygen in HfO2 and ZrO2 film also increases from XPS measurement. In addition, both the leakage current density of 5nm HfO2 and ZrO2 film can be improved to 10-8 A/cm2 at |Vg| = 3 V, and the conduction mechanisms were transferred from trap-assisted tunneling to thermal emission because of the significantly reduction of defects. All the experiment processes in this study, the temperatures were controlled below 150 °C. The proposed low-temperature and high pressure O2 or O3 treatment for improving high-k dielectric films is novel and applicable for the future flexible electronics.
Lei, Ming active 2012. "Nonlinear optical characterization of advanced electronic materials." 2012. http://hdl.handle.net/2152/22251.
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Lin, Ching-Hsien, and 林京憲. "First-Principle Investigation on Oxygen Vacancy in High-K Dielectric Materials." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/18940294968448298313.
Full text國立高雄應用科技大學
電子工程系
97
Recently, the thickness of gate oxide made from SiO2 in nano-scale MOSFET has reached a physical limit according to the current leakage. The High-K dielectric materials have been found to be a good solution to the problem. However, there is a tradeoff between the dielectric constant and the energy gap in High-K materials, a larger dielectric constant usually associated with a smaller energy gap. To solve this problem a multilayer structure is adopted, for example a TiO2 grown on HfO2. In this work, an alloy oxide of Hf(1-X)TiXO2 is studied because the properties of TiO2 are complementary to HfO2. The density function theory (DFT) with the DMol3 and CASTEP codes is applied to investigate High-K alloy dielectric materials of Hf(1-X)TiXO2 and Hf(1-X)TiXOY. The mix-atom mode is used to model the alloy oxide. In out study, we find that (i) the position of minority atoms strongly affects the physical properties of bulk material, (ii) the high Ti concentration is easier to produce oxygen vacancies than the low concentration, and (iii) the increase of the Ti concentration decreases the energy gap but increases the dielectric constant. According to these properties, the Hf(1-X)TiXO2 may have possibility to be used as a High-K dielectric layer in nano-scale MOSFET.
Hsueh, Chien-Lan. "Alternative materials for next-generation transistors high-k/Ge-based MOSFET." 2008. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17141.
Full textChang, Youling, and 張佑翎. "Reliability of HfO2 High-k Materials under Dynamic and Static Stress." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/20622670106749666584.
Full text國立暨南國際大學
電機工程學系
100
In this thesis, we studied the reliability of HfO2 film under static stress and dynamic stress. The research topics are: (1) Effects of the surface pre-treatment； (2) Effects of the gate-electrode area. First, we used atomic layer deposition (ALD) HfO2 film with different deposition thicknesses and various surface pre-treatments to measure the electrical properties and reliability of the metal-oxide-semiconductor capacitor (MOSC). Experimental results indicate that HfO2 film with ozone (O3) pre-treatment has best performance in the leakage current, flat-band voltage, hysteresis, and charge trapping. On the other hand, the HfO2 films without RCA standard clean present the worst electrical characteristics. For the reliability performance, irrespective of the deposition thickness, the HfO2 film with O3 pre-treatment has better breakdown field and lifetime due to a lower generation of interface traps during stress as compared with other surface pre-treatments. In addition, the improvement in lifetime of the HfO2 capacitors with various pre-treatments under dynamic stress is different. The HfO2 capacitor with O3 pre-treatment under dynamic stress has the best improvement of lifetime. It can improve the lifetime by 6.65 times. While the HfO2 capacitor without RCA standard clean only improve the lifetime by 5.97 times. This difference is due to the less accumulated charges of the HfO2 capacitors with O3 pre-treatment during dynamic stress. Second, we compared the electrical properties and reliability of HfO2 capacitors with different gate-electrode areas. Experimental results indicate that the HfO2 capacitor with a larger area has more charge and traps during stress and results in the worst electrical performance. However, the HfO2 capacitor with a larger area under dynamic stress behaves the better electrical improvement because the effect of charge detrapping becomes effective. Compared to static stress, the HfO2 capacitor with a larger area under dynamic stress can improve the leakage current by 2.14 times and this improvement is reduced as the gate area decreases. For the reliability performance, as the area of HfO2 capacitor decreases, the phenomenon of soft breakdown is increased and the breakdown time increases. This is due to the soft breakdown represents the charge trapping-detrapping in the gate dielectrics. Additionally, a higher frequency and lower duty cycle in the dynamic stress resulted in a longer lifetime enhancement. Irrespective of the static and dynamic stress, the breakdown distributions of HfO2 capacitors with various areas can be merged to a single Weilbull plot, suggesting that the dielectric breakdown is intrinsic for both cases. Additionally, increasing the stress time and voltage of the opposite polarity in the dynamic stress enhanced the dielectric breakdown lifetimes. We also found that an increase in the dielectric breakdown time is observed as the stress at the opposite polarity above 10-3 s, indicating that there is a critical time for enhancement in charge detrapping.
Yang, Che-Yu, and 楊哲育. "Application Technique of Stacking High-k Dielectric Materials on MOS Device." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/62265826364008893915.
Full text國立臺灣大學
電子工程學研究所
100
The result of this dissertation was divided into two parts. In the first part, it includes anodic oxidation (anodization) process，alternating-current anodization compensation technique and tandem structure to improve high-k dielectrics materials on Si substrate. In the second part, the capacitance- voltage deep depletion phenomenon of HfO2/SiO2 stacks was studied. Firstly, we propose a method that ultra-thin SiO2 was grown on p-type Si substrate by anodization in ambient temperature, then thin Al was deposited on top of SiO2 by thermal evaporation. Thin Al was oxidized to Al2O3 as high-k dielectrics by HNO3 oxidation. In addition, anodization compensation technique was adopted to improve the interface property between Al2O3 and SiO2 and also to compensate the trap. On the other hand, we propose a tandem structure in order to make Al oxidize completely and improve interfacial property thoroughly. Finally, the characteristics of dielectric were analyzed further by using transmission electron microscope (TEM) and energy dispersive X-ray (EDX) spectrometer to know the composition of material. It also provides the information of the physical thickness and related properties of material. Secondly, we study the capacitance-voltage deep-depletion phenomenon of MOS structure with HfO2/SiO2. It was found that much possibility and larger amount of tunneling current would pass through the deep depletion region. Besides, we observed that the characteristics of charge collection were enhanced under the edge fringing field effect. Carriers of the photoluminescence were largely absorbed at the edge of device especially under illumination. In addition, responsivity R and photosensitivity Ps which were evaluative figure for photo-electrical applications were examined and discussed. The slope κ of photocurrent versus irradiance curves reaches to 1.59 which is feasible for image sensor. These results are attributed to the enhanced edge deep depletion absorption of light due to edge fringing field effect. Further analysis of photoelectrical characteristics was carried out and the energy band diagrams were also given to explain the mechanism of device physics.
Cuo, Jiunn-Chyi, and 郭俊麒. "Compound High-k Materials For The Passivation of Silicon Solar Cells." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/09926031228968639634.
Full textHande, Aarabhi A. "Atomic layer deposition of lanthanum based oxides for high-k gate dielectric applications /." 2008. http://proquest.umi.com/pqdweb?did=1650508651&sid=1&Fmt=2&clientId=10361&RQT=309&VName=PQD.
Full textWu, Kai-Ting, and 吳凱庭. "Study on the Tungsten Nanocrystal and High-k Materials for Nonvolatile Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/30062975489906291769.
Full textLin, Yu-Hsien, and 林育賢. "Study on Novel Nonvolatile Memory with High-k Dielectric Materials and Nanocrystals." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/11789648904276112560.
Full text國立交通大學
電子工程系所
94
In this thesis, we design various nonvolatile memory with a high-k charge-trapping layer and nanocrystals. This high-k layer replaces the silicon nitride layer in the SONOS structure. Different program/erase methods are also proposed for low power applications. This nonvolatile memory structure will have superior characteristics in terms of considerably large memory window, high speed program/erase, long retention time, and excellent endurance. First, we present a novel nonvolatile SONOS-type flash memory that was fabricated using hafnium oxide (HfO2) nanocrystals as the trapping storage layer. These HfO2 nanocrystal memories exhibit excellent data retention, endurance, and good reliability, even for the cells subjected to 10k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile flash memory applications. Then, we demonstrate the effect of the post-deposition annealing for the HfO2 trapping layer on the performance of the SONOS-type flash memories. It was found that the memory window becomes larger while the retention and endurance characteristics get worse as the annealing temperature increases. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps as compared to the traps presented in the as-fabricated HfO2 film. Finally, in the aspect of disturbances, we show only insignificant read, drain and gate disturbances presented in the three samples in the normal operation. Next, we have successfully fabricated SONOS-type poly-Si-TFT memories employing three kinds of high-k dielectrics, including HfO2, Hf-silicate and Zr-silicate, as the trapping layer with low-thermal budget processing. It was demonstrated that the fabricated memories exhibit good performance in terms of relatively large memory window, high program/erase speed (1ms/10ms), long retention time ( >106s for 20% charge loss) and negligible read/write disturbances. In particular, 2-bit operation has been successfully demonstrated. Finally, we demonstrate 50nm nonvolatile HfO2 nanocrystal memory on SOI wafer. With this technique, which is fully compatible to current CMOS technologies, to form the very local HfO2 nanocrystals for the application of the nonvolatile flash memories. For aggressively scaling the conventional nonvolatile floating gate memories below sub-70nm node, we can successfully achieve the nano-devices for the application in the next-generation nonvolatile memories
Chan, Tsun Cheng, and 詹圳正. "Study of TiO2 and Nd2O3 High-k Materials Deposited on Polycrystalline Silicon." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/09601866248121861106.
Full text長庚大學
電子工程學研究所
98
In this study, metal induced crystallization (MIC) is used to replace the solid phase crystallization (SPC) to get a larger grain and to reduce the trap states existed in the grain boundaries to improve the electrical characteristics in polysilicon re-crystallization. Besides, high dielectric constant materials as Nd2O3 and TiO2 deposited by RF sputtering are used to replace the conventional SiO2 gate oxide in thin film transistors application. The high-k materials combined with the post rapid thermal annealing can passivate the trap states in the high-k dielectrics and the interface between the gate dielectrics and the polysilicon to improve the electrical characteristics of the polyoxides. As for the low temperature polysilicon (LTPS) application, there are still some problems existied in conventional SPC, including small grain size and more interface and trap states in the grain boundaries. Consequently, applying MIC can get larger grain size and few trap states, but may suffer metal contamination problem to increase the leakage current to degrade the electrical characteristics. Therefore, the NH3 plasma treatment is used to form stronger Si-N bonds in place of weaker Si-Si and Si-O bonds to reduce the leakage current and the trap states in the grain boundaries. The high-k materials are used to fabricate the polyoxides capacitors due to high dielectric constant to get higher capacitance density. The quality of the polyoxides can be improved combined with RTA treatment to reduce and passivate the trap states in the high-k dielectrics and polycrystalline silicon, which can form stronger bonding to improve the electrical characteristics of the polyoxides such as larger electrical breakdown field, smaller gate voltage shift and larger charge to breakdown.
Lin, Shih-Hao, and 林士豪. "The Investigation of Metal-Gate/High-k CMOSFETs、Metal-Insulator-Metal Capacitor and MONOS Non-Volatile Memory Applying High-k Dielectric Materials." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/67231215372915219498.
Full text國立清華大學
電子工程研究所
97
According to International Technology Roadmap for Semiconductor (ITRS), logic and memory devices are being continuously scaled down to reduce the area of the chip and the cost. However, traditional dielectric material SiO2 will face the physical limitation of nano device – large leakage current and device will fail. This scaling issue is a formidable challenge especially for emerging system-on-chip (SoC) integrated circuit designs in which a continuously scaling of gate dielectrics for complementary metal oxide semiconductor and tunneling oxide for non-volatile memory is needed to have high density and low operating voltage. To meet this requirement, high dielectric constant (k) materials provide the only solution since decreasing the dielectric thickness (t) degrades both the leakage current and devices performance. In recent years, logic and memory devices applying high dielectric constant (k) materials become one of the most important researches in the semiconductor industry. In this dissertation, we will investigate the application of several high-k dielectric materials for metal-gate/high-k CMOSFETs、MIM Analog-RF/DRAM Capacitors and MONOS non-volatile memory (NVM). First of all, we demonstrate low Vt of 0.12 and -0.17 V, in dual [TaN-TaN/Ir]/LaTiO n- and p-MOS at 0.63 and 0.66 nm EOT, with good 0.8 MV/cm mobility of 126 and 54 cm2/Vs. This was achieved using Ni-induced solid-phase diffusion to lower high-k interface reaction, with simple self-aligned and gate-first process, compatible with current VLSI. Next, for metal-insulator-metal (MIM) capacitors using high-k dielectric materials for Analog-RF/DRAM, we have fabricated high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal (MIM) capacitors. A low leakage current of 8x10-8 A/cm2 at 125oC was obtained with a high 38 fF/um2 capacitance density and better than ZrO2 MIM capacitors. The excellent device performance is due to the lower electric field in 9.5 nm thick TiO2/ZrO2 devices to decrease leakage current and the higher k of 58 for TiO2 than ZrO2 to preserve the high capacitance density. We also studied the stress reliability of high-k Ni/TiO2/ZrO2/TiN metal-insulator-metal capacitors under constant-voltage stress. The increasing TiO2 thickness on ZrO2 improves the 125oC leakage current, capacitance variation (delta-C/C), and the long term reliability. Finally, we also applied high-k dielectric materials for non-volatile memory. We report a novel charge-tapping-engineered flash (CTEF) non-volatile memory with very thin 5 nm Si3N4 that has a large 5.6 V initial memory window and 3.8 V 10-year extrapolated retention window at 150oC and under a fast 100 us and +16/-16 V program/erase. These were achieved using shallow- and deep -energy Si3N4-HfON trapping layers that are much better than the memory device characteristics for the similar structure without the extra 0.9 nm EOT HfON layer.
Nawaz, Muhammad. "Resistive switching characteristics in high-k dielectric thin films." Phd thesis, 2012. http://hdl.handle.net/1885/156046.
Full textZhao, Han 1982. "A study of electrical and material characteristics of III-V MOSFETs and TFETs with high-[kappa] gate dielectrics." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2184.
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"Structure of high-k thin films on Si substrate." Thesis, 2009. http://library.cuhk.edu.hk/record=b6074953.
Full textWang, Xiaofeng = Si衬底上高k介电薄膜的结构研究 / 王晓峰.
Adviser: Li Quan.
Source: Dissertation Abstracts International, Volume: 72-11, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2009.
Includes bibliographical references (leaves 103-112).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Wang, Xiaofeng = Si chen di shang gao k jie dian bo mo de jie gou yan jiu / Wang Xiaofeng.