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1
Liu, Dameng. "High-K gate oxides for future complementary metal-oxide-semiconductor transistors." Thesis, University of Cambridge, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611517.
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Tewg, Jun-Yen. "Zirconium-doped tantalum oxide high-k gate dielectric films." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/1346.
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A new high-k dielectric material, i.e., zirconium-doped tantalum oxide (Zr-doped TaOx), in the form of a sputter-deposited thin film with a thickness range of 5-100 nm, has been studied. Important applications of this new dielectric material include the gate dielectric layer for the next generation metal-oxide-semiconductor field effect transistor (MOSFET). Due to the aggressive device scaling in ultra-large-scale integrated circuitry (ULSI), the ultra-thin conventional gate oxide (SiO2) is unacceptable for many practical reasons. By replacing the SiO2 layer with a high dielectric constant material (high-k), many of the problems can be solved. In this study, a novel high-k dielectric thin film, i.e., TaOx doped with Zr, was deposited and studied. The films electrical, chemical, and structural properties were investigated experimentally. The Zr dopant concentration and the thermal treatment condition were studied with respect to gas composition, pressure, temperature, and annealing time. Interface layer formation and properties were studied with or without an inserted thin tantalum nitride (TaNx) layer. The gate electrode material influence on the dielectric properties was also investigated. Four types of gate materials, i.e., aluminum (Al), molybdenum (Mo), molybdenum nitride (MoN), and tungsten nitride (WN), were used in this study. The films were analyzed with ESCA, XRD, SIMS, and TEM. Films were made into MOS capacitors and characterized using I-V and C-V curves. Many promising results were obtained using this kind of high-k film. It is potentially applicable to future MOS devices.
3
Li, Huanglong. "First principle modelling of high-K oxide on Ge." Thesis, University of Cambridge, 2014. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.707988.
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4
Lu, Jiang. "Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology." Texas A&M University, 2005. http://hdl.handle.net/1969.1/4714.
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A novel high-k gate dielectric material, i.e., hafnium-doped tantalum oxide (Hf-doped
TaOx), has been studied for the application of the future generation metal-oxidesemiconductor
field effect transistor (MOSFET). The film's electrical, chemical, and
structural properties were investigated experimentally. The incorporation of Hf into TaOx
impacted the electrical properties. The doping process improved the effective dielectric
constant, reduced the fixed charge density, and increased the dielectric strength. The
leakage current density also decreased with the Hf doping concentration. MOS capacitors
with sub-2.0 nm equivalent oxide thickness (EOT) have been achieved with the lightly
Hf-doped TaOx. The low leakage currents and high dielectric constants of the doped films
were explained by their compositions and bond structures. The Hf-doped TaOx film is a
potential high-k gate dielectric for future MOS transistors.
A 5 ÃÂ
tantalum nitride (TaNx) interface layer has been inserted between the Hf-doped
TaOx films and the Si substrate to engineer the high-k/Si interface layer formation and
properties. The electrical characterization result shows that the insertion of a 5 ÃÂ
TaNx
between the doped TaOx films and the Si substrate decreased the film's leakage current density and improved the effective dielectric constant (keffective) value. The improvement
of these dielectric properties can be attributed to the formation of the TaOxNy interfacial
layer after high temperature O2 annealing. The main drawback of the TaNx interface layer
is the high interface density of states and hysteresis, which needs to be decreased.
Advanced metal nitride gate electrodes, e.g., tantalum nitride, molybdenum nitride,
and tungsten nitride, were investigated as the gate electrodes for atomic layer deposition
(ALD) HfO2 high-k dielectric material. Their physical and electrical properties were
affected by the post metallization annealing (PMA) treatment conditions. Work functions
of these three gate electrodes are suitable for NMOS applications after 800ðC PMA.
Metal nitrides can be used as the gate electrode materials for the HfO2 high-k film.
The novel high-k gate stack structures studied in this study are promising candidates
to replace the traditional poly-Si-SiO2 gate stack structure for the future CMOS
technology node.
5
Li, Wenmei. "CHARACTERIZATION OF HIGH-K GATE STACKS IN METAL-OXIDE-SEMICONDUCTOR CAPACITORS." NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20010202-100109.
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The purpose of this research has been to use off-line characterization techniques to establish material-specific properties of gate-stack constituents (i.e., high-k dielectric stacks and electrodes) and complete gate-stack structures. Hence, the characterization methodologies were established to evaluate high-k dielectrics at various processing levels, which, in part, determine the final characteristics of an advanced gate-stack device. Material systems that were investigated include: Al-O, Hf-Si-O, Zr-Si-O, Ti-O, Ta-O and Sr-Ti-O. Various physical and electrical characterization techniques were used to establish fundamental understandings of the materials selected, thin-film growth/deposition processes, and gate-stack structures. General conclusions for stable and unstable gate-dielectric materials have been establishedregarding the presence of a problematic interfacial layer at the Si/dielectric interface, graded dielectric layers, and the stability of gate electrodes on high-k dielectrics.The nanometer-scale chemistry of a gate-stack capacitor whose expected structure is Si/SiOxNy/Ta2O5/TiN/Al was studied by high-resolution electron-energy-loss spectroscopy in a scanning transmission electron microscope. Elemental profiles with near-atomic-level resolution for Si, Ti, N, Al, and O demonstrate that the device structure deviates drastically from the expectation and is chemically complex.It is concluded that the graded distribution of certain elements across the gate-stack capacitor completely precludes a band-structure model that assumes abrupt interfaces and chemically discrete layers. This study impacted on subsequent interpretations of flatband voltage extractions and electrical degradation following backside metallization/postmetallization annealing for capacitors whose dielectric-stack was based on Ta-O.Detailed and extensive electrical characterizations of Pt/SiOx/Sr-Ti-O/Si MOS capacitors were carried out to investigate reliability issues in a bi-layer gate dielectric. Based on these studies, models are proposed to describe the carrier transport and dielectric degradation for a Sr-Ti-O capacitor. It is concluded that conduction is dominated by Frenkel-Poole emission from mid-gap trap levels. The trap barrier height is estimated to be 1.51eV. A model based on the atomic and electronic structure of oxygen vacancies can account for the reported leakage-current characteristics. In addition, it is tentatively proposed that anode-hole injection and hole trapping control the dielectric degradation under gate injection.
6
Gomeniuk, Yu Y., A. N. Nazarov, S. Monaghan, K. Cherkaoui, E. O’Connor, I. Povey, V. Djara, and P. K. Hurley. "Electrical Properties of High-k Oxide in Pd/Al2O3/InGaAs Stack." Thesis, Sumy State University, 2012. http://essuir.sumdu.edu.ua/handle/123456789/35048.
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The paper presents the results of capacitance-voltage (C-V) characterization of metal-oxidesemiconductor
(MOS) structure, namely Pd/Al2O3/ In0.53Ga0.47As/InP. It is shown that MOS structure under
study exhibit both electron and hole trapping with permanent and temporary charge trapping contributions.
The interfacial transition layer between the high-k oxide and InGaAs has the greatest influence on
this charge trapping phenomenon.
When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35048
7
Marshall, Paul Andrew. "Liquid injection MOCVD of hafnium oxide, silicate and aluminate high-k dielectrics." Thesis, University of Liverpool, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.422113.
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8
Gao, Yong. "Deposition, stabilization and characterization of zirconium oxide and hafnium oxide thin films for high k gate dielectrics." Diss., The University of Arizona, 2004. http://hdl.handle.net/10150/290136.
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As the MOS devices continue to scale down in feature size, the gate oxide thickness is approaching the nanometer node. High leakage current densities caused by tunneling is becoming a serious problem. Replacing silicon oxide with a high kappa material as the gate dielectrics is becoming very critical. In recent years, research has been focused on a few promising candidates, such as ZrO₂, HfO₂, Al₂O₃, Ta₂O₅, and some silicates. However, unary metal oxides tend to crystallize at relatively low temperatures (less than 700°C). Crystallized films usually have a very small grain size and high leakage current due to the grain boundaries. The alternatives are high κ oxides which are single crystal or amorphous. Silicates remain amorphous at high temperatures, but have some problems such as phase separation, interface reaction, and lower κ value. In this work, we addressed the crystallization problems of zirconium oxide and hafnium oxide thin films. Both of these two thin films were deposited by DC reactive magnetron sputtering so that very dense films were deposited with little damage. A specially designed system was set up in order to have good control of the deposition process. The crystallization behavior of as-deposited amorphous ZrO₂ and HfO₂ films was studied. It was found that the films tended to have higher crystallization temperature when the films were thinner than a critical thickness of approximately 5 nm. However, it was still well below 900°C. The crystallization temperature was significantly increased by sandwiching the high kappa oxide layer between two silica layers. Ultra thin HfO₂ films of 5nm thickness remained amorphous up to 900°C. This is the highest crystallization temperature which has been reported. The mechanisms for this effect are proposed. Electrical properties of these high kappa dielectric films were also studied. It was found that ultra thin amorphous HfO₂ and ZrO₂ films had superior electrical properties to crystalline films. The leakage current density of ultra thin amorphous films was at least two orders of magnitude lower than that of crystallized films. Amorphous films also showed much less hysteresis in the capacitance-voltage curve than uncapped crystallized films. The mechanisms for the electrical property differences between ultra thin crystalline and amorphous films were studied. Due to successful control of the low dielectric interfacial layer thickness, an effective oxide thickness of 1.2 and 1.4 nm was obtained for HfO₂ and ZrO₂ films, respectively.
9
Tse, Koon-Yiu. "High-K gate oxides and metal gate materials for future complementary metal-oxide-semiconductor field-effect transistors." Thesis, University of Cambridge, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.611979.
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Jeon, Yongjoo. "High-k gate dielectric for 100 nm MOSFET application /." Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004296.
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Ren, Fang. "Development of Aluminum Oxide (Al2O3) Gate Dielectric Protein Biosensor under Physiologic Buffer." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1331128526.
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Yan, Liang. "Characterisation of gate oxide and high-k dielectric reliability in strained si and sige cmos transistors." Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506541.
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13
Kiani, Ahmed. "Analysis of metal oxide thin film transistors with high-k dielectrics and source/drain contact metals." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648586.
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Woods, Keenan. "Amorphous Metal Oxide Thin Films from Aqueous Precursors: New Routes to High-κ Dielectrics, Impact of Annealing Atmosphere Humidity, and Elucidation of Non-uniform Composition Profiles." Thesis, University of Oregon, 2018. http://hdl.handle.net/1794/23173.
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Metal oxide thin films serve as critical components in many modern technologies, including microelectronic devices. Industrial state-of-the-art production utilizes vapor-phase techniques to make high-quality (dense, smooth, uniform) thin film materials. However, vapor-phase techniques require large energy inputs and expensive equipment and precursors. Solution-phase routes to metal oxides have attracted great interest as cost-effective alternatives to vapor-phase methods and also offer the potential of large-area coverage, facile control of metal composition, and low-temperature processing.
Solution deposition has previously been dominated by sol-gel routes, which utilize organic ligands, additives, and/or solvents. However, sol-gel films are often porous and contain residual carbon impurities, which can negatively impact device properties. All-inorganic aqueous routes produce dense, ultrasmooth films without carbon impurities, but the mechanisms involved in converting aqueous precursors to metal oxides are virtually unexplored. Understanding these mechanisms and the parameters that influence them is critical for widespread use of aqueous approaches to prepare microelectronic components. Additionally, understanding (and controlling) density and composition inhomogeneities is important for optimizing electronic properties. An overview of deposition approaches and the challenges facing aqueous routes are presented in Chapter I. A summary of thin film characterization techniques central to this work is given in Chapter II.
This dissertation contributes to the field of solution-phase deposition by focusing on three areas. First, an all-inorganic aqueous route to high-κ metal oxide dielectrics is developed for two ternary systems. Chapters III and IV detail the film formation chemistry and film properties of lanthanum zirconium oxide (LZO) and zirconium aluminum oxide (ZAO), respectively. The functionality of these dielectrics as device components is also demonstrated. Second, the impact of steam annealing on the evolution of aqueous-derived films is reported. Chapter V demonstrates that steam annealing lowers processing temperatures by effectively reducing residual counterion content, improving film stability with respect to water absorption, and enhancing dielectric properties of LZO films. Third, density and composition inhomogeneities in aqueous-derived films are investigated. Chapters VI and VII examine density inhomogeneities in single- and multi-metal component thin films, respectively, and show that these density inhomogeneities are related to inhomogeneous metal component distributions.
This dissertation includes previously published coauthored material.
15
Gaddipati, Surendra. "Characterization of HfO2 Films for Flash Memory Applications." Scholar Commons, 2004. https://scholarcommons.usf.edu/etd/1040.
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The scaling of integrated circuits requires the use of alternative dielectric materials as the replacement for silicon dioxide in the submicron devices. The scaling limit for silicon dioxide used in MOSFETs is 1.2nm and the Oxide Nitride Oxide (ONO) stack used in flash memory applications is 13.0nm. The use of alternative dielectrics with high- κ value will alleviate the problem of charge retention and also would help to decrease the programming voltage in case of flash memory cells.
Many alternative high- κ dielectric materials such as TaO2, TiO2, Al2O3 etc., have been examined for this purpose previously. Recently the metal oxides such as ZrO2 and HfO2 have been found to be viable replacements for the existing oxide. The high- κ value along with high bandgap motivates this replacement. A complete modeling of the reactively sputtered HfO2 films in the thickness range of 294Å to 480Å is attempted using the data obtained by one of the group members at the Sharp Laboratories of America, Inc.
The IV and CV data is used to characterize the material properties and conduction mechanism in HfO2 films used as a control dielectric. The slope of the Poole-Frenkel plot is close to the theoretical value in the intermediate region however it starts to deviate at high field regions. Temperature dependent data also suggests that there are two types of vii traps active in the intermediate and high field regions. However the origin of these traps is not known. Temperature dependent data indicates that there is a rapid increase in the leakage current at elevated temperatures in the high field region further suggesting that the charge retention capability of the device would be adversely affected under such conditions.
16
Rossi, Leonardo. "Flexible oxide thin film transistors: fabrication and photoresponse." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14542/.
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Gli ossidi amorfi semiconduttori (AOS) sono nuovi candidati per l’elettronica flessibile e su grandi aree: grazie ai loro legami prevalentemente ionici hanno una mobilità relativamente alta (µ > 10cm^2/Vs) anche nella fase amorfa. Transistor a film sottile (TFT) basati sugli AOS saranno quindi più performanti di tecnologie a base di a-Si e più economici di quelle a base di silicio
policristallino. Essendo amorfi, possono essere depositati a basse temperature e su substrati polimerici, caratteristica chiave per l’elettronica flessibile e su grandi aree. Per questa tesi, diversi TFT sono stati fabbricati e caratterizzati nei laboratori del CENIMAT all’Università Nova di Lisbona sotto la supervisione del Prof. P. Barquinha. Questi dispositivi sono composti di contatti in molibdeno, un canale semiconduttivo di ossido di zinco, gallio e indio (IGZO) e un dielettrico composto da 7 strati alternati di SiO2 e SiO2+Ta2O5. Tutti i dispositivi sono stati depositati mediante sputtering su sostrati flessibili (fogli di PEN). Le misure tensione-corrente mostrano che i dispositivi mantengono alte mobilità (decine di 10cm^2/Vs) anche quando fabbricati a temperature inferiori a 200°C. Si è analizzato il funzionamento dei dispositivi come fototransistor rilevando la risposta alla luce ultravioletta e in particolare la loro responsività e spostamento della tensione di soglia in funzione della lunghezza d’onda incidente. Questi risultati consentono di formulare ipotesi sul comportamento dei dispositivi alla scala microscopica. In particolare, indicano che i) la mobilità del canale non è influenzata dall’illuminazione, ii) sia l'IGZO sia il Ta2O5 contribuiscono al processo di fotoconduttività e iii) il processo di fotogenerazione non è adiabatico. La tesi contiene inoltre una descrizione del processo di ricombinazione e presenta un’applicazione pratica di tali dispositivi in un circuito per RFID. Infine, esplora la possibilità di migliorarne la flessibilità e le prestazioni.
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Khan, Ngwashi Divine. "An investigation of the performance and stability of zinc oxide thin-film transistors and the role of high-k dielectrics." Thesis, De Montfort University, 2010. http://hdl.handle.net/2086/4398.
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Transparent oxide semiconducting films have continued to receive considerable attention, from a fundamental and application-based point of view, primarily because of their useful fundamental properties. Of particular interest is zinc oxide (ZnO), an n-type semiconductor that exhibits excellent optical, electrical, catalytic and gas-sensing properties, and has many applications in various fields. In this work, thin film transistor (TFT) arrays based on ZnO have been prepared by reactive radio frequency (RF) magnetron sputtering. Prior to the TFT fabrication, ZnO layers were sputtered on to glass and silicon substrates, and the deposition parameters optimised for electrical resistivities suitable for TFT applications. The sputtering process was carried out at room temperature with no intentional heating. The aim of this work is to prepare ZnO thin films with stable semiconducting electrical properties to be used as the active channel in TFTs; and to understand the role of intrinsic point defects in device performance and stability. The effect of oxygen (O2) adsorption on TFT device characteristics is also investigated. The structural quality of the material (defect type and concentration), electrical and optical properties (transmission/absorption) of semiconductor materials are usually closely correlated. Using the Vienna ab-initio simulation package (VASP), it is predicted that O2 adsorption may influence film transport properties only within a few atomic layers beneath the adsorption site. These findings were exploited to deposit thin films that are relatively stable in atmospheric ambient with improved TFT applications. TFTs incorporating the optimised layer were fabricated and demonstrated very impressive performance metrics, with effective channel mobilities as high as 30 cm2/V-1s-1, on-off current ratios of 107 and sub-threshold slopes of 0.9 – 3.2 V/dec. These were found to be dependent on film thickness (~15 – 60 nm) and the underlying dielectric (silicon dioxide (SiO2), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3) and hafnium oxide (HfO2)). In this work, prior to sputtering the ZnO layer (using a ZnO target of 99.999 % purity), the sputtering chamber was evacuated to a base pressure ~4 x 10-6 Torr. Oxygen (O2) and argon (Ar) gas (with O2/Ar ratio of varying proportions) were then pumped into the chamber and the deposition process optimised by varying the RF power between 25 and 500 W and the O2/Ar ratio between 0.010 to 0.375. A two-level factorial design technique was implemented to test specific parameter combinations (i.e. RF power and O2/Ar ratio) and then statistical analysis was utilised to map out the responses. The ZnO films were sputtered on glass and silicon substrates for transparency and resistivity measurements, and TFT fabrication respectively. For TFT device fabrication, ZnO films were deposited onto thermally-grown silicon dioxide (SiO2) or a high-k dielectric layer (HfO2, Gd2O3 and Y2O3) deposited by a metal-organic chemical deposition (MOCVD) process. Also, by using ab initio simulation as implemented in the “Vienna ab initio simulation package (VASP)”, the role of oxygen adsorption on the electrical stability of ZnO thin film is also investigated. The results indicate that O2 adsorption on ZnO layers could modify both the electronic density of states in the vicinity of the Fermi level and the band gap of the film. This study is complemented by studying the effects of low temperature annealing in air on the properties of ZnO films. It is speculated that O2 adsorption/desorption at low temperatures (150 – 350 0C) induces variations in the electrical resistance, band gap and Urbach energy of the film, consistent with the trends predicted from DFT results.
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Kumar, Pushpendra. "Impact of 14/28nm FDSOI high-k metal gate stack processes on reliability and electrostatic control through combined electrical and physicochemical characterization techniques." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT114/document.
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Cette thèse concerne l’étude des procédés de fabrication des grilles HKMG des technologies FDSOI 14 et 28 nm sur les performances électriques des transistors MOS. Elle a porté spécifiquement sur l'aspect fiabilité et la maîtrise du travail de sortie effectif (WFeff), au travers de la diffusion des additifs comme le lanthane (La) et l’aluminium (Al). Ce travail combine des techniques de caractérisation électriques et physico-chimiques et leur développement. L'effet de l'incorporation de ces additifs sur la fiabilité et la durée de vie du dispositif a été étudié. Le lanthane dégrade les performances de claquage TDDB et de dérives suite aux tests aux tensions négatives. L’introduction d’aluminium améliore le claquage TDDB, mais dégrade les dérives aux tensions positives. Ces comportements ont été reliés à des mécanismes physiques. Par ailleurs, la diffusion de ces additifs dans l’empilement de grille a été étudiée pour différents matériaux high-k en fonction de la température et de la durée de recuit de diffusion. Les doses d’additifs ont pu être ainsi mesurées, comparées et corrélées au décalage de travail de sortie effectif de grille. On a également étudié, les influences des paramètres du procédé de dépôt de grille TiN sur leur microstructure et les propriétés électriques du dispositif, identifiant certaines conditions à même de réduire la taille de grain ou la dispersion d’orientation cristalline. Toutefois, les modulations obtenues sur le travail de sortie effectif de grille dépendent plus du ratio Ti/N, suggérant un changement du dipôle à l'interface SiO2 / high-k. Enfin, une technique éprouvée de mesure de spectroscopie à rayon X sous tension a pu être mise en place grâce des dispositifs spécifiques et une méthodologie adaptée. Elle permet de mesurer les positions relatives des bandes d’énergie à l'intérieur de l’empilement de grille. Cette technique a démontré que le décalage du travail de sortie effectif induits par des additifs (La or Al) ou par des variations d'épaisseur de grille métallique TiN provient de modifications du dipôle à l'interface SiO2/ high-kThis Ph.D. thesis is focused on the impact of the 14 and 28 nm FDSOI technologies HKMG stack processes on the electrical performance of MOS transistors. It concerns specifically the reliability aspect and the engineering of effective workfunction (WFeff ), through diffusion of lanthanum (La) and aluminum (Al) additives. This work combines electrical and physicochemical characterization techniques, and their development. The impact of La and Al incorporation, in the MOS gate stack, on reliability and device lifetime has been studied. La addition has a significant negative impact on device lifetime related to both NBTI and TDDB degradations. Addition of Al has a significant negative impact on lifetime related to PBTI, but on the contrary improves the lifetime for TDDB degradation. These impacts on device lifetime have been well correlated to the material changes inside the gate oxides. Moreover, diffusion of these additives into the HKMG stack with annealing temperature and time has been studied on different high-k materials. The diffused dose has been compared with the resulting shift in effective workfunction (WFeff), evidencing clear correlation. In addition, impact of TiN metal gate RF-PVD parameters on its crystal size and orientation, and device electrical properties has been studied. XRD technique has been used to obtain the crystal size and orientation information. These properties are significantly modulated by TiN process, with a low grain size and a unique crystal orientation obtained in some conditions. However, the WFeff modulations are rather correlated to the Ti/N ratio change, suggesting a change in the dipole at SiO2/high-k interface. Lastly, using specific test structures and a new test methodology, a robust and accurate XPS under bias technique has been developed to determine the relative band energy positions inside the HKMG stack of MOS devices. Using this technique, we demonstrated that WFeff shift induced by La and Al or by variations in gate thickness originates due to modifications of the dipole at SiO2/high-k interface
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Benoist, Antoine. "Pre and post breakdwon modeling of high-k dielectrics regarding antifuse and OxRAM non-volatile memories." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI007.
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Les mémoires non volatiles intégrées représentent une part importante du marché des semi-conducteurs. Bien qu'il s'adresse à de nombreuses applications différentes, ce type de mémoire fait face à des problèmes pour poursuivre la réduction continue de la résolution des technologies CMOS. En effet, l'introduction récente de high-k et de métal pour la grille des transistors menace la compétitivité de la solution Flash. En conséquence, de nombreuses solutions émergentes sont étudiées. L'Antifuse dans le cadre des mémoires OTP est utilisée pour l'identification de puces, la configuration de circuits, la réparation de système ou le stockage de données sécurisées. La programmation Antifuse repose sur la dégradation de l'oxyde de grille de son condensateur sous haute tension. Des travaux antérieurs ont déjà apporté quelques connaissances sur les mécanismes physiques impliqués sur des technologies à oxyde de grille SiO2. De nouveaux défis découlent de l'introduction des nouveaux matériaux de grille. Un examen complet est nécessaire sur les mécanismes de dégradation des oxydes impliqués dans la programmation Antifuse. L'utilisation intensive de la haute tension suggère également d'étendre notre connaissance sur la fiabilité dans cette gamme de tension. Les états pré et post-claquage de l'oxyde de grille sous des mécanismes à haute tension sont donc étudiés dans ce manuscrit se concentrant sur les technologies CMOS les plus avancées. Une loi en puissance type TDDB a été étendue vers les hautes tensions pour être utilisée comme un modèle de temps de programmation Antifuse. L'extension de la fiabilité TDDB nous donne également un élément clé pour modéliser la durée de vie du transistor de sélection. Des paramètres de programmation tels que l'amplitude de la tension, la compliance du courant ou la température sont également étudiés et leur impact sur le rendement en courant de lecture est abordé. Cette étude nous permet de rétrécir agressivement la surface globale de la cellule sans perte de performance ni de dégradation de la fiabilité. Un processus de caractérisation Antifuse est proposé pour être retravaillé et un modèle de programmation de tension-température-dépendante est inventé. Ce manuscrit a également mis l'accent sur la modélisation de courant de cellule programmée comme la fuite d’un oxyde de grille post-claquage. Un modèle compact MOSFET dégradé est proposé et comparé à l'état de l’art. Un bon accord est trouvé pour s'adapter à la large gamme de caractérisations I (V) de la cellule programmée. L'activation de ce modèle dans un environnement de design nous a permis de simuler la dispersion des distributions de courants de cellules programmées au niveau de la taille du produit à l'aide de runs Monte-Carlo. Enfin, cette thèse s'achève autour d'une étude d'investigation OxRAM comme une solution émergente. En combinant le dispositif Antifuse avec le mécanisme de commutation résistif de l'OxRAM, une solution hybride est proposée en perspectiveEmbedded Non Volatile Memories represent a significant part of the semiconductor market. While it addresses many different applications, this type of memory faces issues to keep the CMOS scaling down roadmap. Indeed, the recent introduction of high-k and metal for the CMOS gate is threatening the Flash’s competitiveness. As a consequence many emerging solutions are being. The Antifuse as part of the OTP memories is fully CMOS compliant, Antifuse memories are used for Chip ID, chip configuration, system repairing or secured data storage to say the least. The Antifuse programming relies on the gate oxide breakdown of its capacitor under high voltage. Previous work already brought some knowledge about the physical mechanisms involved but mainly on SiO2 gate oxide technologies. New challenges arise from the introduction of the new gate materials. A full review is needed about the oxide breakdown mechanisms involved in the Antifuse programming. The extensive use of high voltage also suggests to extend our knowledge about reliability within this voltage range. Pre and post gate oxide breakdown under high voltage mechanisms are then deeply investigated in this manuscript focusing on the most advanced CMOS technologies. Fowler Nordheim Tunneling has been confirmed as the main mechanism responsible for the gate oxide leakage conduction under high voltage during the wearout phase even-though defect contribution has been evidenced to mainly contribute under low voltage , e.g. the virgin Antifuse leakage current. A TDDB based power law has been extended toward high voltage to be used as a robust Antifuse programming time model. Extending the TDDB reliability under high electric field also gives us key element to model the selection MOSFET time to failure. Programming parameters such as voltage amplitude, current compliance or temperature are also investigated and their impact on the Read Current Yield are tackled. This study allows us to aggressively shrink the bitcell overall area without losing performance nor degrading the reliability. This study also reveals a worst case scenario for the programming parameters when temperature is very low. As a consequence, the early Antifuse characterization process is proposed to be rework and a programming voltage-temperature-dependent solution is invented. This manuscript also focused on the Antifuse programmed cell current modeling as gate oxide post-breakdown conduction. A remaining MOSFET compact model is proposed and compared to the state of the art. Good agreement is found to fit the wide range of read current. Enabling this model within a CAD environment has allowed us to simulate the Read Current Yield dispersion at product size level using Monte-Carlo runs. Finally, this thesis wraps up around an OxRAM investigation study as a serious emerging eNVM solution. Combining the Antifuse device with the resistive switching mechanism of the OxRAM, a hybrid solution is proposed as a perspective
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Richter, Jan Hinnerk. "Electronic Properties of Metal Oxide Films Studied by Core Level Spectroscopy." Doctoral thesis, Uppsala : Uppsala universitet, Fakultetsövergripande enheter, Acta Universitatis Upsaliensis, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-7180.
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Koslowski, Nico [Verfasser], Jörg J. [Akademischer Betreuer] Schneider, and Barbara [Akademischer Betreuer] Albert. "Approaching metal oxide high-k dielectrics and semiconductors by solution-processing of molecular precursors / Nico Koslowski ; Jörg J. Schneider, Barbara Albert." Darmstadt : Universitäts- und Landesbibliothek, 2021. http://d-nb.info/1241741581/34.
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Cai, Wei. "Ballistic Electron Emission Microscopy and Internal Photoemission Study on Metal Bi-layer/Oxide/Si, High-k Oxide/Si, and “End-on” Metal Contacts to Vertical Si Nanowires." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1269521615.
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Lie, Fee Li. "Interface Formation Between High Dielectric Permittivity Films and III-V Compound Semiconductors using HF Chemistries and Atomic Layer Deposition." Diss., The University of Arizona, 2011. http://hdl.handle.net/10150/204301.
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In-based III-V compound semiconductors have higher electron mobilities than either Si or Ge and direct band gaps. These properties could enable the fabrication of low power, high-speed n-channel metal oxide semiconductor field effect transistors (MOSFETs) and optoelectronics combining MOS technology with photonics. Since thermal and native oxides formed on III-V surfaces exhibit large current leakage and high densities of trap states, a key to incorporating these materials into advanced devices is the development of processing steps that form stable interfaces with dielectric layers. In this thesis, a processing flow consisting of native oxide removal using HF chemistries and deposition of high dielectric permittivity films using atomic layer deposition was investigated. Understanding the reaction mechanisms of these processes could provide the means of controlling composition and structure, yielding a desired electronic behavior. Quantitative X-ray photoelectron spectroscopy analysis of surfaces was coupled with electrical measurements on MOS capacitors of the interface quality in order to understand the nature of high-k/III-V interface defects and their repair. Ex situ liquid phase HF etching removed InSb, InAs, and InGaAs(100) native oxides and produced an Sb- or As-enriched surface, which oxidized when exposed to air. A 5 to 22 °A thick As- and Sb-rich residual oxide was left on the surface after etching and < 5 min of air exposure. The results showed that group V enrichment originated from the reduction of group V oxides by protons in the solution and the preferential reaction of HF with the group III atom of the substrate. A sub-atmospheric in situ gas phase HF/H2O process removed native oxide from InSb, InAs, and InGaAs(100) surfaces, producing an In or Ga fluoride-rich sacrificial layer. A 50 to 90% oxide removal was achieved and a 10 to 25 °A-thick overlayer consisting of mainly In and Ga fluorides was produced. The composition and morphology of the sacrificial layer were controlled by the partial pressure of H2O as well as the ratio of HF to H2O used. Water played a critical role in the process by directly participating in the etching reaction and promoting the desorption of fluoride etching products. Accumulation of thick fluoride layer at high HF to water partial pressure ratios prevented adsorption and diffusion of etchant to the buried residual oxide. When oxide was removed, HF preferentially reacted with In or Ga atoms from the substrate, enriching the surface with group III fluorides and producing approximately one monolayer of elemental group V atoms at the interface. Interface reactions occurred during atomic layer deposition of Al2O3, in which trimethylaluminum (TMA) removed surface oxides and fluorides. Chemically sharp InSb/Al2O3 and InGaAs/Al2O3 interfaces were achieved for gas phase HF-etched InSb and liquid phase HF-etched InGaAs. A ligand transfer mechanism promotes nucleation of Al2O3 and removal of III-V atoms from the sacrificial oxide and fluoride layers as volatile trimethyl indium, gallium, arsenic, and antimony. These reactions have been explained by the relative bond strength of surface and precursor metal atoms with O and F. Interaction of a InSb(100) surface with TiCl4 as a model for metal halide ALD precursors showed that similar ligand transfer reactions occured. Adsorbed chlorine from the dissociative adsorption of TiCl4 on the InSb surface at elevated temperature, however, preferentially etched In atoms from the substrate and produced a roughened surface. The quality of InGaAs/Al2O3 interfaces prepared by solvent cleaning and liquid phase HF were assesed electrically using capacitance-voltage and conductance measurements. Surface recombination velocity (SRV) values were extracted from the measurements to represent the net effect of interface defects, which includes defect density and capture cross section. The InGaAs/Al2O3 interface prepared by solvent cleaning consisted of interfacial native oxides while that etched in liquid phase HF consisted of submonolayer arsenic oxide. The two chemically contrasting interfaces, however, gave similar SRV values of 34.4±3.7 and 28.9±13.4 cm/s for native oxide and liquid phase HF prepared samples, respectively. This suggests that the presence or absence of oxides was not the only determining factor. Post Al2O3 deposition annealing in forming gas and NH3 ambient significantly improved the electrical quality for both surfaces, as shown by SRV values between 1 to 4 cm/s which is comparable to that of an ideal H-terminated Si surface. XPS analysis showed that the contribution from elemental As and Ga2O3 at the interface of both surfaces increased after annealing in forming gas and NH3, likely due to thermal or hydrogen-induced reaction between interfacial As oxide and Ga atoms in the substrate. There was no correlation between the atomic coverages of interfacial elemental As and oxides to the SRV values. High activity defects at III-V/Al2O3 interfaces are associated with interfacial dangling bonds which were passivated thermally and chemically by annealing in forming gas and NH3.
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Hossain, Md Tashfin Zayed. "Electrical characteristics of gallium nitride and silicon based metal-oxide-semiconductor (MOS) capacitors." Diss., Kansas State University, 2013. http://hdl.handle.net/2097/16942.
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Doctor of PhilosophyDepartment of Chemical Engineering
James H. Edgar
The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.
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Han, Lei. "Investigation of Gate Dielectric Materials and Dielectric/Silicon Interfaces for Metal Oxide Semiconductor Devices." UKnowledge, 2015. http://uknowledge.uky.edu/ece_etds/69.
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The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.
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Henkel, Karsten. "Electrical investigations on praseodymium oxide aluminum oxynitride containing metal insulator semiconductor stacks and on metal ferroelectric insulator semiconductor structures consisting of poly(vinylidene fluoride trifluoroethylene) /." Aachen : Shaker, 2009. http://d-nb.info/995916187/04.
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Sahin, Dondu. "Structural And Electrical Properties Of Flash Memory Cells With Hfo2 Tunnel Oxide And With/without Nanocrystals." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/3/12610766/index.pdf.
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In this study, flash memory cells with high-k dielectric HfO2 as tunnel oxide and group IV (Si, Ge) nanocrystals were fabricated and tested. The device structure was grown by magnetron sputtering deposition method and analyzed by various diagnostic techniques such as X-ray Photoelectron Spectroscopy (XPS) and Raman spectroscopy. The use of HfO2 tunnel oxide dielectric with high permittivity constant was one of the main purposes of this study. The ultimate aim was to investigate the use of Si and Ge nanocrystals together with HfO2 tunnel oxide in the memory elements. Interface structure of the fabricated devices was studied by XPS spectroscopy. A depth profile analysis was performed with XPS. Nanocrystal formations were verified using Raman spectroscopy technique. The final part of the study includes electrical characterization of memory devices fabricated using Si and Ge floating gate. C-V (Capacitance Voltage) and G-V (Conductance-Voltage) measurements and charge storage behaviour based on C-V measurements were performed. For comparison, structure of Si and Ge layers either in thin film or in the nanocrystal form were studied. A comparison of the C-V characteristics of these two structures revealed that the memory device with thin films do not confine charge carriers under the gate electrode as should be expected for a continuous film. On the other hand, the device with nanocrystals exhibited better memory behavior as a result of better confinement in the isolated nanocrystals. Trace amount of oxygen was found to be enough to oxidize Ge nanocrystals as confirmed by the Raman measurements. The charge storage capability is weakened in these samples as a result of Ge oxidation. In general, this work has demonstrated that high-k dielectric HfO2 and group IV nanocrystals can be used in the new generation MOS based memory elements. The operation of the memory elements are highly dependent on the material and device structures, which are determined by the process conditions.
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Boujamaa, Rachid. "Caractérisations physico-chimiques et électriques d’empilements de couches d’oxyde à forte permittivité (high-k) / grille métallique pour l’ajustement du travail effectif de la grille : application aux nouvelles générations de transistors." Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT100.
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Cette thèse s'inscrit dans le cadre du développement des technologies CMOS 32/28nm chez STMicroelectronics. Elle porte sur l'étude d'empilements de grille métal/diélectrique high-k élaborés selon une stratégie d'intégration Gate First, où le couple TiN/HfSiON est introduit avec une couche interfaciale SiON et une encapsulation de la grille TiN par du polysilicium. Cette étude s'est principalement focalisée sur l'analyse des interactions entre les différentes couches constituant les empilements, en particulier des additifs lanthane et aluminium, employés pour moduler la tension de seuil Vth des transistors NMOS et PMOS respectivement. Les analyses physico-chimiques réalisées au cours de ces travaux ont permis de mettre en évidence la diffusion en profondeur des éléments La et Al à travers le diélectrique de grille HfSiON sous l'effet du recuit d'activation des dopants à 1065°C. Les résultats obtenus ont montré que ce processus de diffusion entraine une réaction du lanthane et de l'aluminium avec la couche interfaciale de SiON pour former un silicate stable La(ou Al)SiO au profit de la couche de SiON. L'analyse des propriétés électrique des structures MOS a permis de révéler que la présence d'atomes La ou Al proximité de l'interface HfSiON/SiON conduit à la présence d'un dipôle généré à cette interface, qui a pour effet de décaler le travail de sortie effectif de la grille métalliqueThis thesis is part of the development of CMOS technologies 32/28nm STMicroelectronics. It focuses on the study of stacks of metal / high-k dielectric prepared by an integration strategy Gate First , where the couple TiN / HfSiON gate is introduced with an interfacial layer SiON and encapsulation of TiN gate polysilicon by . The study was mainly focused on the analysis of interactions between the various layers forming the stacks , in particular lanthanum and aluminum additives , used for modulating the threshold voltage Vth of the PMOS and NMOS transistors respectively . The physico-chemical analyzes in this work helped to highlight the depth distribution of the elements La and Al through the HfSiON gate dielectric under the influence of dopant activation annealing at 1065 ° C. The results obtained showed that this diffusion process causes a reaction of lanthanum and aluminum with the interfacial layer of SiON to form a stable silicate La ( or Al ) SiO benefit of the SiON layer . The analysis of electrical properties of MOS structures revealed that the presence of the atoms near the Al or HfSiON / SiON interface leads to the presence of a dipole generated at this interface , which has the effect of shifting actual output work of the metal gate
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Fratelli, Ilaria. "Flexible oxide thin film transistors: device fabrication and kelvin probe force microscopy analysis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13538/.
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I transistor a film sottile basati su ossidi amorfi semiconduttori sono ottimi candidati nell'ambito dell'elettronica su larga scala. Al contrario delle tecnologie basate su a-Si:H a poly-Si, gli AOS presentano un'elevata mobilità elettrica (m > 10 cm^2/ Vs) nonostante la struttura amorfa. Inoltre, la possibilità di depositare AOS a basse temperature e su substrati polimerici, permette il loro impiego nel campo dell'elettronica flessibile.
Al fine di migliorare questa tecnologia, numerosi TFT basati su AOS sono stati fabbricati durante 4 mesi di attività all'Università Nova di Lisbona. Tutti i transistor presentano un canale formato da a-GIZO, mentre il dielettrico è stato realizzato con due materiali differenti: Parylene (organico) e 7 strati alternati di SiO2
e SiO2 + Ta2O5. I dispositivi sono stati realizzati su substrati
flessibili sviluppando una nuova tecnica per la laminazione e la delaminazione di fogli di PEN su supporto rigido. L'ottimizzazione del processo di fabbricazione ha permesso la realizzazione
di dispositivi che presentano caratteristiche paragonabili a quelle previste per TFT costruiti su substrati rigidi (m = 35.7 cm^2/Vs; VON = -0.10 V; S = 0.084 V/dec).
Al Dipartimento di Fisica dell'UNIBO, l'utilizzo del KPFM ha permesso lo studio a livello microscopico delle prestazioni presentate dai dispositivi analizzati. Grazie a questa tecnica di indagine, è stato possibile analizzare l'impatto delle resistenze di contatto sui dispositivi meno performanti e identificare l'esistenza di cariche intrappolate nei TFT basati su Parylene.
Gli ottimi risultati ottenuti dall'analisi KPFM suggeriscono un futuro impiego di questa tecnica per lo studio del legame tra stress meccanico e degradazione elettrica dei dispositivi. Infatti, la comprensione dei fenomeni microscopici dovuti alla deformazione strutturale sarà un passaggio indispensabile per lo sviluppo dell'elettronica flessibile.
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Soussou, Assawer. "Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT018/document.
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L'introduction du SiGe dans les pMOS (Bulk et FDSOI) exige un bon contrôle de la tension de seuil (VT). Ceci nécessite une extraction précise des paramètres électriques ainsi qu'une compréhension des effets électriques du Ge dans de tels dispositifs. Dans cette thèse, nous avons d'abord proposé des méthodes pour une identification précise des paramètres électriques du « gate stack »: VT, la tension de bande plate (VFB) et l'épaisseur équivalente d'oxyde (EOT). Ces méthodes ont été validées avec des simulations Poisson-Schrödinger (PS) et appliquées avec succès aux mesures. Dans un second temps, nous avons étudié les effets électriques du Ge sur les paramètres du « gate stack » des pMOS. La comparaison des caractérisations électriques (C-V) avec les simulations PS a montré un décalage supplémentaire du travail de sortie effectif qui croit avec le Ge. Des caractérisations STEM, EELS et SIMS ont prouvé que ce décalage est due à la présence de dipôles à l'interface SiGe/oxydeMaintaining good threshold voltage (VT) centering is a paramount challenge for CMOS technology. The SiGe introduction in bulk and FDSOI pFETs requires VT control for such devices. To this end, we have to extract accurately electrical parameters and to understand Ge integration effects in SiGe based pFETs. In this thesis, first, we have proposed extraction methods to determine VT, flat band voltage (VFB) and equivalent oxide thickness (EOT) parameters in bulk and FDSOI transistors. The extraction methods have been validated via Poisson-Schrodinger (PS) simulations and successfully applied to measurements. Second, we have highlighted and explained electric effects of Ge on pMOS gate stack parameters. Electrical characterizations compared with PS simulations have evidenced an additional effective work function increase, induced by Ge, related to interfacial dipoles. STEM, EELS and SIMS characterizations have demonstrated that dipoles are located at SiGe/IL interface
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Spisni, Giacomo. "Radiation-sensitive OXide semiconductor Field Effect Transistor (ROXFET): a novel thin-film device for real-time and remote ionizing radiation detection." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/24394/.
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Nowadays, ionizing radiation detectors find application in a wide range of contexts, spanning from industry to healthcare and security. In this background, the next generation of ionizing radiation sensors require devices that are accurate, light-weight, relatively inexpensive and capable to be read-out in real-time and remotely. In recent years, research groups at the University of Bologna and the NOVA University of Lisbon (Portugal) have developed Radiation-sensitive OXide-semiconductor Field-Effect Transistors (ROXFET) to be employed as fast, real-time x-ray dosimetry detection systems. The ROXFET operation relies on the principle that, upon exposure to radiation, excitons are generated in the dielectric and separated into hole and electron charge carriers. While electrons are able to diffuse out of the dielectric layer, hole charges get trapped and contribute to the field-effect in the semiconductor channel. Macroscopically, such contribution is observable as a shift in transistor threshold voltage toward negative values, which turns out to be proportional to the absorbed radiation dose. In laboratory tests, ROXFET devices proved to be sensitive in a wide energy range and capable of providing reliable information about their radiation exposure history. Furthermore, the design of ROXFET can be integrated on a flexible substrate and read in real-time as a passive radiofrequency tag. Aim of this thesis work was to contribute to the development of the ROXFET technology. To this end, I carried out multiple characterization tests on recently fabricated samples, revealing how they outperformed previously observed radiation sensitivities. Later on, I worked in a clean-room facility to fabricate new ROXFET experimental samples by leveraging the knowledge acquired from previous observations.
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Tanaka, N., H. Iwai, K. Kakushima, E. Okunishi, J. Yamasaki, and S. Inamoto. "Annealing effects on a high-k lanthanum oxide film on Si (001) analyzed by aberration-corrected transmission electron microscopy/scanning transmission electron microscopy and electron energy loss spectroscopy." American Institute of Physics, 2010. http://hdl.handle.net/2237/14189.
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Albertin, Kátia Franklin. "Estudo de camadas dielétricas para aplicação em capacitores MOS." Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-08012008-144158/.
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Foram estudados filmes de oxinitreto de silício obtidos por PECVD à 320°C, a partir da mistura gasosa de N2O+SiH4+He, com diferentes valores de pressão e potência de deposição com o objetivo de produzir boa qualidade de interface deste material com o Si e de obter uma baixa densidade de carga efetiva visando a aplicação desses filmes em dispositivos semicondutores MOS. Os resultados mostraram que com uma pressão de deposição de 0,160 mbar e potências menores que 125 W/cm2 é possível obter um valor de densidade de estados de interface (Dit) de 4x1010 eV-1.cm-2, campo elétrico de ruptura (Ebd) de 13 MV/cm, valores comparáveis ao SiO2 térmico e uma densidade de carga efetiva (Nss) de 4x1011 cm-2. Segundo resultados experimentais esse valor de Nss é o mínimo possível que se pode atingir com a limpeza química utilizada em nosso laboratório. Pode-se dizer que estes são resultados bastante interessantes considerando que se trata de um material obtido por PECVD à baixa temperatura, porém viável para aplicação em dispositivos MOS. Iniciando os estudos com dielétricos de maiores valores de constante dielétrica optamos por estudar filmes de TiOx (k=40-100), obtidos por sputtering reativo, a partir da mistura gasosa de Ar+O2 e utilizando alvo de Ti. Foram fabricados capacitores MOS com estes filmes e obteve-se valores de constante dielétrica que variaram de 40-160. Porém esses materiais ainda apresentavam valores apreciáveis de corrente de fuga que foram minimizadas em ordens de grandeza quando utilizados dielétricos de dupla camada com SiO2 ou SiOxNy (otimizado neste trabalho) na interface, além de se observar uma melhora significativa da qualidade de interface. Utilizando dupla camada dielétrica com filmes de SiOxNy e SiO2, ainda espessos (³ 1nm) para camada intermediária, obteve-se uma constante dielétrica efetiva em torno de 20. Vale ressaltar que os dois filmes SiOxNy e TiOx, conseqüentemente a dupla camada, foram fabricados a baixas temperaturas.Silicon oxynitride films obtained by the PECVD technique from N2O+SiH4+He gaseous mixtures, at 320°C, with different deposition pressure and RF power were studied intending to improve the interface quality with Si, decreasing the effective charge density and the interface state density in order to utilize them in MOS semiconductor devices. The results showed that with a deposition pressure of 0.160 mbar and a RF power density lower than 125 W/cm2 it is possible to obtain interface state density (Dit) values of 4x1010 eV-1.cm-2, Electrical Breakdown (Ebd) of 13 MV/cm, comparable with the obtained for thermally grown SiO2 , and an effective charge density (Nss) of 4x1011 cm-2. According with experimental results this Nss value is the minimum attainable with our chemical cleaning process. In this way it can be said that these results are very promising, considering that these materials were obtained by PECVD at low temperatures, but still viable for MOS devices application. In order to initiate studies with high dielectrics constant material, TiOx films (k= 40-180), obtained by reactive sputtering through the Ar+O2 gaseous mixture utilizing a Ti target, were chosen. MOS capacitors with these films were fabricated and dielectric constant values varying from 40 to 160 were obtained. However, until now, these materials have presented appreciable leakage current values, which were, minimize by orders of magnitude with the addition of a thin SiO2 or SiOxNy (optimized in this work) layer at the interface were utilized. This thin layer also resulted in a significant improvement of the interface quality. Utilizing double dielectric layer with SiOxNy or SiO2, still thick (³ 1nm) as intermediate layer a dielectric constant value of 20 was obtained. Its important to mention that the SiOxNy and TiOx films, and consequently the double layer, were deposited at low temperatures.
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Pelloquin, Sylvain. "LaAlO3 amorphe déposé par épitaxie par jets moléculaires sur silicium comme alternative pour la grille high-κ des transistors CMOS." Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00694351.
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Depuis l'invention du transistor MOS à effet de champ dans les années 60, l'exploitation de cette brique élémentaire a permis une évolution exponentielle du domaine de la microélectronique, avec une course effrénée vers la miniaturisation des dispositifs électroniques CMOS. Dans ce contexte, l'introduction des oxydes "high-κ" (notamment HfO2) a permis de franchir la barrière sub-nanométrique de l'EOT (Equivalent Oxide Thickness) pour l'oxyde de grille. Les travaux actuels concernent notamment la recherche de matériaux "high-κ" et de procédés qui permettraient d'avoir une interface abrupte, thermodynamiquement stable avec le silicium, pouvant conduire à des EOTs de l'ordre de 5Å. L'objectif de cette thèse, était d'explorer le potentiel de l'oxyde LaAlO3 amorphe déposé sur silicium par des techniques d'Épitaxie par Jets Moléculaires, en combinant des études sur les propriétés physico-chimiques et électriques de ce système. Le travail de thèse a d'abord consisté à définir des procédures d'élaboration sur Si de couches très minces (≈4nm), robustes et reproductibles, afin de fiabiliser les mesures électriques, puis à optimiser la qualité électrique des hétérostructures en ajustant les paramètres de dépôt à partir de corrélations entre résultats électriques et propriétés physico-chimiques (densité, stœchiométrie, environnement chimique...) et enfin à valider un procédé d'intégration du matériau dans la réalisation de MOSFET. La stabilité et la reproductibilité des mesures ont été atteintes grâce à une préparation de surface du substrat adaptée et grâce à l'introduction d'oxygène atomique pendant le dépôt de LaAlO3, permettant ainsi une homogénéisation des couches et une réduction des courants de fuite. Après optimisation des paramètres de dépôt, les meilleures structures présentent des EOTs de 8-9Å, une constante diélectrique de 16 et des courants de fuite de l'ordre de 10-2A/cm². Les caractérisations physico-chimiques fines des couches par XPS ont révélé des inhomogénéités de composition qui peuvent expliquer que le κ mesuré soit inférieur aux valeurs de LaAlO3 cristallin (20-25). Bien que les interfaces LAO/Si soient abruptes après le dépôt et que LaAlO3 soit thermodynamiquement stable vis-à-vis du silicium, le système LAO amorphe /Si s'est révélé instable pour des recuits post-dépôt effectués à des températures supérieures à 700°C. Un procédé de fabrication de MOSFETs aux dimensions relâchées a été défini pour tester les filières high-κ. Les premières étapes du procédé ont été validées pour LaAlO3.
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Weerakkody, D. A. "Engineered high-k oxides." Thesis, University of Liverpool, 2016. http://livrepository.liverpool.ac.uk/3003448/.
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The evolution of integrated circuit technology over the five decades resulted in scaling down the minimum feature size of a transistor from 10 μm to ~14 nm. The high-k dielectrics were identified as potential candidates to replace SiO2 from 2007 due to the large leakage current observed when scaling down SiO2. These materials captured the attention of many researchers and led them to focus on many emerging applications in addition to metal oxide semiconductor field effect transistors (MOSFET). In this thesis, two emerging applications of high-k dielectrics were investigated: (i) germanium based MOSFETs and (ii) high frequency high speed rectifiers for optical rectennas.
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Xia, Zhanbo. "Materials and Device Engineering for High Performance β-Ga2O3-based Electronics." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587688595358557.
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Saura, Mas Xavier. "Filamentos conductores de ruptura dieléctrica en aislantes delgados." Doctoral thesis, Universitat Autònoma de Barcelona, 2014. http://hdl.handle.net/10803/285732.
Full textAbstract:
La industria micro y nanoelectrónica requiere de múltiples líneas de investigación para la introducción de continuas mejoras en los dispositivos en términos de rendimiento, funcionalidad y escalabilidad. Una de estas mejoras se centra en la idea de utilizar el fenómeno de la ruptura dieléctrica como principio de operación de dispositivos electrónicos. Esta idea ha generado mucho interés recientemente, especialmente en el campo de las memorias no volátiles.
Así, la investigación realizada a lo largo de esta tesis doctoral gira en torno a la ruptura dieléctrica de óxidos de alta permitividad y la posterior conducción filamentaria observada en capacidades metal-aislante-semiconductor (MOS) y metal-aislante-metal (MIM). En concreto, este trabajo se ha centrado en el estudio de tres principales objetivos que han concluido con la publicación de varios artículos, los cuales han permitido presentar esta tesis como compendio de publicaciones.
Por un lado, se muestran los resultados del estudio realizado en relación con el fenómeno de conmutación resistiva observado en capacidades MOS, poniendo especial interés en el fenómeno de Threshold Switching el cual ha sido analizado en términos del modelo de contacto puntual cuántico. Por otro lado, se describen los resultados obtenidos en relación con el estudio y exploración del efecto de campo sobre caminos de ruptura dieléctrica generados en estructuras MIM planares. Para ello se ha realizado el diseño, simulación, fabricación y caracterización de varios dispositivos específicos cuyas dimensiones críticas son del orden de pocos nanómetros. De la caracterización de estas estructuras se han obtenido resultados que muestran indicios del efecto de campo sobre dichos caminos. Por último, se analiza la estadística espacial y temporal de múltiples caminos de ruptura observados en el electrodo superior de capacidades MOS y MIM obtenidos a partir del estrés eléctrico aplicado sobre las mismas. En este sentido, se han desarrollado tres métodos de análisis de distribuciones estadísticas para detectar posibles desviaciones respecto a un proceso aleatorio espacial completo: el primero basado en las distancias entre filamentos vecinos de orden k; el segundo relacionado con la caracterización espacio-temporal de los filamentos; y por último un método en el que se han desarrollado expresiones para el estudio de las distribuciones estadísticas de las distancias y ángulos de los spots en relación a un punto fijo asociado a la punta de inyección de carga utilizada para la generación de los eventos.Micro and nanoelectronics industry requires multiple lines of research for introducing continuous improvements in electronic devices in terms of performance, functionality and scalability. One of these improvements focuses on the idea of using the dielectric breakdown phenomenon as a principle of operation of these devices. This idea has generated much interest recently, especially in the field of non-volatile memories. Thus, the research done in this thesis focuses its attention around the dielectric breakdown phenomena and the subsequent filamentary conduction observed in metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) devices with high dielectric permittivity. Specifically, this work focuses on the study of three main objectives which have resulted in the publication of several articles and this has allowed presenting the thesis as a compendium of publications. The study shows results in relation to the resistive switching phenomenon observed in MOS devices, with particular interest in the phenomenon of Threshold Switching described in terms of the quantum point contact model. Furthermore, results regarding the study of the field-effect on dielectric breakdown paths generated in planar MIM structures are also described. With this goal, it is shown the design, simulation, fabrication and characterization of several devices whose critical dimensions are in the order of a few nanometers. The characterization of these structures shows preliminary results that point in the direction of the expected field effect. Finally, the spatial and temporal statistics of multiple breakdown paths, observed in the top electrode of MOS and MIM capacitors as a result of the applied electrical stress, is analyzed. Three methods were developed to analyze statistical distributions for detecting possible deviations from a complete spatial random process. One is based on the distances between neighboring filaments of order k; the second one concerns the spatio-temporal characterization of the observed filaments; and finally a method is presented, in which expressions have been developed, for the study of the statistical distributions of the distances and angles of the spots relative to a fixed point, which is associated with the charge injection point used in the generation of events.
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Zhang, Zhichun. "Process Dependence of Defects and Dopants in Wide Band Gap Semiconductor and Oxides." The Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1366107518.
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Xiong, Ka. "Interfaces and defects of high-K oxides." Thesis, University of Cambridge, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.614372.
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Cheng, Chih-hao, and 鄭志豪. "The Fabrication and Characterization of Metal-Oxide-High-k-Oxide-Semiconductor (MOHOS)/ Metal-High-k-High-k-Oxide-Semiconductor(MHHOS) Capacitors and Transistors for Non-volatile Memory Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/37003694507556811759.
Full textAbstract:
碩士國立清華大學
電子工程研究所
95
Abstract Conventional SONOS (polysilicon-oxide-nitride-oxide-silicon) non-volatile memory devices use silicon nitride as the charge storage layer. In this work, metal－high-k dielectric－high-k dielectric－oxide－silicon (MHHOS) capacitors and transistors were fabricated using Ta2O5 as the charge storage layer and Y2O3, La2O3 as the blocking oxide layers. Both Al/Y2O3/Ta2O5/SiO2/Si and Al/La2O3/Ta2O5/SiO2/Si capacitors achieve retention time longer than 10 years. In addition, the conduction mechanism under positive bias for Al/SiO2/Ta2O5/SiO2/Si capacitors was studied. With Ta2O5 as the charge storage layer, the dominating conduction mechanism at 495 K with the electric field lower than 0.3 MV/cm is Poole-Frenkel emission. With SiO2 as the blocking layer, the dominating conduction mechanism at the electric field of 0.5 MV/cm < E < 1 MV/cm and in the temperature range from 448 K to 495 K is Schottky emission. The dominating conduction mechanism with the electric field above 1 MV/cm and at the temperature lower than 58 K is Fowler-Nodheim tunneling. The programming and erase times of the Al/Y2O3/Ta2O5/SiO2/Si and the Al/Y2O3/Ta2O5/SiO2/Si transistors are characterized. With a programming stress pulse voltage of 6 V, the threshold voltage shift of more than 0.5 V for both structures are achieved in 10 ns. With a erase stress pulse voltage of -8 V, the erase times of the Al/Y2O3/Ta2O5/SiO2/Si and Al/La2O3/Ta2O5/SiO2/Si transistors are 10μs and 1μs, respectively. The retention properties of MHHOS transistors were also characterized. The Al/Y2O3/Ta2O5/SiO2/Si transistor can keep a ΔVth window of 0.89 V for 10 years. The corresponding number for the Al/La2O3/Ta2O5/SiO2/Si transistor is 0.83 V for 10 years.
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Revathy, P. "High-k Dielectrics For Metal-Insulator-Metal Capacitors." Thesis, 2013. http://etd.iisc.ernet.in/handle/2005/2597.
Full textAbstract:
Metal-insulator-metal (MIM) capacitors are used for analog, RF, and DRAM applications in ICs. The International Technology Roadmap for Semiconductors (ITRS) specifies continuing increase in capacitance density (> 7 fF/ m2), lower leakage current density (< 10 8 A/cm2), very low effective oxide thickness (EOT < 1 nm, for DRAM applications), and better capacitance density-voltage (C-V) linearity ( < 100 ppm/V2, for analog/RF applications). In addition, the maximum fabrication/processing temper-ature should not be greater than 400 0C, in order to be compatible with the thermal budget of back-end fabrication steps. Low dielectric constants of conventional SiO2 and Si3N4 capacitors limit the capacitance densities of these devices. Although scaling down of dielectric thickness increases the capacitance density, it results in large leakage current density and poor C-V linearity.
In this work, the effects of high-k materials (Eu2O3, Gd2O3, TiO2) on the device performance of MIM capacitors are studied. The performance of multi-dielectric stack, and doped-dielectric stack devices are also investigated. The effects of anneal temperature, anneal ambient, anneal mode, and dielectric thickness on device performance are evaluated. C-V, current density-voltage (J-V), and reliability measurements are performed to benchmark the electrical performance, and this is correlated to the structural and material properties of the films through ellipsometry, scanning electron microscopy (SEM), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS) measurements.
High-performance MIM capacitors are fabricated by using (RF sputtered) Eu2O3 dielectric. The fabricated devices are subjected to different anneal conditions, to study their device performance. Forming gas (FG) and argon (Ar) annealed devices are shown to have higher capacitance densities (7 fF/ m2jF G), lower leakage current densities (3.2 10 8 A/cm2jAr at -1 V), and higher , compared to oxygen (O2) annealed de-vices ( 100kHz = 193 ppm/V2jO2). The electrical characterization results are correlated with the surface chemical states of the films through XPS measurements. The annealing ambient is shown to alter the surface chemical states, which, in turn, modulate the electrical characteristics.
High-density MIM capacitors are fabricated by using (RF sputtered) Gd2O3, and Gd2O3-Eu2O3 stacked dielectrics. The fabricated Gd2O3 capacitors are also subjected to different anneal conditions, to study their device performance. Although Gd2O3 capacitors provide high capacitance density (15 fF/ m2), they suffer from high leakage current density, high , and poor reliability. Therefore, stacked dielectrics of Gd2O3 and Eu2O3
(Gd2O3/Eu2O3 and Eu2O3/Gd2O3) are fabricated to reduce leakage current density, improve , and improve reliability, with only a marginal reduction in capacitance density, compared to Gd2O3 capacitors. Density of defects and barrier/trap heights are extracted for the fabricated capacitors, and correlated with the device characteristics.
High-performance MIM capacitors with bilayer dielectric stacks of (ALD-deposited) TiO2-ZrO2, and Si-doped ZrO2 are characterized. Devices with (ALD-deposited) TiO2/ ZrO2/TiO2 (TZT) and AlO-doped TZT stacks are also characterized. The influence of doping on the device performance is studied. The surface chemical states of the deposited films are analyzed by high-resolution XPS. The structural analysis of the samples is performed by XRD measurements, and this is correlated to the electrical characteristics of the devices. Reliability measurements are performed to study the effects of constant voltage and current stress on device performance. High capacitance density (> 45 fF/ m2), low leakage current density (< 5 10 8 A/cm2 at -1 V, for most devices), and sub-nm EOT are achieved. These parameters exceed the ITRS specifications for DRAM storage capacitors.
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Chang, Hsiu-Fu, and 張修福. "Characteristic Analysis of Metal Oxide Semiconductor Devices with High-k Gate Oxide Dielectrics." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/88306041948279404342.
Full textAbstract:
碩士亞洲大學
光電與通訊學系
104
In this work, the hafnium oxide(HfO2) doped aluminum to produce hafnium aluminum oxide (HfAlO) of high dielectric oxide layer material that deposition by chemical vapor atomic layer deposition (ALD), and then the two types high dielectric oxide materials with oxygen plasma and nitrogen plasma surface treatment to reduce the concentration of defects. By current-voltage and capacitance-voltage characteristics, it can be seen that the leakage current is obviously improved, and then the XPS analysis and the component curve fitting are used to verify. Confirm that the sediment of the hafnium oxide and hafnium aluminum oxide with oxygen plasma and nitrogen plasma surface treatment can reduce the defect density to improve the insulation leakage current. According to the result, hafnium aluminum oxide as a thin film transistor gate insulation layer to make the bottom gate structure of indium gallium zinc oxide thin film transistor (IGZO-TTFT). From the electrical measurement results show that the gate leakage current is significantly reduced. The thin film transistor without plasma treatment showed that threshold voltage, sub-threshold swing and the field effect mobility were extracted to be 1.41V, 870mV/dec and 39.14 cm2/Vs ,respectively. The thin film transistor with oxygen plasma treatment showed that threshold voltage, sub-threshold swing and the field effect mobility were extracted to be 1.37V, 528mV/dec and 17.86 cm2/Vs ,respectively. The thin film transistor with nitrogen plasma treatment showed that threshold voltage, sub-threshold swing and the field effect mobility were extracted to be 1.72V, 520mV/dec and8.6cm2/Vs ,respectively. Although the carrier mobility will decline after the plasma, the sub-threshold swing (S.S.) will be better. In addition, the plasma treatment will make the devices into a normally closed state with a power saving effect.
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Lin, Jian Chyi, and 林建旗. "Development of High-k Erbium Oxide and Neodymium Oxide sensing membranes for ISFET." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/63009903073246527136.
Full textAbstract:
碩士長庚大學
電子工程學研究所
96
Bergveld reported measuring ion concentration in solutions on ion sensitive field effect transistors (ISFETs), which are based on semiconductor technology. The 1970 paper of Bergveld is cited as the first paper; many theoretical and experimental studies have been published to describe the behavior of this chemically sensitive electronic device. The commonly accepted model to account for the pH sensitivity of the ISFET is the site-dissociation model, which was first proposed by Yates etc. Recently, Al2O3, TiO2, Ta2O5, and SnO2 were proposed as hydrogen ion sensing membrane for pH-ISFET to replace Si3N4 membrane because of their high sensitivity performance. In this thesis, the erbium oxide, erbium titanium oxide, neodymium oxide, and neodymium titanium oxide were investigated as the sensing membrane of EIS structure. In the experiment, the Er2O3, ErTixOy, Nd2O3, and NdTixOy grew on Si substrate by reactive RF-sputter. We found that these films’ properties are different due to the different temperature of RTA, and it is shown that Ti-doping exhibits better sensitivity. In this work, EIS structures with Er2O3, Er¬TixOy, Nd2O3, and NdTixOy membrane were fabricated to verify pH sensing performance.
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Lu, Hsi-Chieh, and 盧晞婕. "Characterization of Metal Oxide Semiconductor Devices with High-k Dielectrics." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/5t3dd9.
Full textAbstract:
碩士國立交通大學
照明與能源光電研究所
105
In order to improve the properties of III-V metal oxide semiconductor transistor performance, one challenge is to overcome the problem of high-k interface defects. we make MOSCAPs with the combination of wet chemical surface cleaning with TMA pretreatment , reducing oxides of the substrate surface, and hydrogen plasma for improving the quality of the interface between the substrate and Al2O3 is effect will, interface state density (Dit) is lowered to 3E12cm-2V-1. And attempts by the reaction of Ti and Al2O3 formed to increase the dielectric and slow leakage current. An auxiliary TEM image, showing the value of the dielectric equivalent oxide thickness of the gate oxide layer of the rent significantly improved. Finally, we fabricated a n-InGaAs field effect transistor with atomic layer deposition alumina dielectric layer. The transistor on-off current is about~1 E3.
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"Structure of high-k thin films on Si substrate." Thesis, 2009. http://library.cuhk.edu.hk/record=b6074953.
Full textAbstract:
We have investigated the structure and interfacial structure of two types of high-k dielectric thin films on Si using combined experimental and theoretical approaches. In the Hf-based high- k dielectrics, the crystallinity of three films, pure HfO2, Y-incorporated HfO2 and Al-incorporated HfO2, is examined by transmission electron diffraction (TED), and the local coordination symmetries of the Hf atoms in the films are revealed by the profile of electron energy-loss near-edge structure (ELNES) taken at oxygen K-edge. These ELNES spectra are then simulated using real-space multiple-scattering (RSMS) method. We find a good agreement between the experimental and the simulated result of pure HfO2. The incorporation of Y indeed stabilizes HfO 2 to a cubic structure, but it also contributes to possible lattice distortion and creation of complex defect states, causing discrepancies between the experimental and the simulated result. As a comparison, the local coordination symmetry of Hf is largely degraded upon the incorporation of Al, which not only amorphorizes HfO2, but also introduces significantly amount of O vacancies in the film. We have further investigated the interfacial structures of HfO2 and Al-incorporated HfO2 thin films on Si using spatially resolved ELNES, which a series of the oxygen K-edge spectra is acquired when a 0.3 nm electron probe scanning across the film/Si interface. We find that interfaces are not atomically sharp, and variation in the local coordination symmetry of Hf atoms lasts for a couple of monolayers for both the HfO2 and the Al-incorporated HfO2 samples. Annealing of the HfO2 film in the oxygen environment leads to the formation of a thick SiO2/SiOx stack layer in-between the original HfO2 and the Si substrate. As a comparison, the interfacial stability is significantly improved by incorporating Al into the HfO 2 film to form HfAlO, which effectively reduces/eliminates the interfacial silicon oxide formation during the oxygen annealing process. The interfacial structure of SiTiO3 (STO) dielectric and Si is significant different from that between Hf-based dielectric and Si, as the crystalline STO is epitaxially grown on the Si. Together with the high resolution high-angle annular-dark-field (HAADF) image, the spatially resolved ELNES acquired across the STO/Si interface reveal an amorphous interfacial region of 1-2 monolayer thickness, which is lack of Sr, but contains Ti, Si, and O. Based on these experimental evidences, we propose a classical molecular dynamic (MD) interface model, in which the STO is connected to Si by a distorted Ti-O layer and a complex Si-O layer. The simulated results, based on the MD interface model, generally agree with the experimental results, disclosing a gradual change of the local atomic coordination symmetry and possible defect incorporation at the interface.Wang, Xiaofeng = Si衬底上高k介电薄膜的结构研究 / 王晓峰.
Adviser: Li Quan.
Source: Dissertation Abstracts International, Volume: 72-11, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2009.
Includes bibliographical references (leaves 103-112).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Wang, Xiaofeng = Si chen di shang gao k jie dian bo mo de jie gou yan jiu / Wang Xiaofeng.
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Lin, Chen-Han. "Nanocrystals Embedded Zirconium-doped Hafnium Oxide High-k Gate Dielectric Films." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-08-9884.
Full textAbstract:
Nanocrystals embedded zirconium-doped hafnium oxide (ZrHfO) high-k gate dielectric films have been studied for the applications of the future metal oxide semiconductor field effect transistor (MOSFET) and nonvolatile memory. ZrHfO has excellent gate dielectric properties and can be prepared into MOS structure with a low equivalent oxide thickness (EOT). Ruthenium (Ru) modification effects on the ZrHfO high-k MOS capacitor have been investigated. The bulk and interfacial properties changed with the inclusion of Ru nanoparticles. The permittivity of the ZrHfO film was increased while the energy depth of traps involved in the current transport was lowered. However, the barrier height of titanium nitride (TiN)/ZrHfO was not affected by the Ru nanoparticles. These results can be important to the novel metal gate/high-k/Si MOS structure. The Ru-modified ZrHfO gate dielectric film showed a large breakdown voltage and a long lifetime.
The conventional polycrystalline Si (poly-Si) charge trapping layer can be replaced by the novel floating gate structure composed of discrete nanodots embedded in the high-k film. By replacing the SiO2 layer with the ZrHfO film, promising memory functions, e.g., low programming voltage and long charge retention time, can be expected. In this study, the ZrHfO high-k MOS capacitors that separately contain nanocrystalline ruthenium oxide (nc-RuO), indium tin oxide (nc-ITO), and zinc oxide (nc-ZnO) have been successfully fabricated by the sputtering deposition method followed with the rapid thermal annealing process. Material and electrical properties of these kinds of memory devices have been investigated using analysis tools such as XPS, XRD, and HRTEM; electrical characterizations such as C-V, J-V, CVS, and frequency-dependent measurements. All capacitors showed an obvious memory window contributed by the charge trapping effect. The formation of the interface at the nc-RuO/ZrHfO and nc-ITO/ZrHfO contact regions was confirmed by the XPS spectra. Charges were deeply trapped to the bulk nanocrystal sites. However, a portion of holes were loosely trapped at the nanocrystal/ZrHfO interface. Charges trapped to the different sites lead to different detrapping characteristics. For further improving the memory functions, the dual-layer nc-ITO and -ZnO embedded ZrHfO gate dielectric stacks have been fabricated. The dual-layer embedded structure contains two vertically-separated nanocrystal layers with a higher density than the single-layer embedded structure. The critical memory functions, e.g., memory window, programming efficiency, and charge retention can be improved by using the dual-layer nanocrystals embedded floating gate structure. This kind of gate dielectric stack is vital for the next-generation nonvolatile memory applications.
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"Microstructure and electronic structure study of Hf-based high-K thin films." 2006. http://library.cuhk.edu.hk/record=b5893041.
Full textAbstract:
Wang Xiaofeng = Hf基高K介电薄膜的微观结构和电子结构研究 / 王晓峰.Thesis (M.Phil.)--Chinese University of Hong Kong, 2006.
Includes bibliographical references (leaves 62-67).
Text in English; abstracts in English and Chinese.
Wang Xiaofeng = Hf ji gao K jie dian bo mo de wei guan jie gou he dian zi jie gou yan jiu / Wang Xiaofeng.
Table of Contents --- p.iv
List of Figures --- p.vii
List of Tables --- p.x
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Background --- p.3
Chapter 2.1 --- Ideal high-k materials --- p.3
Chapter 2.1.1 --- Current problems with Si02 and possible solutions --- p.3
Chapter 2.1.2 --- Requirements on the high-k gate dielectric materials --- p.6
Chapter 2.2 --- Recent results on high-k gate dielectrics --- p.8
Chapter 2.2.1 --- A1203 --- p.8
Chapter 2.2.2 --- Y203 and La203 --- p.9
Chapter 2.2.3 --- Hf02 and Zr02 --- p.10
Chapter 2.2.4 --- Pseudo-binary Alloys --- p.10
Chapter 3 --- Experimental and Instrumentation --- p.13
Chapter 3.1 --- Transmission electron microscopy (TEM) --- p.13
Chapter 3.2 --- Transmission electron diffraction (TED) --- p.15
Chapter 3.3 --- Electron energy loss spectroscopy (EELS) --- p.16
Chapter 4 --- Data Analysis Methodology --- p.22
Chapter 4.1 --- Diffraction analysis --- p.22
Chapter 4.1.1 --- Ring ratio analysis for polycrystal diffraction pattern --- p.23
Chapter 4.1.2 --- RDF analysis for amorphous materials --- p.24
Chapter 4.2 --- Eliminating the plural scattering in EELS --- p.29
Chapter 4.2.1 --- Removal of plural scattering from inner-shell edges --- p.30
Chapter 4.2.2 --- Fourier-Ratio deconvolution --- p.30
Chapter 4.2.3 --- "Demonstration using Co L2,3 core-loss spectrum" --- p.31
Chapter 5 --- The Temperature Effect on the Microstructure of HfO2 Films --- p.37
Chapter 5.1 --- Experimental --- p.38
Chapter 5.2 --- Phase identification and crystallinity analysis of the Hf02 thin films --- p.38
Chapter 5.2.1 --- Phase and crystallinity analysis from TEDs --- p.38
Chapter 5.2.2 --- The phase and crystallinity evolution with the growth temperature --- p.39
Chapter 5.3 --- The local symmetry of Hf atom in the films --- p.40
Chapter 6 --- Effect of A1 Addition on the Microstructure and Electronic Structure of HfO2 Films --- p.43
Chapter 6.1 --- Experimental --- p.44
Chapter 6.2 --- RDF analysis of HfAlO films --- p.45
Chapter 6.3 --- The local symmetry of Hf atom in the HfAlO films --- p.46
Chapter 6.4 --- Loss functions of HfAlO films --- p.48
Chapter 7 --- Comparison of A1 and Y Addition on the Microstructure of Hf02 Films --- p.56
Chapter 7.1 --- Experimental --- p.57
Chapter 7.2 --- Phase identification and crystallinity analysis of the alloy thin films --- p.57
Chapter 7.2.1 --- Phase and crystallinity analysis from TEDs --- p.57
Chapter 7.2.2 --- The phase and crystallinity evolution with the Y and A1 incorporation --- p.58
Chapter 7.3 --- The local symmetry of Hf atom in the alloy thin films --- p.59
Chapter 8 --- Conclusion --- p.61
Bibliography --- p.62
48
Liu, Wen-Da, and 劉文達. "Electrical characteristics of ultra-thin high-k gate oxide-semiconductor interfaces." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/77497303794687044259.
Full textAbstract:
碩士國立中山大學
光電工程研究所
90
Abstract The purpose of this thesis is to study the electrical characteristics of ultra-thin high-k gate oxide-semiconductor interfaces. The measured samples are Y2O3/Si、Gd2O3/GaAs、Ga2O3(Gd2O3)/GaAs MOS capacitors. An accurate C-V relation has been obtained consistently by using a model that includes both series and shunt parasitic resistances. Using the semiconductor parameters and the oxide parameters, an ideal C-V curve with Dit = 0 is fitted to the accurate capacitance data, and the interface state density is deduced by Terman method. After post - metallization annealing (PMA) at 425℃, the oxide charge density, interface state density and leakage current were reduced. The results are following : (1) For Y2O3/Si MOS capacitors, we obtained a oxide charge density ~ 7.7 x 1010 cm-2, an interface state density ~ 3.6 x 1010 cm-2ev-1, and an equivalent oxide thickness ~ 52Å; (2) For Gd2O3/GaAs MOS capacitors, we obtained a oxide charge density ~ 9.8 x 1011 cm-2, an interface state density ~ 2 x 1011 cm-2ev-1, and an equivalent oxide thickness ~ 57Å; (3) For Ga2O3(Gd2O3)/GaAs MOS capacitors, we obtained a oxide charge density ~ 4.2 x 1012 cm-2, an interface state density ~ 6 x 1011 cm-2ev-1, and an equivalent oxide thickness ~ 91Å. The dielectric constants obtained from our data are smaller than the reported values. A possible explanation is that an interfacial layer formed at the oxide/semiconductor interface to reduce equivalent dielectric constant.
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Tang, Ho-Cheng, and 湯和錚. "Study of Enhancement-Mode GaAs Metal-Oxide-Semiconductor Field-Effect Transistors with High-K Gate Oxides." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/95423476178714766568.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
97
The purpose of this thesis is to simulate the enhancement-mode GaAs metal-oxide-semiconductor field-effect transistors with high-k gate dielectrics. We use APSYS commercial software to simulate the influences of the high-k gate dielectrics and the indium composition in the channel on the device characteristics. The short channel effect is also investigated. Simulation results show that the device performance enhances and the threshold voltage exhibits a decreasing trend with the reduced channel length. However, the channel current can not be pinched off due to the drain-induced barrier lowering (DIBL) when the channel length is reduced below 0.1 m. Besides, the increased indium compositions in the channel improve the device performance although not as overwhelming as the gate dielectrics.
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Bai, Weiping. "Germanium MOS devices integrating high-k dielectric and metal gate." Thesis, 2007. http://hdl.handle.net/2152/2991.
Full text