Dissertations / Theses: 'High low'

1

Guo, Haidong. "A low power low noise high accuracy sensor IC." Online access for everyone, 2006. http://www.dissertations.wsu.edu/Dissertations/Fall2006/h_guo_111406.pdf.

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Blanchard, Enka. "Usability : low tech, high security." Thesis, Sorbonne Paris Cité, 2019. http://www.theses.fr/2019USPCC005/document.

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Cette thèse est consacrée au domaine de l’utilisabilité de la sécurité, en particulier dans le contexte de l’authentification en ligne et du vote vérifiable.Le rôle toujours plus important de nos identifiants en ligne, qu’ils soient utilisés pour accéder aux réseaux sociaux, aux services bancaires ou aux systèmes de vote, a débouché sur des solutions faisant plus de mal que de bien. Le problème n’est pas juste technique mais a une forte composante psycho-sociale, qui se révèle dans l’usage des mots de passe --- objet central d'étude de cette thèse. Les utilisateurs font quotidiennement face à des compromis, souvent inconscients, entre sécuriser leurs données et dépenser les ressources mentales limitées et déjà trop sollicitées. Des travaux récents ont montré que l'absence de règles communes, les contraintes ad-hoc si fréquentes et les recommandations contradictoires compliquent ce choix, mais ces recherches sont généralement ignorées, victimes d'une probable incompréhension entre chercheurs, développeurs et utilisateurs. Cette thèse vise à résoudre ces problèmes avec des solutions inspirées par la cryptographie, la psychologie, ainsi que sept études utilisateurs, afin d'obtenir des outils simplifiés non seulement pour l'utilisateur final mais aussi pour le développeur.La première partie des contributions se concentre sur le fournisseur de service, avec deux outils permettant d'améliorer l'expérience utilisateur sans effort de sa part. Nous commençons par une étude sur la facilité de transcription de différents types de codes, afin d'obtenir un design réduisant les erreurs tout en augmentant la vitesse de frappe. Nous montrons aussi comment accepter les fautes de frappe dans les mots de passe peut améliorer la sécurité, en offrant un protocole compatible avec les méthodes de hachage standard.La deuxième partie offre des outils directement aux utilisateurs, avec un gestionnaire de mot de passe mental qui ne nécessite que la mémorisation d'une phrase et d'un code PIN, avec des garanties sur la sécurité des mots de passe si certains sont compromis. Nous proposons aussi une méthode de création de phrase de passe à la fois plus facile et sécurisée, et terminons en montrant empiriquement des failles dans le principal modèle de calcul mental utilisé aujourd'hui dans le domaine.Enfin, nous nous consacrons aux nouveaux protocoles de vote, en commençant par les difficultés à les faire accepter en pratique. Nous répondons à une demande pour des systèmes non-électroniques en proposant plusieurs implémentations de vote vérifiable en papier, une panoplie de primitives et un protocole de vote pour les très petites élections
This dissertation deals with the field of usable security, particularly in the contexts of online authentication and verifiable voting systems.The ever-expanding role of online accounts in our lives, from social networks to banking or online voting, has led to some initially counterproductive solutions. As recent research has shown, the problem is not just technical but has a very real psychosocial component. Password-based authentication, the subject of most of this thesis, is intrinsically linked to the unconscious mechanisms people use when interacting with security systems. Everyday, users face trade-offs between protecting their security and spending valuable mental resources, with a choice made harder by conflicting recommendations, a lack of standards, and the ad-hoc constraints still frequently encountered. Moreover, as recent results from usable security are often ignored, the problem might stem from a fundamental disconnect between the users, the developers and the researchers. We try to address those problems with solutions that are not only simplified for the user's sake but also for the developer's. To this end, we use tools from cryptography and psychology, and report on seven usability experiments.The first part of the contributions uses a service provider's point of view, with two tools to improve the end-user's experience without requiring their cooperation. We start by analysing how easily codes of different structures can be transcribed, with a proposal that reduces error rates while increasing speed. We then look at how servers can accept typos in passwords without changing the general hashing protocol, and how this could improve security. The second part focuses on end-users, starting by a proposed mental password manager that only depends on remembering only a single passphrase and PIN, with guarantees on the mutual security of generated passwords if some get stolen. We also provide a better way to create such passphrases. As mental computing models are central to expanding this field, we finish by empirically showing why the main model used today is not adapted to the purpose.In the third part, we focus on voting protocols, and investigate why changing the ones used in practice is an uphill battle. We try to answer a demand for simple paper-based systems by providing low-tech versions of the first paper-based verifiable voting scheme. To conclude, we propose a set of low-tech primitives combined in a protocol that allows usable verifiable voting with no electronic means in small elections

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Mesquita, Pedro. "Sonaecom: low scale, High uncertainty." Master's thesis, NSBE - UNL, 2009. http://hdl.handle.net/10362/9700.

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Toma, Kumika. "Effects of High-Carbohydrate and Low-Fat Versus High-Protein and Low-Carbohydrate Diets on High-Intensity Aerobic Exercise." View abstract, 2009. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3372362.

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Ibrahim, Sameh Ahmed Assem Mostafa. "High-speed low-power equalizers for high-loss channels." Diss., Restricted to subscribing institutions, 2009. http://proquest.umi.com/pqdweb?did=2026920921&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Saadallah, Nisrine. "High-speed low-power asynchronous circuits." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=80140.

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This thesis presents several design experiments for high-performance power-efficient asynchronous circuits.
In Chapter two we present a new asynchronous pipeline logic family with improved latency and throughput compared to several other asynchronous pipeline circuits. The channels between pipeline stages use data encoding and a small set of minimum-delay timing constraints that permit modular design with few dependencies on technology and layout. We develop circuit blocks that implement linear pipelines as well as forking, joining and data-dependent decisions. An implementation in 0.18mum CMOS exhibits a latency of 56ps per pipeline stage and throughput of 4.8-giga data item per second (GDI/s) in Hspice simulation.
We also present the design of a low-control-overhead asynchronous microprocessor integrated with a high-speed sampling FIFO. This is an experiment in exploring the benefits of asynchronous design in high-speed embedded DSP applications. It reports on the design approach, implementation and performance, including a comparison with the synchronous version of the microprocessor.

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Zhu, Haikun. "High-performance low-power VLSI design." Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3250072.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed April 4, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 97-101).

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Wen, Chien-Hui. "High Birefringence and Low Viscosity Liquid Crystals." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3206.

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In this dissertation, liquid crystal (LC) materials and devices are investigated in order to meet the challenges for photonics and displays applications. We have studied three kinds of liquid crystal materials: positive dielectric anisotropic LCs, negative dielectric anisotropic LCs, and dual- frequency LCs. For the positive dielectric anisotropic LCs, we have developed some high birefringence isothiocyanato tolane LC compounds with birefringence ~0.4, and super high birefringence isothiocyanato biphenyl-bistolane LC compounds with birefringence as high as ~0.7. Moreover, we have studied the photostability of several high birefringence LC compounds, mixtures, and LC alignment layers in order to determine the failure mechanism concerning the lifetime of LC devices. Although cyano and isothiocyanato LC compounds have similar absorption peaks, the isothiocyanato compounds are more stable than their cyano counterparts under the same illumination conditions. This ultraviolet-durable performance of isothiocyanato compounds originates from its molecular structure and the delocalized electron distribution. We have investigated the alignment performance of negative dielectric anisotropic LCs in homeotropic (vertical aligned, VA) LC cell. Some (2,3) laterally difluorinated biphenyls, terphenyls and tolanes are selected for this study. Due to the strong repulsive force between LCs and alignment layer, (2,3) laterally difluorinated terphenyls and tolanes do not align well in a VA cell resulting in a poor contrast ratio for the LC panel. We have developed a novel method to suppress the light leakage at dark state. By doping positive [Delta][epsilon] or non-polar LC compounds/mixtures into the host negative LC mixtures, the repulsive force is reduced and the cell exhibits an excellent dark state. In addition, these dopants increase the birefringence and reduce the viscosity of the host LCs which leads to a faster response time. Dual-frequency liquid crystal exhibits a unique feature that its dielectric anisotropy changes from positive to negative when we increase the operating frequency. Submillisecond response time can be achieved by switching the frequency of a biased voltage, rather than switching the voltage at a given frequency. In this dissertation, we investigate the dielectric heating effect of dual-frequency LCs. Because the absorption peak of imaginary dielectric constant occurs at high frequency region (~ MHz), there is a heat generated when the LC cell is operated at a high frequency voltage. To measure the transient temperature change of the LC inside the cell, we have developed a non-contact method by utilizing the temperature-dependent birefringence property of the LC. Most importantly, we have formulated a new dual-frequency LC mixture which greatly reduces the dielectric heating effect while maintaining good physical properties. Another achievement in this thesis is that we have developed a polarization independent phase modulator by using a negative dielectric anisotropic LC gel. With ~20 % of polymer mixed in the LC host, the LC forms polymer network which, in turn, exerts a strong anchoring force to the neighboring LC molecules. As a result, the operating voltage increases but the response time is significantly decreased. On the phase shift point of view, our homeotropic LC gel has ~0.08 [pi] phase shift, which is 2X larger than the previous nano-sized polymer-dispersed liquid crystal droplets. Moreover, it is free from light scattering and requires a lower operating voltage. In conclusion, this dissertation provides solutions to improve the performance of LC devices both in photonics and displays applications. These will have great impacts in defense and display systems such as optical phased array, LCD TVs, projectors, and LCD monitors.
Ph.D.
Other
Optics and Photonics
Optics

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Ucar, Egemen. "Ternary Nanocomposites Of High Density, Linear Low Density And Low Density Polyethylenes." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608446/index.pdf.

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In this study, the effects of organoclay loading, compatibilizer loading and polyethylene type on the morphology, rheology, thermal properties and mechanical properties of polyethylene/compatibilizer/organoclay nanocomposites were investigated. As compatibilizer, terpolymer of ethylene-methacrylate-glycidyl methacrylate (Lotader®
AX8900), as organoclay Cloisite®
15A were used. All samples were prepared by a co-rotating twin screw extruder, followed by injection molding. Considering ternary nanocomposites, highest impact strength results were obtained with 10% compatibilizer plus 2% organoclay
highest yield stress, elastic modulus, flexural strength, flexural modulus were obtained with 5% compatibilizer plus 4-6% organoclay. DSC data indicated that addition of organoclay and compatibilizer did not change the melting point remarkably
on the other hand it affected the crystallinity. The organoclay used had no nucleation effect on polyethylene, and the compatibilizer decreased the crystallinity of the matrix. X-ray diffraction showed that in all ternary nanocomposites and in binary nanocomposite of high density polyethylene with organoclay, layer separation associated with intercalation of the clay structure occurred,. The highest increase of interlayer gallery spacing was obtained with 10% compatibilizer plus 2% organoclay, which were 25%, 28% and 27% for HDPE, LLDPE and LDPE matrices respectively.

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Selvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.

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A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme.

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Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.

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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.
The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.

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Liu, Yushi. "Low Profile, High Power Density and High Efficiency DC-DC Converters." Thesis, University of Colorado at Boulder, 2019. http://pqdtopen.proquest.com/#viewpdf?dispub=10980034.

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Due to the ever decreasing thickness and increasing battery size of modern cellphones, battery chargers inside cellphones are required to meet increasingly stringent power density requirements, including small printed circuit board (PCB) area and component height. This thesis is focused on low-profile, high-power-density, and high-efficiency dc-dc converters for battery charging applications.

This thesis investigates five topologies, including ZVS-QSW buck converter, three-level buck converter, four-level buck converter, a resonant switched capacitor converter, and a new reconfigurable hybrid switched capacitor converter. The operation principle of each topology is described, and the advantages and disadvantages of each topology are analyzed and compared in terms of efficiency and power density. To accurately evaluate the performance of each topology, this thesis utilizes the augmented state-space modeling method that efficiently calculates the steady-state waveforms of a converter. To accurately predict losses, the dynamic on-resistance of GaN transistors and core loss of inductors have been modeled. Furthermore, a comprehensive optimization methodology is utilized to select circuit and component parameters.

For 2:1 conversation ratio application scenario, two prototypes using GaN transistors and low-voltage Silicon MOSFET have been designed, built and tested for an input voltage range of 5 V to 20 V, an output voltage range of 3 V to 4.2 V, and a maximum output current of 10 A. The prototype with GaN transistors (EPC2023) occupies a PCB area of 358 mm² with component height of 1 mm. To maximize efficiency, the converter is designed to achieve ZVS at light-to-medium loads, while sacrificing ZVS to reduce transistor conduction and inductor losses. This prototype converter achieves a peak efficiency of 98.5%. The prototype using low-voltage Silicon MOSFET (CPF03433) occupies a PCB area of 310 mm². A prototype of four-level buck converter with a PCB area of 410 mm², optimized for 3:1 conversion ratio, has also been built and tested. For extreme-power-density application, a prototype with a PCB area of 79.6 mm² and component height of 1 mm is built and tested. The prototype converter achieves a peak efficiency of 96.7% and a power density of 3230 W/in³.

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Malmgren, Evelina, Frida Ingelsson, and Annica Ohlsson. "Low carb high fat : Passar det normalviktiga?" Thesis, Umeå universitet, Idrottsmedicin, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-56469.

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Low Carb High Fat (LCHF) ses som en striktare variant av GI eller Atkins och är en diet riktad framförallt till personer som lider av det metabola syndromet, där man utesluter i princip alla kolhydrater för att undvika blodsockerhöjningar. Överviktiga och diabetiker som testat denna diet har både fått bättre blodfetter, viktnedgång samt ett förbättrat blodsocker men samtidigt finns det många motsträvare – framförallt SNR (svenska näringsrekommendationer). Syftet med detta projekt var att visa effekterna hos friska, normalviktiga personer som genomgått en tre veckors dietperiod med LCHF kost. Hur vikten, blodfetterna samt det psykiska har påverkats. Resultatet har visat på att vikten har minskat samt att blodfetterna höjts avsevärt, vilket ger ett svar på att LCHF inte passar normalviktiga.

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Kim, Bae-Kyun. "High temperature oxidation of low carbon steel." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19519.

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The quality of steel may be seriously affected by the surface defects that appear on slab surfaces after hot rolling. These defects are related to iron oxidation and, in order to reduce the occurrence of these defects, it is necessary to better understand the formation of iron oxides during high temperature oxidation and the oxide descaling mechanisms. However, systematic research tools and experimental strategies for addressing these issues have not yet been developed. In addition, the mechanisms of oxide cracking and failure have not been understood. In this thesis, research tools and strategies are proposed for studying the high temperature oxidation of low carbon steels. These tools allow the presentation of new data on the phase composition of iron oxides at elevated temperature, characteristics of iron oxide formation, oxide microstructure and texture, oxide defects, and stress distributions in different oxide layers, as well as residual stresses. The microscopic model that was proposed for description of oxide failure allows better understanding of the mechanism for surface defect formation during hot rolling. To describe the dynamics of phase composition changes in textured oxides at elevated temperature, a new phase analysis method is proposed. This x-ray diffraction phase analysis is based on the Rietveld and Dickson's methods, and is used for investigating the effect of alloying elements on the oxidation process. This method was also adopted to track in-situ phase composition changes during high temperature oxidation of commercial low carbon steels. The structure of oxides on low carbon steels, pure iron, and Si-steels was systematically examined by orientation imaging microscopy (OIM). It is demonstrated that OIM can be an invaluable tool for visualizing the oxide microstructure texture and studies of oxide defects. In order to simulate industrial hot rolling of oxidized steel sheet, high temperature oxidations tests were made in the tube furnace up to 950°C, in air. The oxidation process and microstructure development were described using OIM maps including image quality (IQ) and inverse pole figure (IPF) maps. The three different iron oxides phases could be distinguished and the characteristics of oxides with different oxidation histories were compared. Iron oxides developed during high temperature oxidation consisted of wustite (FeO), magnetite (Fe304), and hematite (Fe20s) structures with varying texture, grain shape and size. In order to understand the mechanical properties of iron oxides, residual stresses in the three iron oxides phases were assessed using a specially designed x-ray stress measurement system. The stress distributions in the oxide layers were also simulated using finite element simulation of the hot rolling process.

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Mattsson, Håkan, and Roger Nordahl. "Compensation to executives : high, low or nothing?" Thesis, Gotland University, Institution 2, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:hgo:diva-491.

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Prior studies argue that the board and management of a firm should maximize shareholder value. Also, there is evidence that compensation levels are linked to firm performance as well as monitoring, in other words, the composition of the board influence compensation.

We document no correlation between CEO compensation and firm performance for a sample of Swedish companies listed on the Stockholm Stock Exchange (SSE) over the sample period 1999 to 2008. However, the Industry firms might pay the CEO for performance. Also, stock ownership influence compensation levels; when the five largest shareholders increase their holdings, CEO compensation levels decrease. We interpret this finding as that monitoring is important and the agency costs can be reduced by higher holdings by institutional investors.

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Diatchki, Iavor Sotirov. "High-level abstractions for low-level programming /." Full text open access at:, 2007. http://content.ohsu.edu/u?/etd,227.

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Ahn, Jeongyoun Marron James Stephen. "High dimension, low sample size data analysis." Chapel Hill, N.C. : University of North Carolina at Chapel Hill, 2006. http://dc.lib.unc.edu/u?/etd,375.

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Thesis (Ph. D.)--University of North Carolina at Chapel Hill, 2006.
Title from electronic title page (viewed Oct. 10, 2007). "... in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Department of Statistics and Operations Research." Discipline: Statistics and Operations Research; Department/School: Statistics and Operations Research.

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Pettersson, Ulrika. "Surfaces Designed for High and Low Friction." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-5835.

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19

Mahattanakul, Jirayuth. "High frequency, low distortion current-mode filters." Thesis, Imperial College London, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300970.

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Worapishet, Apisak. "High frequency low power switched-current techniques." Thesis, Imperial College London, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.392911.

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Claus, David. "High accuracy metrology using low-resolution cameras." Thesis, University of Oxford, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442843.

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Jacobs, M. J. "A low cost, high precision star sensor." Thesis, Stellenbosch : University of Stellenbosch, 1995. http://hdl.handle.net/10019.1/4659.

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Thesis (MEng (Electrical and Electronic Engineering))--University of Stellenbosch, 1995.
189 leaves single sided printed, preliminary pages and numbered pages 1-126. Includes bibliography, list of appendixes, figures, notation and symbols. Digitized at 300 dpi (OCR), using a Bizhub 250 Scanner.
ENGLISH ABSTRACT: The Sunsat microsatellite is being developed at the University of Stellenbosch. It is equipped with a high resolution earth imager which requires a sophisticated attitude determination and control system. Precise control of the satellite is impossible without high precision attitude sensors. The most accurate attitude sensor presently used by satellites is the star sensor. The aim 'of this thesis is to develop a low cost, high precision star sensor for the Sunsat microsatellite. The development included the selection of electronic and optical hardware followed by the design, construction and testing of the sensor. Software algorithms were developed and programmed to control the imager, extract stars from images and match the observed constellations to a star catalogue. A set of matching observed and reference vectors are passed to the attitude determination and control system which calculates the three axis orientation of the satellite.
AFRIKAANSE OPSOMMING: Die Sunsat mikrosatelliet word tans by die Universiteit van Stellenbosch ontwikkel. Dit is toegerus met 'n hoeresolusie aardwaarnemingskamera en vereis 'n gevorderde orientasiebepaling-en beheerstelsel. Presiese beheer is onmoontlik sonder akkurate sensore. 'n Stersensor is die mees akkurate tipe sensor waarmee satelliete tans toegerus word. Die doelwit van hierdie tesis is die ontwikkeling van 'n hoe resolusie, laekoste stersensor vir die Sunsat mikrosatelliet. Die ontwikkeling behels die seleksie van elektroniese en optiese apparatuur wat gevolg is deur die ontwerp, opbou en toets van die sensor. Programmatuur algoritrnes is ontwerp om die kamera te beheer, sterre in fotos te herken en waargenome konstellasies in die sterkatalogus te vind. 'n Stel waargenome en verwysingsvektore stel die orientasiebepaling-en beheerstelsel in staat om die orientasie van die satelliet te bereken.

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Martins, da Silva Lucas Filipe. "Adhesive joints for low and high temperatures." Thesis, University of Bristol, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.400421.

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Burrow, Stephen George. "Low power, high efficiency Class D amplifiers." Thesis, University of Bristol, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.271779.

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Ni, George (George Wei). "Low-cost, high performance solar vapor generation." Thesis, Massachusetts Institute of Technology, 2018. http://hdl.handle.net/1721.1/115737.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Mechanical Engineering, 2018.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 163-170).
Sustainable access to energy and access to water are two of the defining technological problems that society currently faces. Threats of climate change and depletion of fossil fuel reserves are forcing a shift towards more renewable sources of energy, such as solar energy and others. At the same time, water resources are becoming scarcer, caused by unsustainable extraction of ground water resources. Current projections show that by 2025, the population of people living in water-stressed areas is expected to increase to 3.9 billion. Exacerbating this problem is continuing urbanization, which stresses local water supplies further. The two problems of energy and water are inextricably tied together. Water processing, such as desalination and wastewater management, fundamentally requires energy inputs, while energy production often requires water for operational cooling. This thesis focuses on developing technologies for low-intensity utilization of solar energy for desalination and wastewater management. Traditional solar thermal technologies collect sunlight, and use motorized optical concentrators to concentrate the weak solar flux to create high temperature steam, often 400'C or higher. These optical concentrators are costly and require maintenance that are unattractive in many small-scale and low-intensity applications. These applications include distributed desalination, medical sterilization, wastewater management, and more. In this thesis, the research has focused on 1) evaporation mechanisms in nanofluids for solar applications, 2) a solar steam generation structure that operates without optical concentrators, and 3) a floating solar still that produces water without the need for periodic cleaning of excess salts, and has a material cost of $3 to supply individual daily drinking water needs, which can be paid back quickly for some regions like the Maldive. One of the first approaches to solar vapor generation was to use nanoparticles suspended in water, or nanofluids, to localize solar absorption to near the evaporation surface. This approach reduces the temperature drop between the heat generation site and the evaporation surface, increasing the evaporation rate. This thesis first explores the vapor generation mechanisms in nanofluid-based solar vapor generation, and develops a small-scale nanofluid-based solar receiver that could generate vapor at 70% efficiency. A theory was developed to show how nanoparticle suspension could affect the nanofluid transient performance. This thesis next demonstrates a small-scale floating solar steam generator, that does not require optical concentration. This was achieved by further extending the heat localization concept, using various widely available materials to reduce radiative, convective, and conductive losses. By reconfiguring the device, steam at 100°C or vapor at 70% efficiency could be produced. The basic steam generator was then improved and adapted to reject excess salts left behind from vapor formation. The salt rejecting structure was coupled with a condensation cover, to form a floating solar still that was demonstrated to operate in the ocean, simultaneously producing drinkable water and rejecting the excess salts. Salt rejection experiments were conducted to prove the long-term ability of the structure to operate in saline waters.
by George Wei Ni.
Ph. D.

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Li, Wei Ph D. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. "Very-high-frequency low-voltage power delivery." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82352.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 217-223).
Power conversion for the myriad low-voltage electronic circuits in use today, including portable electronic devices, digital electronics, sensors and communication circuits, is becoming increasingly challenging due to the desire for lower voltages, higher conversion ratios and higher bandwidth. Future computation systems also pose a major challenge in energy delivery that is difficult to meet with existing devices and design strategies. To reduce interconnect bottlenecks and enable more flexible energy utilization, it is desired to deliver power across interconnects at high voltage and low current with on- or over-die transformation to low voltage and high current, while providing localized voltage regulation in numerous zones. This thesis introduces elements for hybrid GaN-Si dc-de power converters operating at very high frequencies (VHF, 30-300 MHz) for low-voltage applications. Contributions include development of a new VHF frequency multiplier inverter suitable for step-down power conversion, and a Si CMOS switched-capacitor step-down rectifier. These are applied to develop a prototype GaN-Si hybrid dc-dc converter operating at 50 MHz. Additionally, this thesis exploits these elements to propose an ac power delivery architecture for low-voltage electronics in which power is delivered across the interconnect to the load at VHF ac, with local on-die transformation and rectification to dc. With the proposed technologies and emerging passives, it is predicted that the ac power delivery system can achieve over 90 % efficiency with greater than 1 W/mm² power density and 5:1 voltage conversion ratio. A prototype system has been designed and fabricated using a TSMC 0.25 [mu]m CMOS process to validate the concept. It operates at 50 MHz with output power of 4 W. The prototype converter has 8:1 voltage conversion ratio with input voltage of 20 V and output voltage of 2.5 V. To the author's best knowledge, this is the first ac power delivery architecture for low-voltage electronics ever built and tested.
by Wei Li.
Ph.D.

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Lee, Sunghyuk. "Techniques for low-power high-performance ADCs." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87928.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 127-133).
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
by Sunghyuk Lee.
Ph. D.

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28

Cunningham, Michael Lawrence. "A High Temperature Wideband Low Noise Amplifier." Thesis, Virginia Tech, 2016. http://hdl.handle.net/10919/78388.

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As the oil industry continues to drill deeper to reach new wells, electronics are being required to operate at extreme pressures and temperatures. Coupled with substantial real-time data targets, the need for robust high speed electronics is quickly on the rise. This paper presents a high temperature wideband low noise amplifier (LNA) with zero temperature coefficient maximum available gain (ZTCMAG) biasing for a downhole communication system. The proposed LNA is designed and prototyped using 0.25μm GaN on SiC RF transistor technology, which is chosen due to the high junction temperature capability. Measurements show that the proposed LNA can operate reliably up to an ambient temperature of 230°C with a minimum noise figure (NF) of 2.0 dB, gain of 16.1 dB, and P1dB of 19.1 dBm from 230.5MHz — 285.5MHz. The maximum variation with temperature from 25°C to 230°C is 1.53dB for NF and 0.65dB for gain.
Master of Science

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29

Ridgeway, Robert. "Low Noise Amplifiers with High Dynamic Range." International Foundation for Telemetering, 2009. http://hdl.handle.net/10150/606146.

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ITC/USA 2009 Conference Proceedings / The Forty-Fifth Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2009 / Riviera Hotel & Convention Center, Las Vegas, Nevada
This new transistor will make it possible to achieve signal to noise ratio improvements of up to 15 dB (six times more link distance) for systems where the antenna looks sky ward. Using this type of low noise pHEMT device for on the horizon links insures that the telemetry link will be limited only by the natural thermal radio back ground noise and not by the receivers noise.

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30

Yang, Boyi. "High Performance Low Voltage Power MOSFET for High-Frequency Synchronous Buck Converters." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5582.

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Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35[micro]m process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.
ID: 031001367; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Weiwei Deng.; Title from PDF title page (viewed May 8, 2013).; Thesis (M.S.M.E.)--University of Central Florida, 2012.; Includes bibliographical references (p. 84-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering

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31

Foster, Timothy John. "High pressure and high magnetic field studies of low dimensional semiconductor structures." Thesis, University of Nottingham, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315090.

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Poitzsch, Alec Julius. "A high voltage, high current, low error operational amplifier with novel features." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91698.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 173-174).
This project details the design and evaluation of an operational amplifier designed in XF40, a 40 Volt bipolar process. Initially the signal path circuitry of the amplifier is outlined. Design decisions are chiefly formed around high voltage and high current drive functionality. A novel topology is introduced which compensates base current errors introduced by the individual stages, resulting in a very low (first-order canceled) overall input-referred voltage offset. Novel features are introduced which expand the functionality of the amplifier. Input stage gm is configurable, allowing for the tuning of amplifier bandwidth for a given gain configuration. A robust current-limiting architecture is implemented which allows for a user-configurable output current limit. When this current limit is reached, the amplifier latches into an alternate mode of operation, protecting the amplifier and the load. We utilize disjoint voltage supply rails at the input and output of the amplifier, substantially minimizing overall power dissipation. The chosen topology permits this feature without the introduction of additional errors. We introduce a "boosting" circuit which extends the large signal bandwidth and slew rate of the amplifier. Amplifier performance is evaluated through simulation in Cadence and ADICE (SPICE). The amplifier is capable of driving 1 Ampere through capacitive and resistive loads. The result is a low distortion amplifier with microvolt-order input-referred offset (VOS), 65 MHz large signal bandwidth, and 3000 V/[mu]s slew rate, powered at 20 mA quiescent current.
by Alec Julius Poitzsch.
M. Eng.

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Domond, Natasha Marie. "Educators' Perceptions of High-Stakes Testing in Low and High Poverty Schools." ScholarWorks, 2015. https://scholarworks.waldenu.edu/dissertations/1688.

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Since the development and implementation of the No Child Left Behind Act (NCLB) of 2002, educators have received pressure from local, state, and federal policyholders for students to achieve academically and for schools to make adequate yearly progress to avoid state and federal sanctions. The purpose of this study was to examine educators' perceptions of the effects of high-stakes testing and the accountability policies in high poverty and low poverty schools. The theoretical frameworks were conservation of resources theory, jobs demands-resources model, and job autonomy and control theory. Research questions focused on understanding educators' perception of high-stakes testing regarding curricula, instructional practices, available instructional support, and job satisfaction. A cross-sectional, quasi-experimental design was used to obtain both quantitative and qualitative with a sample of 200 teachers and 6 principals, respectively. To investigate the differences in responses between teachers, a two-way factorial analysis of variance was used. Quantitative findings indicated that teachers in lower poverty schools had a lower perception when it came to the curricula, instructional method, and instructional support. Teachers in lower poverty schools expressed higher job satisfaction. Qualitative findings showed that principals felt that the Georgia Professional Standards teaches how to pass the test and does not give students the opportunity to apply what is learned. These findings illuminate the role of poverty in high-stakes testing and accountability policies; they also assist policymakers and stakeholders in identifying supports needed to ensure that all children succeed.

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Riley, Libby J. "Perceived Best Practices Used in Low-Socioeconomic Status, High-Attendance High Schools." Thesis, Frostburg State University, 2018. http://pqdtopen.proquest.com/#viewpdf?dispub=10638721.

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The purpose of this study was to identify best practices perceived and used by principals in low-SES high schools to achieve high annual attendance rates.

The study was an applied qualitative design, which used interviews for data collection and an emergent approach to data analysis. It involved a combination of criterion and extreme sampling to identify and interview eight principals from low-SES high schools (grades 9–12) in West Virginia with an annual attendance rate over 90%. Coding and data analysis processes involved in vitro and structural protocols.

The following best practices emerged from the research in order of most to least used: offering incentives and student recognition; establishing a positive school culture with high expectations for students to come to school; holding meetings with parents, students and an administrator; having personalized communication between students and an adult within the school; telephoning families of absent students; consistently following established district and state policies for attendance; and picking up absent students at their homes.

All the approaches revealed could be characterized as aspects of one overall best practice: developing a positive culture within the school. The ensuing specific best practices were actions and policies consistently applied and enforced.

Improved attendance results in improved performance and college- and career-readiness. Approaches similar to those revealed in this study of high-attendance, low-SES West Virginia high schools may help to improve attendance and achievement in other high schools, not just in West Virginia, but throughout the United States.

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35

Winter, Jan-Christopher. "QCD jet evolution at high and low scales." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1208912443778-27732.

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This thesis deals with a broad range of aspects that concern the simulation of QCD jet physics by Monte Carlo event generators. Phenomenological work is presented in validating the CKKW approach for merging tree-level matrix elements and parton showers. In the second part the main project is documented comprising the definition, realization and verification of a new QCD colour-dipole cascade. Finally, a new cluster-hadronization model is introduced.

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36

Bystrøm, Vebjørn. "Low power/high performance dynamic reconfigurable filter-design." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8899.

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The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting area to work with. The first part of the text describes some theory behind the digital filter and how to optimize the multipliers that are a part of digital filters. The substantial thing to emphasize here is the use of Canonical Signed Digits (CSD) encoding. CSD representation for FIR filters can reduce the delay and complexity of the hardware implementation. CSD-encoding reduces the amount of non-zero digits and will by this reduce the multiplication process to a few additions/subtractions and shifts. In this thesis it was designed 4 versions of the same filter, that was implemented on an FPGA, where the substantial and most interesting results were the differences between coefficients that was CSD-encoded and coefficients that was represented with 2's complement. It was shown that the filter version that had CSD-encoded coefficients used almost 20% less area then the filter version with 2's complement coefficients. The CSD-encoded filter could run on a maximum frequency of 504,032 MHz compared the other filter that could run on a maximum frequency of 249,123 MHz. One of the filters that was designed was designed using the * operator in VHDL, that proved to be the most efficient when it came to the use of number of slices and speed. The reason for this was because an FPGA has built-in multipliers, so if one has the opportunity to use the multiplier they will give the best result instead of using logic blocks on the FPGA It was also discussed a filter that has the ability to change the coefficients at run-time without starting the design from the beginning. This is an advantage because a constant coefficient multiplier requires the FPGA to be reconfigured and the whole design cycle to be re-implemented. The drawback with the dynamic multiplier is that is uses more hardware resources.

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37

Lam, Lap. "High versus low, elite criticism and popular lyrics." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ61131.pdf.

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Allport, P. P. "High energy neutrino scattering at low Q'2." Thesis, University of Oxford, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.376865.

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39

Daubney, Ben. "Using low-level motion for high-level vision." Thesis, University of Bristol, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.508101.

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40

Hofmann, S. "Low temperature growth of high aspect ratio nanostructures." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604141.

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Carbon nanotubes and -fibres were selectively grown by chemical vapour deposition on pre-patterned catalysts. A systematic study was performed relating the growth and crystallinity of the carbon nanostructures to reactor characteristics, gaseous precursors and diluents as well as catalyst type and material. A DC plasma excitation at low discharge currents (<30 mA) not only resulted in vertical alignment of as-grown carbon nanofibres but, in combination with an acetylene feedback and nickel, cobalt or iron catalysts, enabled an onset of growth at temperatures below 300°C. Extended activation energies of 0.23 eV - 0.35 eV for the growth rate were much lower than for thermal growth (1.2 - 1.5 eV). This suggests a surface diffusion limited growth mechanism on a solid phase catalyst. The result allowed the direct synthesis of patterned, aligned carbon nanofibres onto polyimide foils to fabricate flexible field emitters. Carbon nanofibre-based scanning probes were achieved by novel catalyst patterning techniques, and complex shaped electrochemistry electrodes could be homogeneously covered with free-standing carbon nanofibres by using colloidal catalyst systems. The growth of silicon nanowires was studied based on silane as precursor gas and gold as thin film or colloidal catalyst. A low power RF (10 W) plasma significantly increased the growth rate at temperatures below 400°C. The as-grown silicon nanowires were highly crystalline with diameters (inner core <10 nm) small enough for the observation of quantum confinement effects. Element specific and general growth mechanisms of plasma enhanced chemical vapour deposition are highlighted.

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Li, Nan. "Improvements in High-Coverage and Low-Power LBIST." Doctoral thesis, KTH, Elektroniksystem, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-165463.

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Testing cost is one of the major contributors to the manufacturing cost of integrated circuits. Logic Built-In Self Test (LBIST) offers test cost reduction in terms of using smaller and cheaper ATE, test data volume reduction due to on-chip test pattern generation, test time reduction due to at-speed test pattern application. However, it is difficult to reach a sufficient test coverage with affordable area overhead using LBIST. Also, excessive power dissipation during test due to the random nature of LBIST patterns causes yield-decreasing problems such as IR-drop and overheating. In this dissertation, we present techniques and algorithms addressing these problems. In order to increase test coverage of LBIST, we propose to use on-chip circuitry to store and generate the "top-off" deterministic test patterns. First, we study the synthesis of Registers with Non-Linear Update (RNLUs) as on-chip sequence generators. We present algorithms constructing RNLUs which generate completely and incompletely specified sequences. Then, we evaluate the effectiveness of RNLUs generating deterministic test patterns on-chip. Our experimental results show that we are able to achieve higher test coverage with less area overhead compared to test point insertion. Finally, we investigate the possibilities of integrating the presented on-chip deterministic test pattern generator with existing Design-For-Testability (DFT) techniques with a case study. The problem of excessive test power dissipation is addressed with a scan partitioning algorithm which reduces capture power for delay-fault LBIST. The traditional S-graph model for scan partitioning does not quantify the dependency between scan cells. We present an algorithm using a novel weighted S-graph model in which the weights are scan cell dependencies determined by signal probability analysis. Our experimental results show that, on average, the presented method reduces average capture power by 50% and peak capture power by 39% with less than 2% drop in the transition fault coverage. By comparing the proposed algorithm to the original scan partitioning, we show that the proposed method is able to achieve higher capture power reduction with less fault coverage drop.

QC 20150508

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42

Xu, Shu. "Synthesis of High Quality Low-toxic Semiconductor Nanocrystals." Thesis, University of East Anglia, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.502562.

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New approaches for the synthesis of highly luminescent InP and InP/ZnS nanocrystals were developed by stepwise systematic investigation of the parameters during the reaction stages. The parameters, including solvents, precursors, ligands, capping agents, protic agents, Lewis acids and bases and temperature were discussed in detail in different chapters. The investigation processes helped increase understanding of understand the reaction and surface passivation mechanisms and to develop convenient synthesis approaches. Highly luminescent InP NCs were prepared with an in-situ indium chloride complex in the presence of zinc carboxylates or zinc dithiocarbamates - convenient nucleation initiators and stabilisers. The nanocrystals prepared covered a wide photoluminescence emission range from blue to the near infra-red. This synthesis method also allowed the in-situ growth of highly luminescent InP/ZnS core-shell nanocrystals as well. The principles of selection of reagents are also applicable in the synthesis of other nanocrystals. The as-prepared high-quality InP and InP/ZnS nanocrystals have been exploited in applications in the fields of light emitting diodes (LEOs) and bioimaging.

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43

Berchuk, Vitaliy, Ed Grozalis, Jennifer Yin, and Chris Dehmelt. "A Low Cost, High Density Reconfigurable Recording Subsystem." International Foundation for Telemetering, 2012. http://hdl.handle.net/10150/581620.

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ITC/USA 2012 Conference Proceedings / The Forty-Eighth Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2012 / Town and Country Resort & Convention Center, San Diego, California
Modern test programs require an increase in sensor and bus data while at the same time seeking a decrease in the size and price of data acquisition components. Data archiving, which has been traditionally supplied via dedicated standalone hardware, is not exempt to this demand, but in many ways has not kept up with other instrumentation components in terms of flexibility, size, density and price. The archiving capabilities of a data acquisition system must be able to meet the changing needs of the customer. This paper presents a Solid State Drive (SSD) based data recorder implementation that can be easily reconfigured to address the requirements of different applications, including traditional PCM based systems and contemporary network based systems. The paper identifies the requirements, design challenges, trade-offs and risks in creating a low-cost, flexible data archiving subsystem that can be used in a standalone configuration or be directly integrated with a host data acquisition system.

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44

Banik, Chandan Kumer. "High mass low velocity impact on concrete beams." Thesis, Heriot-Watt University, 2006. http://hdl.handle.net/10399/160.

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45

Goff, Simon E. J. "Organometallic chemistry at high pressures and low temperatures." Thesis, University of Nottingham, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.338521.

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46

Thornton, John Stephen. "Instrumentation for low cost, high resolution NMR imaging." Thesis, University of Manchester, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.358563.

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47

Massara, Aeneas Benedict. "High-speed low-cost lasers for datacommunication networks." Thesis, University of Bristol, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.396679.

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48

Stolk, Jonathan Douglas. "Development of low thermal expansion, high conductivity nanocomposites /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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49

Meco, Halim. "Solidification at the High and Low Rate Extreme." Washington, D.C. : Oak Ridge, Tenn. : United States. Dept. of Energy. Office of Science ; distributed by the Office of Scientific and Technical Information, U.S. Dept. of Energy, 2004. http://www.osti.gov/servlets/purl/835376-9UiMWH/webviewable/.

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Zhang, Ling. "Low power high performance interconnect design and optimization." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3368979.

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Thesis (Ph. D.)--University of California, San Diego, 2009.
Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 113-118).

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Dissertations / Theses on the topic 'High low'

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