Relevant bibliographies by topics / High-power computing

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'High-power computing'

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Published: 4 June 2025
Last updated: 15 July 2025

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Journal articles on the topic "High-power computing"

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Lin, How. "Extreme Power Considerations for High Performance Computing." International Symposium on Microelectronics 2014, no. 1 (2014): 000769–75. http://dx.doi.org/10.4071/isom-wp56.

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Power demand in the high end computing and data server segments are driving higher power delivery requirements at all packaging levels in a typical system. At the compute device level, compute node cards are now requiring core power supplies with current levels well above 100 amps at 1 volt or less. This imposes severe power delivery challenges in both power supply power conversion efficiency improvement and power delivery path loss minimization. Due to substantial aggregate I2R losses introduced by the current carrying structures in the power delivery paths, depending on the current level used, up to 10% and more of power loss could result. The focus of this paper is in the discussion of novel interconnect structures developed for reduction of current delivery path power loss. i3Electronics Research & Development addresses these extremes with packaging constructs capable of efficient handling in excess of 200 amps at the device level. Through the course of this study, methods were developed for thermal and electrical modeling, dynamic test apparatus and testing. Several test vehicles were built based on concepts with promising modeled results. Power loss / efficiency, thermal dynamics and electrical dynamics were measured using these test vehicles. The measured and modeled results were compared and studied to assess the accuracy of the power delivery network modeling methodology. This paper will present the methods and constructs developed along with the models and test results.
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Wenheng Liu and V. K. Prasanna. "Utilizing the power of high-performance computing." IEEE Signal Processing Magazine 15, no. 5 (1998): 85–100. http://dx.doi.org/10.1109/79.708542.

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Forge, Simon. "High-power computing and the value chain." Futures 26, no. 4 (1994): 430–52. http://dx.doi.org/10.1016/0016-3287(94)90008-6.

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Matthew, N. O. Sadiku, A. Omotoso Adedamola, and M. Musa Sarhan. "Power Aware Computing." International Journal of Trend in Scientific Research and Development 4, no. 1 (2019): 24–25. https://doi.org/10.5281/zenodo.3604651.

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With the proliferation of portable computing devices, power consumption has become a major concern. Power consumption has posed a serious challenge to the high performance computing systems. Power aware computing is to minimize energy requirements for computation. The main objective of power aware computing is to conserve energy for routing messages from source to destination. This paper provides a brief introduction to power aware computing. Matthew N. O. Sadiku | Adedamola A. Omotoso | Sarhan M. Musa "Power Aware Computing" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-4 | Issue-1 , December 2019, URL: https://www.ijtsrd.com/papers/ijtsrd29395.pdf
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Rama Sangireddy, H. Kim, and A. K. Somani. "Low-power high-performance reconfigurable computing cache architectures." IEEE Transactions on Computers 53, no. 10 (2004): 1274–90. http://dx.doi.org/10.1109/tc.2004.80.

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Ge, Rong, Xizhou Feng, Pengfei Zou, and Tyler Allen. "The Paradigm of Power Bounded High-Performance Computing." Journal of Computer Science and Technology 38, no. 1 (2023): 87–102. http://dx.doi.org/10.1007/s11390-023-2885-7.

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O’Connor, Owen, Tarek Elfouly, and Ali Alouani. "Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms." Energies 16, no. 16 (2023): 6043. http://dx.doi.org/10.3390/en16166043.

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There are many real-world applications that require high-performance mobile computing systems for onboard, real-time processing of gathered data due to latency, reliability, security, or other application constraints. Unfortunately, most existing high-performance mobile computing systems require a prohibitively high power consumption in the face of the limited power available from the batteries typically used in these applications. For high-performance mobile computing to be practical, alternative hardware designs are needed to increase the computing performance while minimizing the required power consumption. This article surveys the state-of-the-art in high-efficiency, high-performance onboard mobile computing, focusing on the latest developments. It was found that more research is needed to design high-performance mobile computing systems while minimizing the required power consumption to meet the needs of these applications.
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Anil Kumar Chunduru. "GPU Parallel Computing Architectures : Unlocking the Power of Parallelism for High-Performance Applications." International Journal of Scientific Research in Computer Science, Engineering and Information Technology 10, no. 6 (2024): 390–96. http://dx.doi.org/10.32628/cseit24106175.

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Graphics Processing Units (GPUs) have evolved from specialized graphics rendering hardware to become powerful parallel computing architectures, revolutionizing high-performance computing across diverse domains. This comprehensive article explores the fundamental principles of GPU parallel computing architectures, their design, and their impact on modern computational challenges. We begin by examining the multi-core structure, memory hierarchy, and data processing capabilities of GPUs, including the SIMD execution model and thread organization. The article then delves into prominent programming models like CUDA and OpenCL, discussing their features and comparative advantages. We explore how GPUs are leveraged for general-purpose computing in scientific simulations, machine learning, and big data analytics, while also addressing the challenges inherent in GPU parallel computing, such as data transfer bottlenecks and load balancing. Recent technological advancements, including tensor cores, unified memory architecture, and ray tracing acceleration, are analyzed for their transformative potential. The article concludes by examining future directions in GPU technology, including integration with emerging technologies like quantum computing, advancements in energy efficiency, and the potential impact on solving complex global challenges. Through this comprehensive analysis, we illustrate the pivotal role of GPU parallel computing architectures in shaping the future of high-performance computing and their potential to address some of the world's most pressing computational problems.
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Borghesi, Andrea, Andrea Bartolini, Michele Lombardi, Michela Milano, and Luca Benini. "Scheduling-based power capping in high performance computing systems." Sustainable Computing: Informatics and Systems 19 (September 2018): 1–13. http://dx.doi.org/10.1016/j.suscom.2018.05.007.

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Natarajan, Venkat, Anand Deshpande, Sudarshan Solanki, and Arun Chandrasekhar. "Thermal and Power Challenges in High Performance Computing Systems." Japanese Journal of Applied Physics 48, no. 5 (2009): 05EA01. http://dx.doi.org/10.1143/jjap.48.05ea01.

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Dissertations / Theses on the topic "High-power computing"

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Choi, Jee Whan. "Power and performance modeling for high-performance computing algorithms." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53561.

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The overarching goal of this thesis is to provide an algorithm-centric approach to analyzing the relationship between time, energy, and power. This research is aimed at algorithm designers and performance tuners so that they may be able to make decisions on how algorithms should be designed and tuned depending on whether the goal is to minimize time or to minimize energy on current and future systems. First, we present a simple analytical cost model for energy and power. Assuming a simple von Neumann architecture with a two-level memory hierarchy, this model pre- dicts energy and power for algorithms using just a few simple parameters, such as the number of floating point operations (FLOPs or flops) and the amount of data moved (bytes or words). Using highly optimized microbenchmarks and a small number of test platforms, we show that although this model uses only a few simple parameters, it is, nevertheless, accurate. We can also visualize this model using energy “arch lines,” analogous to the “rooflines” in time. These “rooflines in energy” allow users to easily assess and com- pare different algorithms’ intensities in energy and time to various target systems’ balances in energy and time. This visualization of our model gives us many inter- esting insights, and as such, we refer to our analytical model as the energy roofline model. Second, we present the results of our microbenchmarking study of time, energy, and power costs of computation and memory access of several candidate compute- node building blocks of future high–performance computing (HPC) systems. Over a dozen server-, desktop-, and mobile-class platforms that span a range of compute and power characteristics were evaluated, including x86 (both conventional and Xeon Phi accelerator), ARM, graphics processing units (GPU), and hybrid (AMD accelerated processing units (APU) and other system–on–chip (SoC)) processors. The purpose of this study was twofold; first, it was to extend the validation of the energy roofline model to a more comprehensive set of target systems to show that the model works well independent of system hardware and microarchitecture; second, it was to improve the model by uncovering and remedying potential shortcomings, such as incorporating the effects of power “capping,” multi–level memory hierarchy, and different implementation strategies on power and performance. Third, we incorporate dynamic voltage and frequency scaling (DVFS) into the energy roofline model to explore its potential for saving energy. Rather than the more traditional approach of using DVFS to reduce energy, whereby a “slack” in computation is used as an opportunity to dynamically cycle down the processor clock, the energy roofline model can be used to determine precisely how the time and energy costs of different operations, both compute and memory, change with respect to frequency and voltage settings. This information can be used to target a specific optimization goal, whether that be time, energy, or a combination of both. In the final chapter of this thesis, we use our model to predict the energy dissi- pation of a real application running on a real system. The fast multipole method (FMM) kernel was executed on the GPU component of the Tegra K1 SoC under various frequency and voltage settings and a breakdown of instructions and data ac- cess pattern was collected via performance counters. The total energy dissipation of FMM was then calculated as a weighted sum of these instructions and the associated costs in energy. On eight different voltage and frequency settings and eight different algorithm–specific input parameters per setting, for a total of 64 total test cases, the accuracy of the energy roofline model for predicting total energy dissipation was within 6.2%, with a standard deviation of 4.7%, when compared to actual energy measurements. Despite its simplicity and its foundation on the first principles of algorithm anal- ysis, the energy roofline model has proven to be both practical and accurate for real applications running on a real system. And as such, it can be an invaluable tool for al- gorithm designers and performance tuners with which they can more precisely analyze the impact of their design decisions on both performance and energy efficiency.
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Borghesi, Andrea <1988&gt. "Power-Aware Job Dispatching in High Performance Computing Systems." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amsdottorato.unibo.it/7982/1/master.pdf.

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This works deals with the power-aware job dispatching problem in supercomputers; broadly speaking the dispatching consists of assigning finite capacity resources to a set of activities, with a special concern toward power and energy efficient solutions. We introduce novel optimization approaches to address its multiple aspects. The proposed techniques have a broad application range but are aimed at applications in the field of High Performance Computing (HPC) systems. Devising a power-aware HPC job dispatcher is a complex, where contrasting goals must be satisfied. Furthermore, the online nature of the problem request that solutions must be computed in real time respecting stringent limits. This aspect historically discouraged the usage of exact methods and favouring instead the adoption of heuristic techniques. The application of optimization approaches to the dispatching task is still an unexplored area of research and can drastically improve the performance of HPC systems. In this work we tackle the job dispatching problem on a real HPC machine, the Eurora supercomputer hosted at the Cineca research center, Bologna. We propose a Constraint Programming (CP) model that outperforms the dispatching software currently in use. An essential element to take power-aware decisions during the job dispatching phase is the possibility to estimate jobs power consumptions before their execution. To this end, we applied Machine Learning techniques to create a prediction model that was trained and tested on the Euora supercomputer, showing a great prediction accuracy. Then we finally develop a power-aware solution, considering the same target machine, and we devise different approaches to solve the dispatching problem while curtailing the power consumption of the whole system under a given threshold. We proposed a heuristic technique and a CP/heuristic hybrid method, both able to solve practical size instances and outperform the current state-of-the-art techniques.
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MA, LIANG. "Low power and high performance heterogeneous computing on FPGAs." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2727228.

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ROOZMEH, MEHDI. "High Performance Computing via High Level Synthesis." Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710706.

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As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of the available computing power. This thesis is in particular devoted to High Performance Computing applications, where those trends are carried to the extreme. In this domain, the primary aspects to be taken into consideration are (1) performance (by definition) and (2) energy consumption (since operational costs dominate over procurement costs). These requirements can be satisfied more easily by deploying heterogeneous platforms, which include CPUs, GPUs and FPGAs to provide a broad range of performance and energy-per-operation choices. In particular, as we will see, FPGAs clearly dominate both CPUs and GPUs in terms of energy, and can provide comparable performance. An important aspect of this trend is of course design technology, because these applications were traditionally programmed in high-level languages, while FPGAs required low-level RTL design. The OpenCL (Open Computing Language) developed by the Khronos group enables developers to program CPU, GPU and recently FPGAs using functionally portable (but sadly not performance portable) source code which creates new possibilities and challenges both for research and industry. FPGAs have been always used for mid-size designs and ASIC prototyping thanks to their energy efficient and flexible hardware architecture, but their usage requires hardware design knowledge and laborious design cycles. Several approaches are developed and deployed to address this issue and shorten the gap between software and hardware in FPGA design flow, in order to enable FPGAs to capture a larger portion of the hardware acceleration market in data centers. Moreover, FPGAs usage in data centers is growing already, regardless of and in addition to their use as computational accelerators, because they can be used as high performance, low power and secure switches inside data-centers. High-Level Synthesis (HLS) is the methodology that enables designers to map their applications on FPGAs (and ASICs). It synthesizes parallel hardware from a model originally written C-based programming languages .e.g. C/C++, SystemC and OpenCL. Design space exploration of the variety of implementations that can be obtained from this C model is possible through wide range of optimization techniques and directives, e.g. to pipeline loops and partition memories into multiple banks, which guide RTL generation toward application dependent hardware and benefit designers from flexible parallel architecture of FPGAs. Model Based Design (MBD) is a high-level and visual process used to generate implementations that solve mathematical problems through a varied set of IP-blocks. MBD enables developers with different expertise, e.g. control theory, embedded software development, and hardware design to share a common design framework and contribute to a shared design using the same tool. Simulink, developed by MATLAB, is a model based design tool for simulation and development of complex dynamical systems. Moreover, Simulink embedded code generators can produce verified C/C++ and HDL code from the graphical model. This code can be used to program micro-controllers and FPGAs. This PhD thesis work presents a study using automatic code generator of Simulink to target Xilinx FPGAs using both HDL and C/C++ code to demonstrate capabilities and challenges of high-level synthesis process. To do so, firstly, digital signal processing unit of a real-time radar application is developed using Simulink blocks. Secondly, generated C based model was used for high level synthesis process and finally the implementation cost of HLS is compared to traditional HDL synthesis using Xilinx tool chain. Alternative to model based design approach, this work also presents an analysis on FPGA programming via high-level synthesis techniques for computationally intensive algorithms and demonstrates the importance of HLS by comparing performance-per-watt of GPUs(NVIDIA) and FPGAs(Xilinx) manufactured in the same node running standard OpenCL benchmarks. We conclude that generation of high quality RTL from OpenCL model requires stronger hardware background with respect to the MBD approach, however, the availability of a fast and broad design space exploration ability and portability of the OpenCL code, e.g. to CPUs and GPUs, motivates FPGA industry leaders to provide users with OpenCL software development environment which promises FPGA programming in CPU/GPU-like fashion. Our experiments, through extensive design space exploration(DSE), suggest that FPGAs have higher performance-per-watt with respect to two high-end GPUs manufactured in the same technology(28 nm). Moreover, FPGAs with more available resources and using a more modern process (20 nm) can outperform the tested GPUs while consuming much less power at the cost of more expensive devices.
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Bartolini, Andrea <1981&gt. "Dynamic power management: from portable devices to high performance computing." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3558/1/bartolini_andrea_tesi.pdf.

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Electronic applications are nowadays converging under the umbrella of the cloud computing vision. The future ecosystem of information and communication technology is going to integrate clouds of portable clients and embedded devices exchanging information, through the internet layer, with processing clusters of servers, data-centers and high performance computing systems. Even thus the whole society is waiting to embrace this revolution, there is a backside of the story. Portable devices require battery to work far from the power plugs and their storage capacity does not scale as the increasing power requirement does. At the other end processing clusters, such as data-centers and server farms, are build upon the integration of thousands multiprocessors. For each of them during the last decade the technology scaling has produced a dramatic increase in power density with significant spatial and temporal variability. This leads to power and temperature hot-spots, which may cause non-uniform ageing and accelerated chip failure. Nonetheless all the heat removed from the silicon translates in high cooling costs. Moreover trend in ICT carbon footprint shows that run-time power consumption of the all spectrum of devices accounts for a significant slice of entire world carbon emissions. This thesis work embrace the full ICT ecosystem and dynamic power consumption concerns by describing a set of new and promising system levels resource management techniques to reduce the power consumption and related issues for two corner cases: Mobile Devices and High Performance Computing.
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Bartolini, Andrea <1981&gt. "Dynamic power management: from portable devices to high performance computing." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2011. http://amsdottorato.unibo.it/3558/.

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Electronic applications are nowadays converging under the umbrella of the cloud computing vision. The future ecosystem of information and communication technology is going to integrate clouds of portable clients and embedded devices exchanging information, through the internet layer, with processing clusters of servers, data-centers and high performance computing systems. Even thus the whole society is waiting to embrace this revolution, there is a backside of the story. Portable devices require battery to work far from the power plugs and their storage capacity does not scale as the increasing power requirement does. At the other end processing clusters, such as data-centers and server farms, are build upon the integration of thousands multiprocessors. For each of them during the last decade the technology scaling has produced a dramatic increase in power density with significant spatial and temporal variability. This leads to power and temperature hot-spots, which may cause non-uniform ageing and accelerated chip failure. Nonetheless all the heat removed from the silicon translates in high cooling costs. Moreover trend in ICT carbon footprint shows that run-time power consumption of the all spectrum of devices accounts for a significant slice of entire world carbon emissions. This thesis work embrace the full ICT ecosystem and dynamic power consumption concerns by describing a set of new and promising system levels resource management techniques to reduce the power consumption and related issues for two corner cases: Mobile Devices and High Performance Computing.
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Ge, Rong. "Theories and Techniques for Efficient High-End Computing." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/28863.

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Today, power consumption costs supercomputer centers millions of dollars annually and the heat produced can reduce system reliability and availability. Achieving high performance while reducing power consumption is challenging since power and performance are inextricably interwoven; reducing power often results in degradation in performance. This thesis aims to address these challenges by providing theories, techniques, and tools to 1) accurately predict performance and improve it in systems with advanced hierarchical memories, 2) understand and evaluate power and its impacts on performance, 3) control power and performance for maximum efficiency. Our theories, techniques, and tools have been applied to high-end computing systems. Our theroetical models can improve algorithm performance by up to 59% and accurately predict the impacts of power on performance. Our techniques can evaluate power consumption of high-end computing systems and their applications with fine granularity and save up to 36% energy with little performance degradation.<br>Ph. D.
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Zhang, Ziming. "Adaptive Power Management for Autonomic Resource Configuration in Large-scale Computer Systems." Thesis, University of North Texas, 2015. https://digital.library.unt.edu/ark:/67531/metadc804939/.

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In order to run and manage resource-intensive high-performance applications, large-scale computing and storage platforms have been evolving rapidly in various domains in both academia and industry. The energy expenditure consumed to operate and maintain these cloud computing infrastructures is a major factor to influence the overall profit and efficiency for most cloud service providers. Moreover, considering the mitigation of environmental damage from excessive carbon dioxide emission, the amount of power consumed by enterprise-scale data centers should be constrained for protection of the environment.Generally speaking, there exists a trade-off between power consumption and application performance in large-scale computing systems and how to balance these two factors has become an important topic for researchers and engineers in cloud and HPC communities. Therefore, minimizing the power usage while satisfying the Service Level Agreements have become one of the most desirable objectives in cloud computing research and implementation. Since the fundamental feature of the cloud computing platform is hosting workloads with a variety of characteristics in a consolidated and on-demand manner, it is demanding to explore the inherent relationship between power usage and machine configurations. Subsequently, with an understanding of these inherent relationships, researchers are able to develop effective power management policies to optimize productivity by balancing power usage and system performance. In this dissertation, we develop an autonomic power-aware system management framework for large-scale computer systems. We propose a series of techniques including coarse-grain power profiling, VM power modelling, power-aware resource auto-configuration and full-system power usage simulator. These techniques help us to understand the characteristics of power consumption of various system components. Based on these techniques, we are able to test various job scheduling strategies and develop resource management approaches to enhance the systems' power efficiency.
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Zheng, Li. "Power distribution network modeling and microfluidic cooling for high-performance computing systems." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54449.

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A silicon interposer platform with microfluidic cooling is proposed for high-performance computing systems. The key components and technologies for the proposed platform, including electrical and fluidic microbumps, microfluidic vias and heat sinks, and simultaneous flip-chip bonding of the electrical and fluidic microbumps, are developed and demonstrated. Fine-pitch electrical microbumps of 25 µm diameter and 50 µm pitch, fluidic vias of 100 µm diameter, and annular-shaped fluidic microbumps of 150 µm inner diameter and 210 µm outer diameter were fabricated and bonded. Electrical and fluidic tests were conducted to verify the bonding results. Moreover, the thermal and signaling benefits of the proposed platform were evaluated based on thermal measurements and simulations, and signaling simulations. Compared to the conventional air cooling, significant reductions in system temperature and thermal coupling are achieved with the proposed platform. Moreover, the signaling performance is improved due to the reduced temperature, especially for long interconnects on the silicon interposer. A numerical power distribution network (PDN) simulator is developed based on distributed circuit models for on-die power/ground grids, package- and board- level power/ground planes, and the finite difference method. The simulator enables power supply noise simulation, including IR-drop and simultaneous switching noise, for a full chip with multiple blocks of different power, decoupling capacitor, and power/ground pad densities. The distributed circuit model is further extended to include TSVs to enable simulations for 3D PDN. The integration of package- and board- level power/ground planes enables co-simulation of die-package-board PDN and exploration of new PDN configurations.
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Tang, Kun. "Improving the Performance and Energy Efficiency for Power-constrained High Performance Computing." Diss., Temple University Libraries, 2017. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/467325.

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Computer and Information Science<br>Ph.D.<br>The continuous growth in computing capability has expedited the scientific discovery and enabled scientific applications to simulate physical phenomena for increased problem sizes. However, as the computing capability escalates, power constraints are becoming a first-order concern for high performance computing (HPC) facilities. For example, the U.S. Department of Energy has set a power constraint of 20 MW to each exascale machine. How to achieve the target performance under power constraints remains to be an issue. Therefore, efficient operation of these facilities requires power constraints to be taken into account at all layers, which potentially impacts the performance and energy efficiency. In order to improve the performance and energy efficiency for computing and storage resources under power constraints, I proposed the following three techniques. First, I developed a power-aware checkpointing model through exploring the interplay among power capping, temperature, reliability, performance, and energy efficiency. Applying the model leads to maximized performance and energy efficiency, and minimized data movements over storage systems. Second, I characterized the performance and energy efficiency of HPC workflows on heterogeneous processors. In addition, I also characterized how scientific simulation and analysis react to power capping differently and how they vary based on error resilience. Based on the characterization of HPC workflows, I developed a reliability-aware platform configuration model to determine the optimal platform configuration which includes power allocation and distribution, power capping levels, and computing scales for power-constrained HPC workflows. Third, I developed a proactive burst buffer draining scheme to minimize the I/O provisioning requirement of permanent storage systems while preserving the system I/O performance. Facing power constraints, reducing the storage provisioning level directly decreases the power consumption of storage systems. Applying the proactive burst buffer draining scheme minimizes the storage provisioning level and power consumption without compromising the storage I/O performance.<br>Temple University--Theses
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Books on the topic "High-power computing"

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Khaitan, Siddhartha Kumar, and Anshul Gupta, eds. High Performance Computing in Power and Energy Systems. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-32683-7.

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Khaitan, Siddhartha Kumar. High Performance Computing in Power and Energy Systems. Springer Berlin Heidelberg, 2013.

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Corporation, International Business Machines, ed. HPC clusters using Infiniband on IBM Power systems servers. Vervante, 2009.

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Ho, Ron, and Robert Drost, eds. Coupled Data Communication Techniques for High-Performance and Low-Power Computing. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6588-2.

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Labarta, Jesus. High-Performance Computing: 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Springer, 2008.

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Jesús, Labarta, Joe Kazuki, Sato Toshinori, and International Workshop on Advanced Low Power Systems (1st : 2006 : Cairns, Qld.), eds. High-performance computing: 6th international symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006 : revised selected papers. Springer, 2008.

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Gupta, Anshul, and Siddhartha Kumar Khaitan. High Performance Computing in Power and Energy Systems. Springer, 2012.

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Gupta, Anshul, and Siddhartha Kumar Khaitan. High Performance Computing in Power and Energy Systems. Springer, 2014.

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High Performance Computing In Power And Energy Systems. Springer, 2012.

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Ho, Ron, and Robert Drost. Coupled Data Communication Techniques for High-Performance and Low-Power Computing. Springer, 2012.

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Book chapters on the topic "High-power computing"

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Ge, Rong, and Kirk W. Cameron. "Power-Aware High Performance Computing." In Energy-Efficient Distributed Computing Systems. John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118342015.ch2.

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Khaitan, Siddhartha Kumar, and James D. McCalley. "High Performance Computing for Power System Dynamic Simulation." In Power Systems. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-32683-7_2.

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Haj-Yahya, Jawad, Avi Mendelson, Yosi Ben Asher, and Anupam Chattopadhyay. "Power Modeling at High-Performance Computing Processors." In Energy Efficient High Performance Processors. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8554-3_3.

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Borghesi, Andrea, Francesca Collina, Michele Lombardi, Michela Milano, and Luca Benini. "Power Capping in High Performance Computing Systems." In Lecture Notes in Computer Science. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-23219-5_37.

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Falcão, Djalma M. "High performance computing in power system applications." In Vector and Parallel Processing — VECPAR'96. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-62828-2_109.

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Muthukumar, P., Padma Suresh Lekshmi Kanthan, T. Baldwin Immanuel, and K. Eswaramoorthy. "FPGA Performance Optimization Plan for High Power Conversion." In Soft Computing Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1936-5_52.

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Yamaguchi, Kazuya, Takuya Hirata, and Ichijo Hodaka. "High Power Wireless Power Transfer Driven by Square Wave Inputs." In Advances in Intelligent Systems and Computing. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-23207-2_34.

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Gong, Fen, Xiangyang Xia, Shiwu Luo, and Feng Zhou. "High-Capacity Hybrid Active Power Filter for the Power Substation." In Advances in Intelligent and Soft Computing. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25185-6_13.

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Hildenbrand, Dietmar. "The Power of High-Dimensional Geometric Algebras." In The Power of Geometric Algebra Computing. Chapman and Hall/CRC, 2021. http://dx.doi.org/10.1201/9781003139003-9.

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Adhikari, Manoj Singh, Vikalp Joshi, and Raju Patel. "InGaAs MOSFET for High Power Applications." In International Conference on Intelligent Computing and Smart Communication 2019. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0633-8_136.

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Conference papers on the topic "High-power computing"

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Lee, Hoi, Chen Chen, Weijie Han, Athul M. Sudha, Navaneeth Sri Easwaran, and Jin Liu. "High-Efficiency High-Conversion-Ratio Power Delivery Circuits for Computing Applications." In 2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). IEEE, 2024. http://dx.doi.org/10.1109/bcicts59662.2024.10745680.

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Fedorov, Mike, Abdul Awwal, Adrian Barnes, et al. "NIF computing systems for ignition, high neutron yields, and future high-energy-density (HED) science." In High Power Lasers for Fusion Research VIII, edited by Constantin L. Häfner and Abdul A. Awwal. SPIE, 2025. https://doi.org/10.1117/12.3048342.

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Ishihara, Tohru, Jangwoo Kim, Kazutoshi Kobayashi, and Jose Martinez. "Panel Discussions: “Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing”." In 2025 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL CHIPS). IEEE, 2025. https://doi.org/10.1109/coolchips65488.2025.11018567.

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Marthi, Phani R. V., Suman Debnath, Steven Hahn, Harry Hughes, Rahul Mishra, and Jongchan Choi. "High-Performance Computing Based EMT Simulation: Power Grid with IBRs." In 2025 IEEE Conference on Technologies for Sustainability (SusTech). IEEE, 2025. https://doi.org/10.1109/sustech63138.2025.11025731.

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Kulshreshtha, Naman, Tapasya Patki, Jim Garlick, Mark Grondona, and Rong Ge. "Vendor-neutral and Production-grade Job Power Management in High Performance Computing." In SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis. IEEE, 2024. https://doi.org/10.1109/scw63240.2024.00231.

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Hughes, Richard J. "Quantum computing with trapped ions." In Optoelectronics and High-Power Lasers & Applications, edited by Bryan L. Fearey. SPIE, 1998. http://dx.doi.org/10.1117/12.308370.

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Myatt, Christopher J., B. E. King, D. Kielpinski, et al. "Trapped ions, entanglement, and quantum computing." In Optoelectronics and High-Power Lasers & Applications, edited by Bryan L. Fearey. SPIE, 1998. http://dx.doi.org/10.1117/12.308371.

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Kamil, Shoaib, John Shalf, and Erich Strohmaier. "Power efficiency in high performance computing." In Distributed Processing Symposium (IPDPS). IEEE, 2008. http://dx.doi.org/10.1109/ipdps.2008.4536223.

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"High-performance, power-aware computing - HPPAC." In 2009 IEEE International Symposium on Parallel & Distributed Processing. IEEE, 2009. http://dx.doi.org/10.1109/ipdps.2009.5160981.

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"High-performance, power-aware computing - HPPAC." In Distributed Processing, Workshops and Phd Forum (IPDPSW). IEEE, 2010. http://dx.doi.org/10.1109/ipdpsw.2010.5470915.

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Reports on the topic "High-power computing"

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Laros, James H.,, Suzanne M. Kelly, Kevin Pedretti, et al. High Performance Computing - Power Application Programming Interface Specification. Office of Scientific and Technical Information (OSTI), 2016. http://dx.doi.org/10.2172/1494356.

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Laros, James H., Suzanne M. Kelly, Steven Hammond, Ryan Elmore, and Kristin Munch. Power/energy use cases for high performance computing. Office of Scientific and Technical Information (OSTI), 2013. http://dx.doi.org/10.2172/1121915.

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Laros, James H.,, Suzanne M. Kelly, Kevin Pedretti, et al. High Performance Computing - Power Application Programming Interface Specification. Office of Scientific and Technical Information (OSTI), 2016. http://dx.doi.org/10.2172/1561489.

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Laros, James H.,, Suzanne M. Kelly, Kevin Pedretti, et al. High Performance Computing - Power Application Programming Interface Specification. Office of Scientific and Technical Information (OSTI), 2014. http://dx.doi.org/10.2172/1151809.

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Kelly, Suzanne, Kevin Pedretti, Ryan Grant, Stephen Olivier, Michael Levenhagen, and David DeBonis. High Performance Computing - Power Application Programming Interface Specification. Office of Scientific and Technical Information (OSTI), 2015. http://dx.doi.org/10.2172/1762048.

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Laros III, James H., David DeBonis, Ryan Grant, et al. High Performance Computing - Power Application Programming Interface Specification Version 1.4. Office of Scientific and Technical Information (OSTI), 2016. http://dx.doi.org/10.2172/1331358.

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Laros, James H., Ryan Grant, Michael J. Levenhagen, et al. High Performance Computing - Power Application Programming Interface Specification Version 2.0. Office of Scientific and Technical Information (OSTI), 2017. http://dx.doi.org/10.2172/1347187.

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Pasupuleti, Murali Krishna. Neuromorphic Nanotech: 2D Materials for Energy-Efficient Edge Computing. National Education Services, 2025. https://doi.org/10.62311/nesx/rr325.

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Abstract The demand for energy-efficient, real-time computing is driving the evolution of neuromorphic computing and edge AI systems. Traditional silicon-based processors struggle with power inefficiencies, memory bottlenecks, and scalability limitations, making them unsuitable for next-generation low-power AI applications. This research report explores how 2D materials, such as graphene, transition metal dichalcogenides (TMDs), black phosphorus, and MXenes, are enabling the development of neuromorphic architectures that mimic biological neural networks for high-speed, ultra-low-power computation. The study examines synaptic transistors, memristors, and AI-driven optimization techniques that enhance the performance of neuromorphic chips for autonomous AI, smart IoT systems, and real-time decision-making at the edge. Additionally, it discusses manufacturing challenges, economic feasibility, and policy implications related to large-scale adoption of 2D materials in nanoelectronics and semiconductor industries. Through case studies and emerging trends, this report provides a roadmap for integrating neuromorphic nanotech into mainstream AI-powered edge computing, ensuring scalability, sustainability, and high-performance intelligence for next-generation computing applications. Keywords: Neuromorphic computing, 2D materials, energy-efficient AI, edge computing, graphene, transition metal dichalcogenides, black phosphorus, MXenes, synaptic transistors, memristors, nanotechnology, low-power AI, spiking neural networks, AI-driven material discovery, quantum simulations, AI hardware optimization, semiconductor nanotech, real-time AI inference, autonomous AI, AI-powered IoT, sustainable computing.
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Elmore, Ryan, Kenny Gruchalla, Caleb Phillips, Avi Purkayastha, and Nick Wunder. Analysis of Application Power and Schedule Composition in a High Performance Computing Environment. Office of Scientific and Technical Information (OSTI), 2016. http://dx.doi.org/10.2172/1235236.

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McGarrigle, Malachy. Watchpoints for Consideration When Utilising a VDI Network to Teach Archicad BIM Software Within an Educational Programme. Unitec ePress, 2023. http://dx.doi.org/10.34074/ocds.099.

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This research identifies factors to be considered in the adoption of a virtual desktop infrastructure (VDI) accommodating the software needs of a tertiary institution. The study discusses the potential advantages and disadvantages of VDI, focusing specifically on the performance of the architectural software Archicad when used virtually. The findings will be relevant to similar programmes, such as Revit, and software used in other disciplines, especially where processing power is important. Aims discussed include reducing high-specification computers rarely used to capacity, assessing user experience, and feasibility of VDI remote access. Primarily a case study, this project centres around delivery of papers in the New Zealand Diploma of Architectural Technology programme at Unitec | Te Pūkenga that employ Archicad. Software efficiency and performance was monitored throughout teaching across numerous semesters. Incidents were logged and VDI operation tracked, especially during complex tasks such as image rendering. Load testing was also carried out to assess the implications of large user numbers simultaneously performing such complex tasks. Project findings indicate that Archicad performance depends on the design and specification of the virtual platform. Factors such as processing power, RAM allocation and ratio of users to virtual machines (VM)s proved crucial. Tasks executed by the software and how software itself uses hardware are other considerations. This research is important, as its findings could influence the information technology strategies of both academic institutions and industry in coming years. Virtual computing provides many benefits, and this project could provide the confidence for stakeholders to adopt new strategies using VDI instead of the traditional approach of computers with locally installed software applications.
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