Relevant bibliographies by topics / High-speed carry select adder (HCSA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'High-speed carry select adder (HCSA)'

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Published: 2 June 2025
Last updated: 31 July 2025

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Journal articles on the topic "High-speed carry select adder (HCSA)"

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Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

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In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing
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Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

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In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.
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S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

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<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee
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Kokilavani, V., K. Preethi, and P. Balasubramanian. "FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders." Advances in Electronics 2015 (May 27, 2015): 1–13. http://dx.doi.org/10.1155/2015/713843.

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Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work,
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each
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Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

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An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s
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Saravanakumar, Saravanakumar, Vijeyakumar Vijeyakumar, and Sakthisudhan Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (2018): 43. http://dx.doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder ha
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Saravanakumar, Vijeyakumar, and Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 43–47. https://doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder (CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA.&nbsp; The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA a
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Mitra, Partha. "Low Power High Speed SQRT Carry Select Adder." IOSR journal of VLSI and Signal Processing 1, no. 3 (2012): 46–51. http://dx.doi.org/10.9790/4200-0134651.

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Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a
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Dissertations / Theses on the topic "High-speed carry select adder (HCSA)"

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Meruguboina, Dronacharya. "EFFICIENT DESIGN OF CARRY SELECT ADDER USING DOMINO MANCHESTER CARRY CHAIN." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/theses/2125.

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Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will
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Book chapters on the topic "High-speed carry select adder (HCSA)"

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Deepthi, Kummetha, Pratheeksha Bhaskar, M. Priyanka, B. V. Sonika, and B. N. Shashikala. "Design and Implementation of High-Speed Low-Power Carry Select Adder." In Cognitive Informatics and Soft Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1056-1_41.

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VijeyaKumar, K. N., M. Lakshmanan, K. Sakthisudhan, N. Saravanakumar, R. Mythili, and V. KamatchiKannan. "Design and Implementation of High-Speed Energy-Efficient Carry Select Adder for Image Processing Applications." In Innovative Data Communication Technologies and Application. Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7167-8_49.

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Ykuntam, Yamini Devi, and M. Rajan Babu. "A Novel Architecture of High-Speed and Area-Efficient Wallace Tree Multiplier Using Square Root Carry Select Adder with Mirror Adder." In Lecture Notes in Networks and Systems. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3765-9_33.

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Rooj, Nilkantha, Snehanjali Majumder, and Vinay Kumar. "A Novel Design of Carry Select Adder (CSLA) for Low Power, Low Area, and High-Speed VLSI Applications." In Methodologies and Application Issues of Contemporary Computing Framework. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2345-4_2.

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Srividhya, G., T. Sivasakthi, R. Srivarshini, P. Varshaa, and S. Vijayalakshmi. "Enhanced and Efficient Carry Select Adder with Minimal Delay." In Advances in Parallel Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210102.

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In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improve
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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core
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Conference papers on the topic "High-speed carry select adder (HCSA)"

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Solanki, Garima, Sourav Agarwal, Tushar Mishra, and Vansh Khandelwal. "Design and Implementation of BIST logic for High Speed and Energy Efficient Carry Select Adder(CSLA)." In 2024 Third International Conference on Smart Technologies and Systems for Next Generation Computing (ICSTSN). IEEE, 2024. http://dx.doi.org/10.1109/icstsn61422.2024.10670853.

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Parmar, S., and K. P. Singh. "Design of high speed hybrid carry select adder." In 2013 3rd IEEE International Advanced Computing Conference (IACC 2013). IEEE, 2013. http://dx.doi.org/10.1109/iadcc.2013.6514477.

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Katreepalli, Raghava, and Themistoklis Haniotakis. "High Speed Power Efficient Carry Select Adder Design." In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2017. http://dx.doi.org/10.1109/isvlsi.2017.16.

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Potdukhe, Pappu P., and Vishal D. Jaiswal. "Design of high speed carry select adder using brent kung adder." In 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT). IEEE, 2016. http://dx.doi.org/10.1109/iceeot.2016.7754762.

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Simson, Aiswarya, and Deepak S. "Design and Implementation of High Speed Hybrid Carry Select Adder." In 2021 International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT). IEEE, 2021. http://dx.doi.org/10.1109/icaect49130.2021.9392452.

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Chu, Ying-Yi, Shao-Hui Shieh, Hai Feng, Hanyong Deng, Miin-Shyue Shiau, and Der-Chen Huang. "A High-Speed Carry-Select Adder with Optimized Block Sizes." In 2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID). IEEE, 2021. http://dx.doi.org/10.1109/asid52932.2021.9651488.

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Tamar, Habib Ghasemizadeh, Akbar Ghasemizadeh Tamar, Khayrollah Hadidi, Abdollah Khoei, and Pourya Hoseini. "High speed area reduced 64-bit static hybrid carry-lookahead/carry-select adder." In 2011 18th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2011). IEEE, 2011. http://dx.doi.org/10.1109/icecs.2011.6122312.

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Lakshmanan, Ali Meaamar, and Masuri Othman. "High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm." In 2006 IEEE International Conference on Semiconductor Electronics. IEEE, 2006. http://dx.doi.org/10.1109/smelec.2006.380702.

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Saxena, Pallavi. "Design of low power and high speed Carry Select Adder using Brent Kung adder." In 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA). IEEE, 2015. http://dx.doi.org/10.1109/vlsi-sata.2015.7050465.

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Joy, Mary Christina, Ansa Jimmy, Tony C. Thomas, and Manju I. Kollannur. "Modified 16 bit Carry Select and Carry Bypass Adder Architectures for High Speed Operations." In 2020 IEEE International Conference for Innovation in Technology (INOCON). IEEE, 2020. http://dx.doi.org/10.1109/inocon50539.2020.9298435.

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