Log in

Relevant bibliographies by topics / High-speed carry select adder (HCSA) / Journal articles

To see the other types of publications on this topic, follow the link: High-speed carry select adder (HCSA).

Journal articles on the topic 'High-speed carry select adder (HCSA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'High-speed carry select adder (HCSA).'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Yogayata, Shrivastava, Verma Tarun, and Jain Rita. "Design and Implementation of Low Power High Speed 32-Bit HCSA." International Journal of VLSI and Embedded Systems 5 (April 17, 2014): 893–98. https://doi.org/10.5281/zenodo.33236.

Full text

Abstract:

In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing

APA, Harvard, Vancouver, ISO, and other styles

2

Aritra, Mitra, Bakshi Amit, Sharma Bhavesh, and Didwania Nilesh. "Design of a High Speed Adder." International Journal of Scientific & Engineering Research 6, no. 4 (2015): 918–21. https://doi.org/10.5281/zenodo.33243.

Full text

Abstract:

In this paper we have compared different addition algorithms such as Ripple Carry Adder, Carry Save Adder, Carry Select Adder, Carry Look Ahead Adder & Kogge Stone Adder for different performance parameters i.e. Area Utilization, Speed of operation and Power Consumption. A high speed Adder is then designed by merging Kogge Stone & Carry Select Algorithms. The circuits have been designed using Verilog HDL & Synthesize using TSMC 180 nm standard cell. The performance parameters are obtained with the help of Cadence Encounter RTL Compiler.

APA, Harvard, Vancouver, ISO, and other styles

3

S., Nithin, and Ramesh K.B. "Design of High Speed Carry Select Adder Using Kogge-Stone and Carry-Lookahead Adders." Recent Trends in Analog Design and Digital Devices 7, no. 3 (2024): 23–33. https://doi.org/10.5281/zenodo.13709580.

Full text

Abstract:

<em>The adder is acknowledged as the fundamental component in various arithmetic and logical operations. In efforts to enhance operational efficiency, the Carry Select Adder (CSLA) has been devised. By integrating multiple high-speed adder logics within a conventional CSLA framework, operational speed is further enhanced. This study presents the design of a hybrid CSLA that amalgamates the advantages of both Kogge Stone Adder and Look Ahead Adder (CLA) methodologies to achieve superior performance. Kogge Stone Adder, distinguished for its rapid carry generation, is incorporated to bolster spee

APA, Harvard, Vancouver, ISO, and other styles

4

Kokilavani, V., K. Preethi, and P. Balasubramanian. "FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders." Advances in Electronics 2015 (May 27, 2015): 1–13. http://dx.doi.org/10.1155/2015/713843.

Full text

Abstract:

Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select adders are described with a focus on high speed. Conventionally, carry select adders are realized using the following: (i) full adders and 2 : 1 multiplexers, (ii) full adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select adders involve a combination of carry select and carry lookahead adders with/without the use of binary to excess 1 code converters. In this work,

APA, Harvard, Vancouver, ISO, and other styles

5

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." International Daily journal, Discovery Publication 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.32686.

Full text

Abstract:

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each

APA, Harvard, Vancouver, ISO, and other styles

6

Simarpreet, Singh Chawla, Aggarwal Swapnil, Anshika, and Goel Nidhi. "Design and Analysis of a High Speed Carry Select Adder." Discovery The International Daily journal 44, no. 201 (2015): 33–39. https://doi.org/10.5281/zenodo.33104.

Full text

Abstract:

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each s

APA, Harvard, Vancouver, ISO, and other styles

7

Saravanakumar, Saravanakumar, Vijeyakumar Vijeyakumar, and Sakthisudhan Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (2018): 43. http://dx.doi.org/10.11591/ijres.v7.i1.pp43-47.

Full text

Abstract:

This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder ha

APA, Harvard, Vancouver, ISO, and other styles

8

Saravanakumar, Vijeyakumar, and Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems 7, no. 1 (2018): 43–47. https://doi.org/10.11591/ijres.v7.i1.pp43-47.

Full text

Abstract:

This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder (CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA.  The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA a

APA, Harvard, Vancouver, ISO, and other styles

9

Mitra, Partha. "Low Power High Speed SQRT Carry Select Adder." IOSR journal of VLSI and Signal Processing 1, no. 3 (2012): 46–51. http://dx.doi.org/10.9790/4200-0134651.

Full text

APA, Harvard, Vancouver, ISO, and other styles

10

Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

Full text

Abstract:

Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

APA, Harvard, Vancouver, ISO, and other styles

11

Bobba, Ramyabanu, and Pooja Illa. "XOR Based Carry Select Adder for Area and Delay." International Journal of Innovative Science and Research Technology 5, no. 6 (2020): 1615–21. http://dx.doi.org/10.38124/ijisrt20jun1117.

Full text

Abstract:

Low power and area proficient high-speed circuits are the most important areas in VLSI design research. Carry select adder is one of the fastest adders with the low area and power consumption. The paper introduces a 16-bit carry select adder with an optimized multiplexer based full adder circuit using Gate Diffusion Input logic (GDI) technology. Comparison is done on Area, Power and Delay parameters. Our circuit requires only two XOR gates and a multiplexer. In this, each logic gate is designed using GDI technology. This further reduces the transistor count resulting in Area, power, delay and

APA, Harvard, Vancouver, ISO, and other styles

12

Abineetha M, Aparna Bhuvanesvari L, Aswini G, Charulatha N B, and Dr A Kirthika. "HIGH-EFFICIENT VLSI ARCHITECTURE FOR THREE OPERAND BINARY ADDER." international journal of engineering technology and management sciences 7, no. 2 (2023): 543–49. http://dx.doi.org/10.46647/ijetms.2023.v07i02.063.

Full text

Abstract:

This paper presents a VLSI architecture for a three-operand binary adder. The proposed design is based on a carry-select adder (CSLA) and Han-Carlson (HCA) adder. Carry-select adder is known for its high speed and low power consumption. The architecture uses a novel carry-in selection scheme that reduces the number of logic gates required for carry generation. Additionally, Han-Carlson (HCA), a parallel prefix two-operand adder, can also be used for three-operand addition, significantly reducing the critical path delay at the cost of supplementary hardware. In addition to perform the three-ope

APA, Harvard, Vancouver, ISO, and other styles

13

K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

Full text

Abstract:

In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

APA, Harvard, Vancouver, ISO, and other styles

14

B, S. Premananda, Bajpai Archit, Shakthivel G, and R. Anurag A. "Low power add-one circuit IPGL based high speed square root carry select adder." Indian Journal of Science and Technology 14, no. 9 (2021): 776–86. https://doi.org/10.17485/IJST/v14i9.343.

Full text

Abstract:

Abstract <strong>Background:</strong> An adder is the basic building block of any circuitry. Most ripple carry adders suffer from carry rippling which constrains its performance due to increased delay though they occupy less area. <strong>Objectives:</strong> To design and implement a high speed adder to overcome the carry rippling, which should consume less power and also operate at higher frequency. <strong>Method:</strong> Squareroot CSLA architecture is designed by replacing ripple carry adder with of Add- One Circuit (AOC) to minimize the area and carry rippling d

APA, Harvard, Vancouver, ISO, and other styles

15

Hebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

Full text

Abstract:

Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add

APA, Harvard, Vancouver, ISO, and other styles

17

Kamna, nayak, and Patra K.Pitambar. "Study of High Speed 32-Bit Data Processing Using CSLA." Association for International Journal in Computer Science & Electronics 4, no. 3 (2015): 1–9. https://doi.org/10.5281/zenodo.33244.

Full text

Abstract:

Modern applications demand extremely low power and fast speed in computer architectures for battery-operated devices like Laptop and others. In this work, the main focus is on the low power consumption and provides high speed to the processors. Low-power and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The selection behind the carry select adder is that it is very much efficient in terms of delay. The main focus in this work is to improve the speed of the 32-bit processor and in this case

APA, Harvard, Vancouver, ISO, and other styles

18

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Analysis of Low Power, Area- Efficient and High Speed Fast Adder." International Journal of Advanced Research in Computer and Communication Engineering 2, no. 9 (2013): 3705–10. https://doi.org/10.5281/zenodo.32567.

Full text

Abstract:

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

APA, Harvard, Vancouver, ISO, and other styles

19

Malti, Aryayan, and Singh Chauhan Jaikaran. "Efficient Method for Area-Efficient 32bit CSLA." International Journal of Emerging Technology and Advanced Engineering 6, no. 2 (2016): 81–85. https://doi.org/10.5281/zenodo.46811.

Full text

Abstract:

Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

APA, Harvard, Vancouver, ISO, and other styles

20

Bhati, Satyandra, Neeraj Sharma, and Meetu Nag. "Performance Analysis of High Speed and Low Power Binary Adders." IOP Conference Series: Materials Science and Engineering 1224, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1757-899x/1224/1/012026.

Full text

Abstract:

Abstract In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient addin

APA, Harvard, Vancouver, ISO, and other styles

21

J.Ponmalar, T.R.Sureshkumar, and T.Kowsalya. "Low Power, Area- Efficient and High Speed Fast Adder for Processing Element." International Journal of Innovative Research in Science, Engineering and Technology 4, no. 6 (2015): 946–54. https://doi.org/10.5281/zenodo.33096.

Full text

Abstract:

In electronics, adder is a digital circuit that performs addition of numbers. To perform fast arithmetic operations, carry select adder (CSLA) is one of the fastest adders used in many data- processing processors. The structure of CSLA is such that there is further scope of reducing the area, delay and power consumption. Simple and efficient gate – level modification is used in order to reduce the area, delay and power of CSLA. Based on the modifications, 8-bit, 16-bit, 32-bit and 64-bit architectures of CSLA are designed and compared. In this paper, conventional CSLA is compared with Mo

APA, Harvard, Vancouver, ISO, and other styles

22

B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

Full text

Abstract:

Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

APA, Harvard, Vancouver, ISO, and other styles

23

Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

Full text

Abstract:

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

APA, Harvard, Vancouver, ISO, and other styles

24

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. "High-Speed and Energy-Efficient Carry Look-Ahead Adder." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 46. http://dx.doi.org/10.3390/jlpea12030046.

Full text

Abstract:

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry t

APA, Harvard, Vancouver, ISO, and other styles

25

Bharghava ram dinesh, K., R. Vinoth, and M. V. R. Kasyap. "Design and Implementation of High Speed 32-bit MAC Unit." Journal of Physics: Conference Series 2571, no. 1 (2023): 012027. http://dx.doi.org/10.1088/1742-6596/2571/1/012027.

Full text

Abstract:

Abstract Due to the recent advances in VLSI technology, the need for efficient real time signal processing units have increased. The multiplier-and-accumulator (MAC) unit is the essential element of the digital signal processor. The aim is to design an 32-bit MAC unit that can perform multiplication and accumulation operation. Hence designing an effective MAC unit with reduced latency is necessary for better performance. The proposed MAC unit uses Carry-Select adder and Vedic multiplier which offers better speed (1.746 ns) in comparison with MAC unit designed using Ripple carry adder (1.782 ns

APA, Harvard, Vancouver, ISO, and other styles

26

M.Bommi, R., and Dr S.SelvakumarRaja. "A novel design of low-power reversible carry selects adder employing MPFA." International Journal of Engineering & Technology 7, no. 4 (2019): 4780–84. http://dx.doi.org/10.14419/ijet.v7i4.23138.

Full text

Abstract:

In VLSI technology, power dissipation is of major concern next to speed. Due to development in technology, the necessity of fast an efficient high performance processing units has become inevitable. The circuitry of Carry Select Adder (CSLA) promises rapid dispensation in ALU and furthermore optimization can be accomplished. The proposed work encompasses the makeup of reversible design of Carry Select Adder using Modified Peres Full Adder (MPFA) and Fredkin Gate (FG). It is observed that the proposed CSLA is area efficient and attained 70% low power dissipation. The reversible CSLA is synthesi

APA, Harvard, Vancouver, ISO, and other styles

27

Sireesha, P., G. Ramachandra Kumar, C. P. Bhargavi, A. Sowjanya, and P. Manga Rao. "Design and analysis of 32 bit high speed carry select adder." Journal of Physics: Conference Series 1916, no. 1 (2021): 012006. http://dx.doi.org/10.1088/1742-6596/1916/1/012006.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

Setia, Deepika, and Charu Madhu. "Novel Architecture of High Speed Parallel MAC using Carry Select Adder." International Journal of Computer Applications 74, no. 1 (2013): 32–38. http://dx.doi.org/10.5120/12851-9334.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

Full text

Abstract:

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to r

APA, Harvard, Vancouver, ISO, and other styles

30

Lim, Kaeun, Jinhyun Kim, Eunsu Kim, and Youngmin Kim. "Enhanced Dual Carry Approximate Adder with Error Reduction Unit for High-Performance Multiplier and In-Memory Computing." Electronics 14, no. 9 (2025): 1702. https://doi.org/10.3390/electronics14091702.

Full text

Abstract:

The Dual Carry Approximate Adder (DCAA) is proposed as an advanced 8-bit approximate adder featuring dual carry-out and carry-in full adders (FAs) along with an Error Reduction Unit (ERU) to enhance accuracy. The 8-bit adder is partitioned into upper and lower 4-bit blocks, connected via a dual carry-out full adder and a dual carry-in full adder. To minimize impact on the critical path, an ERU is designed for efficient error correction. Four variants of the DCAA are provided, allowing users to select the most suitable design based on their specific power, area, and accuracy requirements. The D

APA, Harvard, Vancouver, ISO, and other styles

31

Nam, Minho, Yeonhun Choi, and Kyoungrok Cho. "High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic." Microelectronics Journal 79 (September 2018): 70–78. http://dx.doi.org/10.1016/j.mejo.2018.07.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

32

Ponnusamy, Anitha, and Palaniappan Ramanathan. "Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop." Applied Mechanics and Materials 573 (June 2014): 187–93. http://dx.doi.org/10.4028/www.scientific.net/amm.573.187.

Full text

Abstract:

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. Th

APA, Harvard, Vancouver, ISO, and other styles

33

Cheng, Wei, and jianping Hu. "A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 133–42. http://dx.doi.org/10.2174/1874129001408010133.

Full text

Abstract:

This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, layouts have been made in a 0.13 􀀁m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE ba

APA, Harvard, Vancouver, ISO, and other styles

34

Anitha, M., J. Princy joice, and Mrs Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select adder Using Modified GDI Technique." International Journal of Engineering Research 4, no. 3 (2015): 127–29. http://dx.doi.org/10.17950/ijer/v4s3/309.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Premananda, B. S., Archit Bajpai, G. Shakthivel, and A. R. Anurag. "Low power add-one circuit IPGL based high speed square root carry select adder." Indian Journal of Science and Technology 14, no. 9 (2021): 776–86. http://dx.doi.org/10.17485/ijst/v14i9.343.

Full text

APA, Harvard, Vancouver, ISO, and other styles

36

Valinataj, Mojtaba, Abbas Mohammadnezhad, and Jari Nurmi. "A low-cost high-speed self-checking carry select adder with multiple-fault detection." Microelectronics Journal 81 (November 2018): 16–27. http://dx.doi.org/10.1016/j.mejo.2018.08.014.

Full text

APA, Harvard, Vancouver, ISO, and other styles

37

Bahadori, Milad, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "An energy and area efficient yet high-speed square-root carry select adder structure." Computers & Electrical Engineering 58 (February 2017): 101–12. http://dx.doi.org/10.1016/j.compeleceng.2017.01.021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

38

G, Dhanasekaran, Parthasarathy N, and Achuthan B. "High Speed, Low power and Area Efficient Processor Design Using Square Root Carry Select Adder." IOSR Journal of Electronics and Communication Engineering 9, no. 2 (2014): 14–18. http://dx.doi.org/10.9790/2834-09271418.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Uthayakumar, C., and B. Justus Rabi. "Design and Implementation of High Speed and Low Power Modified Square Root Carry Select Adder (MSQRTCSLA)." Research Journal of Applied Sciences, Engineering and Technolog 12, no. 1 (2016): 43–51. http://dx.doi.org/10.19026/rjaset.12.2302.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Joo. "VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER." American Journal of Applied Sciences 9, no. 12 (2012): 2028–45. http://dx.doi.org/10.3844/ajassp.2012.2028.2045.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Hasan, Mehedi, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, and Sharnali Islam. "A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder." Microelectronics Journal 109 (March 2021): 104992. http://dx.doi.org/10.1016/j.mejo.2021.104992.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Penchalaiah, U., and Siva Kumar VG. "Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder." International Journal of Engineering & Technology 7, no. 2.32 (2018): 243. http://dx.doi.org/10.14419/ijet.v7i2.32.13519.

Full text

Abstract:

A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of h

APA, Harvard, Vancouver, ISO, and other styles

43

Chang, Y. W., and C. Y. Cheng. "Designing a high speed-low power carry select adder circuit using carbon nano tubes based on field effect transistors." Annals of Electrical and Electronic Engineering 2, no. 2 (2019): 1–5. http://dx.doi.org/10.21833/aeee.2019.02.001.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Yen-Mou Huang and J. B. Kuo. "A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 47, no. 10 (2000): 1074–79. http://dx.doi.org/10.1109/82.877148.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Efficient Implementation of Fixed-Point MAC and Multimode MAC Blocks Based on Vedic Mathematic." Iraqi Journal for Electrical and Electronic Engineering 21, no. 2 (2025): 88–98. https://doi.org/10.37917/ijeee.21.2.9.

Full text

Abstract:

Recently, the need for high speed multiply-accumulate (MAC) operations is crucial in numerous systems like 5G, deep learning, in addition to many digital signal processing (DSP) applications. This work offers an improved MAC (I-MAC) block of different bit-size based on Vedic Mathematic and employing a hybrid adder consists of an enhanced Brent-Kung with a carry-select adder (HBK-CSLA) to achieve the sum of products for the MAC. The work is then, developed to design a new multimode fixed-point (FX-Pt) MAC block by exploiting the proposed design of the I-MAC architecture. The proposed multimode

APA, Harvard, Vancouver, ISO, and other styles

46

Ramesh Babu Chukka, Sudhakar Jyothula, Vijaya Sree Ganta ,. "DESIGN OF HIGH THROUGHPUT ADD COMPARE AND SELECT UNIT FOR LOW POWER VITERBI DECODER." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (2021): 954–60. http://dx.doi.org/10.17762/itii.v9i1.223.

Full text

Abstract:

The main purpose of this paper is to focus on the design of Viterbi Decoder (VD) with low power, which is significant for receiver section of data communication applications such as Radar, Satellite, Telephone and Automatic speech recognition. The Viterbi decoder algorithm consists of three most important blocks – Branch Metric Unit (BMU), Add Compare and Select (ACS) Unit and Survivor Memory Unit (SMU). BMU computes the metrics between the input and output state transitions. ACS unit include the Path Metric Unit (PMU), which computes the metrics with the sequence to a next state of a path and

APA, Harvard, Vancouver, ISO, and other styles

47

Tariq Hussein, Fatima, and Fatemah K. AL-Assfor. "Design Efficient Vedic-Multiplier for Floating-Point MAC Module." Iraqi Journal for Electrical and Electronic Engineering 20, no. 2 (2024): 182–89. http://dx.doi.org/10.37917/ijeee.20.2.15.

Full text

Abstract:

Multiplication-accumulation (MAC) operation plays a crucial role in digital signal processing (DSP) applications, such as image convolution and filters, especially when performed on floating-point numbers to achieve high-level of accuracy. The performance of MAC module highly relies upon the performance of the multiplier utilized. This work offers a distinctive and efficient floating-point Vedic multiplier (VM) called adjusted-VM (AVM) to be utilized in MAC module to meet modern DSP demands. The proposed AVM is based on Urdhva-Tiryakbhyam-Sutra (UT-Sutra) approach and utilizes an enhanced desi

APA, Harvard, Vancouver, ISO, and other styles

48

Mr., Vijay V. Gotmare, and Pankaj Agarwal Dr. "Design of High-Speed Hybrid Carry Select Adders using VHDL." Journal of Information, Knowledge and Research in Electronics and Communication, March 1, 2016, 1251–53. https://doi.org/10.5281/zenodo.46809.

Full text

Abstract:

Carry select adder (CSA) is a square-root time high-speed adder. CSA is one of the fastest adders used in many data processing systems to perform fast arithmetic operations. In this project we propose to design hybrid carry select adders with a focus on high speed. CSA is a compromise between the longer delay Ripple carry adder (RCA) and the shorter delay Carry look-ahead adder (CLA). Conventionally carry select adders are realize using the full adders and 2:1 multiplexers. On the other hand hybrid carry select adders involve a combination of carry select and carry look-ahead adders.In this wo

APA, Harvard, Vancouver, ISO, and other styles

49

N., Mahendran, and Vishwaja S. "Performance Analysis of High Speed Adder for DSP Applications." September 5, 2016. https://doi.org/10.5281/zenodo.1127172.

Full text

Abstract:

The Carry Select Adder (CSLA) is a fast adder which improves the speed of addition. From the structure of the CSLA, it is clear that there is opportunity for reducing the area. The logic operations involved in conventional CSLA and binary to excess-1 converter (BEC) based CSLA are analyzed to make a study on the data dependence and to identify redundant logic operations. In the existing adder design, the carry select (CS) operation is scheduled before the final-sum, which is different from the conventional CSLA design. In the presented scheme, Kogge stone parallel adder approach is used instea

APA, Harvard, Vancouver, ISO, and other styles

50

Vykuntam, Hima Bindu, Chennaiah M, and Sudhakar K. "Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique." International Journal of Scientific Research in Science and Technology, November 15, 2018, 21–26. http://dx.doi.org/10.32628/ijsrst184114.

Full text

Abstract:

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!