Relevant bibliographies by topics / High-speed clock

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'High-speed clock'

Author: Grafiati
Published: 4 June 2021
Last updated: 15 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'High-speed clock.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "High-speed clock"

1

Wu, P. B. "High-Speed Clock Network Design." IEEE Circuits and Devices Magazine 20, no. 5 (September 2004): 36. http://dx.doi.org/10.1109/mcd.2004.1343250.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

SWARTZ, ROBERT G. "ULTRA-HIGH SPEED MULTIPLEXER/DEMULTIPLEXER ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (March 1990): 73–99. http://dx.doi.org/10.1142/s0129156490000058.

Full text
Abstract:
This paper describes two circuit architectures for ultra-high speed digital multiplexers and demultiplexers. The first, Type-I, is fully synchronous and uses a system clock that matches the maximum data rate. Circuits of this type can operate at a data rate equal to the maximum operating speed of a simple digital divider. A simpler and much more powerful architecture is proposed, Type-II, that operates using a half-frequency system clock at data rates up to twice the maximum clock speed of a simple digital divider. Basic building blocks and high speed design techniques are reviewed.
APA, Harvard, Vancouver, ISO, and other styles
3

Yao, Guo Zhong, Li Si Ai, Li Zhong Shen, and Gui Yong Wang. "Research on the High-Speed Data Acquisition System Based on Clock Distribution." Advanced Materials Research 834-836 (October 2013): 1039–46. http://dx.doi.org/10.4028/www.scientific.net/amr.834-836.1039.

Full text
Abstract:
In order to digitize the signal of high frequency or ultra-high frequency, clock distribution technology with the same frequency but different phase is utilized as a solution to this difficulty. The principles of high-speed analog-to-digit converter (ADC) by the lower rate ADC module, key technology and key module of the data acquisition systems are studied. From the aspects of system architecture, clock distribution module based on the AD9520, ADC module based on the AD9480 and data processing, the design method of ultra-high-speed ADC by clock distribution mode are explored. The results show that: driving many ADC modules with serial clocks of the same frequency but different phase in parallel to sample the same signal, the sampling frequency of the ADC system is the sum of each ADC sampling frequency. Four AD9480 modules are driven by four-way 250MHz clocks with phase fault 90°, respectively. And 1GHz samples per second can be attained, which is four times of the sampling frequency by monolithic AD9480.
APA, Harvard, Vancouver, ISO, and other styles
4

KAWASAKI, Kazumasa, Takashi MIYAGUCHI, Hiroshi SAITOH, Tomoyuki KATO, Koroh KOBAYASHI, Hisayuki NAKAGAWA, and Kazunori KOBAYASHI. "E7 Development of Prototype of High Speed Clock Module(Other manufacturing-related technologies)." Proceedings of International Conference on Leading Edge Manufacturing in 21st century : LEM21 2009.5 (2009): 235–38. http://dx.doi.org/10.1299/jsmelem.2009.5.235.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kook, J., J. K. Wee, G. Moon, and S. Lee. "Clock distribution scheme for high-speed DRAM." Electronics Letters 38, no. 13 (2002): 626. http://dx.doi.org/10.1049/el:20020446.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Du, Xiu Li, Cun Da Chu, and Shao Ming Qiu. "Design and Implementation of High-Speed Clock Recovery Circuits Based on FPGA." Applied Mechanics and Materials 602-605 (August 2014): 2586–89. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2586.

Full text
Abstract:
According to the problem that the traditional clock recovery method based on FPGA can not recover the clock of higher frequency NRZ (Non-return to zero) serial data. This paper proposed a clock recovery design that adjusts the output clock earlier or later constantly according to the phase relationship between the input data and the feedback clock. The proposed design can be implemented on the FPGA without the higher operating frequency requirement meets the demand of middle and low version FPGA clients. The circuits implemented on FPGA has been downloaded to the Xilinx Virtex5 XC5VSX50T FPGA after behavioral simulation and post-route simulation, the debugging results verified that the proposed design is effective and realizable for clock recovery of higher frequency NRZ data and realizable for FPGA.
APA, Harvard, Vancouver, ISO, and other styles
7

Luo, Pu. "DLL-Based Receiver for High Speed Data Transmission." Advanced Materials Research 753-755 (August 2013): 2471–74. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2471.

Full text
Abstract:
For modern high speed DAC, receiving data reliably from FPGA is a big challenge, data-independent skew is the major problem. usually system employ data clock while transmitting LVDS data from FPGA. then LVDS data is latched by delayed data clock which generated by DLL in chip. Because DLL has a negative feedback loop, system suffer small effect of PVT variations, robustness is guaranteed. The receiving circuits were implemented in a all-digital 0.18μm CMOS technology ,occupies 0.7 mm2 of area. It operates in the frequency range of 20 MHz~600 MHz.
APA, Harvard, Vancouver, ISO, and other styles
8

MINAMI, FUMIHIRO. "High Speed Clock Design beyond 1 GHz Frequency." Journal of the Institute of Electrical Engineers of Japan 121, no. 5 (2001): 330–33. http://dx.doi.org/10.1541/ieejjournal.121.330.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Yamashita, Takao, and Satoshi Ono. "Clock frequency synchronization using high-speed digital networks." Systems and Computers in Japan 28, no. 5 (May 1997): 44–51. http://dx.doi.org/10.1002/(sici)1520-684x(199705)28:5<44::aid-scj5>3.0.co;2-o.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Li, Tie Hu, Rui Tao Zhang, Wei Dong Yang, and Guang Bing Chen. "An Analog-Digital Clock DLL Control Circuit Used for High-Speed High-Resolution Digital-to-Analog Converter." Applied Mechanics and Materials 716-717 (December 2014): 1293–97. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1293.

Full text
Abstract:
An analog-digital clock delay locked loop (DLL) control circuit is proposed to detect and adjust the analog-digital clock phase difference in real time in a 14-bit 2GSPS digital-to-analog converter (DAC). To achieve a reasonable analog-digital clock phase difference, a digitally controlled delay line (DCDL) should be able to provide a total clock delay up to 1024ps. Such fine control is realized by a control block tracking and maintaining the precise phase relationship between analog and digital clock domains. The control circuit is realized by designing a digital finite state machine (FSM) carefully. The proposed circuit is implemented in 0.18μm CMOS technology. Simulation results show that the proposed circuit performs well in various conditions in high speed data transmission applications.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "High-speed clock"

1

Desiraju, Santosh. "High Speed Clock Glitching." Cleveland State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=csu1424139368.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Namachivayam, Abishek. "High speed Clock and Data Recovery Analysis." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Sun, Lizhong. "High speed submicron CMOS oscillators and PLL clock generators." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0017/NQ48337.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Van, Dinh Anh. "High speed MMDS transceiver implementation with GPS clock synchronization." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ60213.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Sun, Lizhong Carleton University Dissertation Engineering Electronics. "High speed submicron CMOS oscillators and PLL clock generators." Ottawa, 1999.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Chattopadhyay, Atanu. "High-speed structures for dynamically clocked and multi-clock systems." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79221.

Full text
Abstract:
With an ever-decreasing minimum feature size, integrated circuits have more transistors, run faster and are larger than ever before. As a result, problems such as heat dissipation, clock generation and clock distribution are at the forefront of challenges facing chip designers today. A Globally Asynchronous, Locally Synchronous (GALS) system combined with dynamic voltage and frequency scaling is an architecture that can combat many of these issues while allowing for high performance operation. In this thesis, we investigate three distinct circuit designs compatible with, but not limited to, such a system. The first uses a novel bi-directional asynchronous FIFO to communicate between independently-clocked synchronous blocks. The second is an All-Digital Dynamic Clock Generator designed to glitchlessly switch between frequencies with very low latency. The third is a Digitally-Controlled Oscillator that can either be used stand-alone or as part of an all-digital PLL (ADPLL) to generate the global fixed frequency clocks required by the All-Digital Dynamic Clock Generator. These designs have been designed, simulated and shown to perform all the tasks required to implement a Globally Asynchronous, Locally Dynamic System (GALDS) in either a traditional ASIC design or a newer System-on-Chip (SoC).
APA, Harvard, Vancouver, ISO, and other styles
7

Ho, Wen Tsern 1977. "Clock and data recovery circuitry for high speed communication systems." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82494.

Full text
Abstract:
The maturing of the telecommunications industry has seen the development and implementation of devices that work at high frequencies of the electromagnetic spectrum. With the rapid deployment of optical networks, there is an increasing demand for low-cost and efficient communications circuitry. In order to interface with such high frequency signals at lower cost, there has been a recent push for very high frequency circuits using low-cost fabrication technologies like digital CMOS.
This thesis investigates the usage of legacy architectures and the implementation of different topologies using digital CMOS technology. Various Clock and Data Recovery Phase-Locked Loops have been implemented using a 0.18mum CMOS technology, and the process from modeling to actual implementation will be presented. The design of the components of the loop, layout issues, and the performance of the various designs will be discussed. New fully-differential CMOS designs that are optimized for high-speed operation, yet providing stable lock with minimal jitter, with a targeted operation range from 1 GHz to 7 GHz, will be described in detail, as well as their operation and optimization.
APA, Harvard, Vancouver, ISO, and other styles
8

Kumar, Daniel Prashanth. "Calibration of sampling clock skew in high-speed, high-resolution time-interleaved ADCs." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99833.

Full text
Abstract:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 157-160).
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
by Daniel Kumar.
Ph. D.
APA, Harvard, Vancouver, ISO, and other styles
9

Guo, Xiaoling. "CMOS intra-chip wireless clock distribution." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011427.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Shastri, Bhavin. "High-speed burst-mode clock and data recovery circuits for multiaccess networks." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106290.

Full text
Abstract:
Optical multiaccess networks, and specifically passive optical networks (PONs) are considered to be the most promising technologies for the deployment of fiber-to-the-premises/home/user (FTTx) to solve the problem of limited bandwidth in local area networks with a low-cost solution and a guaranteed quality of service. In a PON, multiple users share the fiber infrastructure in a point-to-multipoint (P2MP) network. This topology introduce optical path delays which inherently cause the data packets to undergo amplitude variations up to 20 dB and phase variations from −2π to +2π rad—burst-mode traffic. Consequently, this creates new challenges for the design and test of optical receivers front-ends and clock and data recovery circuits (CDRs), in particular, burst-mode CDRs (BM-CDRs). The research presented in this thesis investigates BM-CDRs, both theoretically and experimentally.We demonstrate two novel BM-CDR architectures. These BM-CDRs achieve error-free operation [bit error rate (BER) <10e−10] while providing instantaneous (0 preamble bit) clock phase acquisition for any phase step (±2π rad) between successive bursts. Instantaneous phase acquisition improves the physical efficiency of upstream PON traffic, and increases the effective throughput of the system by raising the information rate. Our eloquent, scalable BM-CDR architectures leverage the design of low complexity commercial electronics providing a cost-effective solution for PONs.The first BM-CDR (rated at 5 Gb/s) is based on phase-tracking time domain oversampling (semiblind) CDR operated at 2× the bit rate and a clock phase aligner (CPA) that makes use of a phase picking algorithm. The second BM-CDR (rate at 10 Gb/s) is based on semiblind space domain oversampling and employs a phase-tracking CDR with multiphase clocks at the bit rate and a CPA with a novel phase picking algorithm. We experimentally demonstrate these BM-CDRs in optical test beds and study the effect of channel-impairments in: (1) 5 Gb/s time-division multiplexing gigabit PON 20-km uplink; (2) 2.5 Gb/s overlapped subcarrier-multiplexing wavelength-division multiplexed PON 20-km uplink; (3) 1.25 Gb/s 1300-km deployed fiber link spanning Montreal–Quebec City and back; and (4) 622 Mb/s in a 7-user spectral amplitude-coded optical code-division multiple access 20-km PON uplink.We also provide a theoretical framework to model and analyze BM-CDRs. We develop a unified probabilistic theory of BM-CDRs based on semiblind oversampling techniques in either the time or space domain. This theory has also been generalized for conventional CDRs and N×-oversampling CDRs. Based on this theory, we perform a comprehensive theoretical analysis to quantify the performance of the proposed BM-CDRs in terms of the BER and packet loss ratio to assess the tradeoffs between various parameters, and compare the results experimentally to validate the theoretical model. This analysis coupled with the experimental results will refine theoretical models PONs, and provide input for establishing realistic power budgets.
Les réseaux optiques à accès multiple, et plus spécifiquement les réseaux optiques passifs (PONs) sont considérés comme une des technologies les plus prometteuses pour le déploiement de fibre-aux-locaux/cabinet/bâtiment/domicile/usager (FTTx) qui résout le problème de bande passante limitée dans les réseaux locaux (LAN). Les PONs atteignent cet objectif à travers une solution à faible coût. Dans un réseau PON, plusieurs usagers partagent la même infrastructure de fibre selon une topologie de réseau point-à-multipoint (P2MP). Ceci est opposé aux autres technologies d'accès actuelles qui sont basées sur une topologie de réseau point-à-point (P2P), notamment le `digital subscriber line' asymétrique ou à vitesse très élevée (xDSL) et la technologie d'accès par câble coaxial. La nature des réseaux P2MP introduit des délais dans le chemin optique qui occasionnent des variations d'amplitude allant jusqu'à 20 dB et des variations de phase de −2π à 2π rad sur les paquets de données du trafic en mode rafale (burst-mode). En conséquence, cela crée de nouveaux défis pour la conception et le test des récepteurs optiques, des circuits de récupération d'horloge et de données (CDR); en particulier, les circuits CDR en mode rafale (BM-CDR).Nous démontrons deux architectures nouvelles de BM-CDRs. Ces BM-CDRs atteignent un fonctionnement sans erreurs [taux d'erreur binaire (BER) < 10e−10] tout en fournissant une acquisition instantanée (0 bits préambule) de phase de l'horloge pour tous les pas de phases (±2π rad) entre les `bursts' successives. L'acquisition de la phase instantanée améliore l'efficacité physique du trafic en amont du réseau PON, et accroît le débit effectif du système en augmentant le taux d'information. Nos architectures éloquentes et évolutives de BM-CDRs permettent la conception avec de l'électronique commerciale de faible complexité, offrant ainsi une solution rentable pour les PONs.Le premier BM-CDR (à 5 Gb/s) que nous avons conçu et réalisé est basé sur un circuit CDR à sur-échantillonnage temporel (semi-aveugle, opéré à 2× le taux binaire) pour la suivie de phase et sur un aligneur de phase de l'horloge (CPA) qui utilise un algorithme de sélection de phase. Le deuxième BM-CDR (à 10 Gb/s) est basé sur un sur-échantillonnage spatial semi-aveugle, et emploie un circuit CDR de suivi de phase avec des horloges à multi-phases au même débit binaire que l'information, et un CPA avec un algorithme nouveau pour la sélection de phase. En plus, nous démontrons expérimentalement ces BM-CDRs sur différents bancs d'essais optiques: (1) une liaison montante de 5 Gb/s d'un réseau optique passif gigabit Ethernet (GEPON) de 20 km, basé sur un multiplexage temporel (TDM); (2) une autre liaison en amont de 2.5 Gb/s d'un réseau optique passif à multiplexage par longueur d'onde (WDM PON), basé sur un multiplexage de sous-porteuses qui se chevauchent (O-SCM); (3) un lien optique de 1300 km (aller-retour) déployé entre Montréal et Québec à 1.25 Gb/s; et (4) une liaison montante à 622 Mb/s sur un réseau optique passif de 20 km qui utilise un encodage spectral incohérent d'amplitude à accès multiple par répartition de codes (SAC-OCDMA). Nous fournissons également un cadre théorique pour modéliser et analyser les BM-CDRs. Nous développons une théorie unifiée probabiliste pour les BM-CDRs, basée sur des techniques de sur-échantillonnage semi-aveugle soit dans le domaine temporel, soit dans le domaine spatial. Cette théorie a été également généralisée pour les CDRs conventionnels et ceux à sur-échantillonnage de N fois. Sur la base de cette théorie, nous effectuons une analyse théorique. Nous évaluons le BER et le PLR des circuits BM-CDRs pour comparer les résultats avec les expériences afin de valider le modèle théorique. Cette analyse couplée avec ces résultats expérimentaux raffinera les modèles théoriques des circuits 'front-end' de mode rafale et des PONs, et fournira des données pour établir des budgets de puissance réalistes.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "High-speed clock"

1

Zhu, Qing K. High-Speed Clock Network Design. Boston, MA: Springer US, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Zhu, Qing K. High-Speed Clock Network Design. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zhu, Qing K. High-speed clock network design. Boston: Kluwer Academic Publishers, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Roermund, Arthur H. M. van, Casier Herman, and SpringerLink (Online service), eds. Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management. Dordrecht: Springer Science+Business Media B.V., 2009.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Calvert, John R. Design of a synchronous pipelined multiplier and analysis of clock skew in high-speed digital systems. Monterey, Calif: Naval Postgraduate School, 2000.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Zhu, Qing K. High-Speed Clock Network Design. Springer, 2002.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Steyaert, Michiel, Arthur H. M. van Roermund, and Herman Casier. Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management. Springer Netherlands, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Friedman, Eby G., Ivan S. Kourtev, and Baris Taskin. Timing Optimization for High-Speed Digital Circuits. Springer, 2000.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Design of a Synchronous Pipelined Multiplier and Analysis of Clock Skew in High-Speed Digital Systems. Storming Media, 2000.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

Wittman, David M. Time Dilation and Length Contraction. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780199658633.003.0007.

Full text
Abstract:
In Chapter 6, we discovered that different frames mix time and space differently; in this chapter, we will discover that speed causes time to run slowly and space to contract. Of course, the truth is a bit subtler than that, because when two frames are in relative motion each frame measures the other as the high‐speed frame where time runs slowly and space contracts.We deduce time dilation and length contraction in multiple ways: first with a light clock as a thinking tool, and then with spacetime diagrams and a new thinking tool called the symmetric frame. We also examine the experimental proof of these effects. By the end of this chapter, you will understand how time dilation and length contraction fit together with time skew in a fully consistent model that beautifully fits a wide range of evidence.
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "High-speed clock"

1

Zhu, Qing K. "Balanced Clock Routing Algorithms." In High-Speed Clock Network Design, 147–61. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_10.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Zhu, Qing K. "Microprocessor Clock Distribution Examples." In High-Speed Clock Network Design, 89–107. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zhu, Qing K. "Clock Network Simulation Methods." In High-Speed Clock Network Design, 109–24. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Zhu, Qing K. "Routing Clock On Package." In High-Speed Clock Network Design, 135–46. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_9.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Zhu, Qing K. "Clock Generation and De-skewing." In High-Speed Clock Network Design, 75–88. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Zhu, Qing K. "Low-Voltage Swing Clock Distribution." In High-Speed Clock Network Design, 125–34. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Zhu, Qing K. "Clock Tree Design Flow in ASIC." In High-Speed Clock Network Design, 163–70. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Zhu, Qing K. "Overview to Timing Constraints." In High-Speed Clock Network Design, 23–40. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Zhu, Qing K. "Sequential Clocked Elements." In High-Speed Clock Network Design, 41–56. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Zhu, Qing K. "Design Methodology for Domino Circuits." In High-Speed Clock Network Design, 57–73. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4757-3705-9_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "High-speed clock"

1

Pedrotti, Ken. "Clock recovery for high-speed optical communication." In Critical Review Collection. SPIE, 1996. http://dx.doi.org/10.1117/12.229266.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Khalil, Ragai L., Larry R. McAdams, and Joseph W. Goodman. "Optical Clock Distribution For High Speed Computers." In O-E/Fiber LASE '88, edited by James E. Hayes and James Pazaris. SPIE, 1988. http://dx.doi.org/10.1117/12.959999.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Reuben, John, Zackriya V. Mohammed, and Harish M. Kittur. "Low power, high speed hybrid clock divider circuit." In 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT). IEEE, 2013. http://dx.doi.org/10.1109/iccpct.2013.6528876.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Musa, Faisal A., and Anthony Chan Carusone. "High-speed baud-rate clock and data recovery." In 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415568.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Haller, Istvan, and Zoltan Francisc Baruch. "High-speed clock recovery for low-cost FPGAs." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5457133.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Malhotra, Gaurav, and Jalil Kamali. "Symbol spaced clock recovery for high speed links." In 2019 13th International Conference on Signal Processing and Communication Systems (ICSPCS). IEEE, 2019. http://dx.doi.org/10.1109/icspcs47537.2019.9008595.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Yong Zhang, Yaling Li, and Ting Li. "A clock circuit for high speed and high resolution pipeline ADC." In 2014 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2014. http://dx.doi.org/10.1109/edssc.2014.7061147.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Chegeni, Amin, Reza Shayanfar, Khayrollah Hadidi, and Abdollah Khoei. "Input dependent clock jitter in high speed and high resolution ADCs." In 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271948.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Cho, Jun Dong, and Majid Sarrafzadeh. "A buffer distribution algorithm for high-speed clock routing." In the 30th international. New York, New York, USA: ACM Press, 1993. http://dx.doi.org/10.1145/157485.165019.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Enomoto, Tadayoshi, Suguru Nagayama, and Nobuaki Kobayashi. "Low-Power High-Speed 180-nm CMOS Clock Drivers." In 2007 Asia and South Pacific Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/aspdac.2007.357973.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'High-speed clock' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography