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Desiraju, Santosh. "High Speed Clock Glitching." Cleveland State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=csu1424139368.
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Namachivayam, Abishek. "High speed Clock and Data Recovery Analysis." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267.
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Sun, Lizhong. "High speed submicron CMOS oscillators and PLL clock generators." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0017/NQ48337.pdf.
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Van, Dinh Anh. "High speed MMDS transceiver implementation with GPS clock synchronization." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/NQ60213.pdf.
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Sun, Lizhong Carleton University Dissertation Engineering Electronics. "High speed submicron CMOS oscillators and PLL clock generators." Ottawa, 1999.
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Chattopadhyay, Atanu. "High-speed structures for dynamically clocked and multi-clock systems." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79221.
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With an ever-decreasing minimum feature size, integrated circuits have more transistors, run faster and are larger than ever before. As a result, problems such as heat dissipation, clock generation and clock distribution are at the forefront of challenges facing chip designers today. A Globally Asynchronous, Locally Synchronous (GALS) system combined with dynamic voltage and frequency scaling is an architecture that can combat many of these issues while allowing for high performance operation. In this thesis, we investigate three distinct circuit designs compatible with, but not limited to, such a system. The first uses a novel bi-directional asynchronous FIFO to communicate between independently-clocked synchronous blocks. The second is an All-Digital Dynamic Clock Generator designed to glitchlessly switch between frequencies with very low latency. The third is a Digitally-Controlled Oscillator that can either be used stand-alone or as part of an all-digital PLL (ADPLL) to generate the global fixed frequency clocks required by the All-Digital Dynamic Clock Generator. These designs have been designed, simulated and shown to perform all the tasks required to implement a Globally Asynchronous, Locally Dynamic System (GALDS) in either a traditional ASIC design or a newer System-on-Chip (SoC).
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Ho, Wen Tsern 1977. "Clock and data recovery circuitry for high speed communication systems." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82494.
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The maturing of the telecommunications industry has seen the development and implementation of devices that work at high frequencies of the electromagnetic spectrum. With the rapid deployment of optical networks, there is an increasing demand for low-cost and efficient communications circuitry. In order to interface with such high frequency signals at lower cost, there has been a recent push for very high frequency circuits using low-cost fabrication technologies like digital CMOS.This thesis investigates the usage of legacy architectures and the implementation of different topologies using digital CMOS technology. Various Clock and Data Recovery Phase-Locked Loops have been implemented using a 0.18mum CMOS technology, and the process from modeling to actual implementation will be presented. The design of the components of the loop, layout issues, and the performance of the various designs will be discussed. New fully-differential CMOS designs that are optimized for high-speed operation, yet providing stable lock with minimal jitter, with a targeted operation range from 1 GHz to 7 GHz, will be described in detail, as well as their operation and optimization.
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Kumar, Daniel Prashanth. "Calibration of sampling clock skew in high-speed, high-resolution time-interleaved ADCs." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99833.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 157-160).
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
by Daniel Kumar.
Ph. D.
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Guo, Xiaoling. "CMOS intra-chip wireless clock distribution." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011427.
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Shastri, Bhavin. "High-speed burst-mode clock and data recovery circuits for multiaccess networks." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106290.
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Optical multiaccess networks, and specifically passive optical networks (PONs) are considered to be the most promising technologies for the deployment of fiber-to-the-premises/home/user (FTTx) to solve the problem of limited bandwidth in local area networks with a low-cost solution and a guaranteed quality of service. In a PON, multiple users share the fiber infrastructure in a point-to-multipoint (P2MP) network. This topology introduce optical path delays which inherently cause the data packets to undergo amplitude variations up to 20 dB and phase variations from −2π to +2π rad—burst-mode traffic. Consequently, this creates new challenges for the design and test of optical receivers front-ends and clock and data recovery circuits (CDRs), in particular, burst-mode CDRs (BM-CDRs). The research presented in this thesis investigates BM-CDRs, both theoretically and experimentally.We demonstrate two novel BM-CDR architectures. These BM-CDRs achieve error-free operation [bit error rate (BER) <10e−10] while providing instantaneous (0 preamble bit) clock phase acquisition for any phase step (±2π rad) between successive bursts. Instantaneous phase acquisition improves the physical efficiency of upstream PON traffic, and increases the effective throughput of the system by raising the information rate. Our eloquent, scalable BM-CDR architectures leverage the design of low complexity commercial electronics providing a cost-effective solution for PONs.The first BM-CDR (rated at 5 Gb/s) is based on phase-tracking time domain oversampling (semiblind) CDR operated at 2× the bit rate and a clock phase aligner (CPA) that makes use of a phase picking algorithm. The second BM-CDR (rate at 10 Gb/s) is based on semiblind space domain oversampling and employs a phase-tracking CDR with multiphase clocks at the bit rate and a CPA with a novel phase picking algorithm. We experimentally demonstrate these BM-CDRs in optical test beds and study the effect of channel-impairments in: (1) 5 Gb/s time-division multiplexing gigabit PON 20-km uplink; (2) 2.5 Gb/s overlapped subcarrier-multiplexing wavelength-division multiplexed PON 20-km uplink; (3) 1.25 Gb/s 1300-km deployed fiber link spanning Montreal–Quebec City and back; and (4) 622 Mb/s in a 7-user spectral amplitude-coded optical code-division multiple access 20-km PON uplink.We also provide a theoretical framework to model and analyze BM-CDRs. We develop a unified probabilistic theory of BM-CDRs based on semiblind oversampling techniques in either the time or space domain. This theory has also been generalized for conventional CDRs and N×-oversampling CDRs. Based on this theory, we perform a comprehensive theoretical analysis to quantify the performance of the proposed BM-CDRs in terms of the BER and packet loss ratio to assess the tradeoffs between various parameters, and compare the results experimentally to validate the theoretical model. This analysis coupled with the experimental results will refine theoretical models PONs, and provide input for establishing realistic power budgets.Les réseaux optiques à accès multiple, et plus spécifiquement les réseaux optiques passifs (PONs) sont considérés comme une des technologies les plus prometteuses pour le déploiement de fibre-aux-locaux/cabinet/bâtiment/domicile/usager (FTTx) qui résout le problème de bande passante limitée dans les réseaux locaux (LAN). Les PONs atteignent cet objectif à travers une solution à faible coût. Dans un réseau PON, plusieurs usagers partagent la même infrastructure de fibre selon une topologie de réseau point-à-multipoint (P2MP). Ceci est opposé aux autres technologies d'accès actuelles qui sont basées sur une topologie de réseau point-à-point (P2P), notamment le `digital subscriber line' asymétrique ou à vitesse très élevée (xDSL) et la technologie d'accès par câble coaxial. La nature des réseaux P2MP introduit des délais dans le chemin optique qui occasionnent des variations d'amplitude allant jusqu'à 20 dB et des variations de phase de −2π à 2π rad sur les paquets de données du trafic en mode rafale (burst-mode). En conséquence, cela crée de nouveaux défis pour la conception et le test des récepteurs optiques, des circuits de récupération d'horloge et de données (CDR); en particulier, les circuits CDR en mode rafale (BM-CDR).Nous démontrons deux architectures nouvelles de BM-CDRs. Ces BM-CDRs atteignent un fonctionnement sans erreurs [taux d'erreur binaire (BER) < 10e−10] tout en fournissant une acquisition instantanée (0 bits préambule) de phase de l'horloge pour tous les pas de phases (±2π rad) entre les `bursts' successives. L'acquisition de la phase instantanée améliore l'efficacité physique du trafic en amont du réseau PON, et accroît le débit effectif du système en augmentant le taux d'information. Nos architectures éloquentes et évolutives de BM-CDRs permettent la conception avec de l'électronique commerciale de faible complexité, offrant ainsi une solution rentable pour les PONs.Le premier BM-CDR (à 5 Gb/s) que nous avons conçu et réalisé est basé sur un circuit CDR à sur-échantillonnage temporel (semi-aveugle, opéré à 2× le taux binaire) pour la suivie de phase et sur un aligneur de phase de l'horloge (CPA) qui utilise un algorithme de sélection de phase. Le deuxième BM-CDR (à 10 Gb/s) est basé sur un sur-échantillonnage spatial semi-aveugle, et emploie un circuit CDR de suivi de phase avec des horloges à multi-phases au même débit binaire que l'information, et un CPA avec un algorithme nouveau pour la sélection de phase. En plus, nous démontrons expérimentalement ces BM-CDRs sur différents bancs d'essais optiques: (1) une liaison montante de 5 Gb/s d'un réseau optique passif gigabit Ethernet (GEPON) de 20 km, basé sur un multiplexage temporel (TDM); (2) une autre liaison en amont de 2.5 Gb/s d'un réseau optique passif à multiplexage par longueur d'onde (WDM PON), basé sur un multiplexage de sous-porteuses qui se chevauchent (O-SCM); (3) un lien optique de 1300 km (aller-retour) déployé entre Montréal et Québec à 1.25 Gb/s; et (4) une liaison montante à 622 Mb/s sur un réseau optique passif de 20 km qui utilise un encodage spectral incohérent d'amplitude à accès multiple par répartition de codes (SAC-OCDMA). Nous fournissons également un cadre théorique pour modéliser et analyser les BM-CDRs. Nous développons une théorie unifiée probabiliste pour les BM-CDRs, basée sur des techniques de sur-échantillonnage semi-aveugle soit dans le domaine temporel, soit dans le domaine spatial. Cette théorie a été également généralisée pour les CDRs conventionnels et ceux à sur-échantillonnage de N fois. Sur la base de cette théorie, nous effectuons une analyse théorique. Nous évaluons le BER et le PLR des circuits BM-CDRs pour comparer les résultats avec les expériences afin de valider le modèle théorique. Cette analyse couplée avec ces résultats expérimentaux raffinera les modèles théoriques des circuits 'front-end' de mode rafale et des PONs, et fournira des données pour établir des budgets de puissance réalistes.
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Li, Ran. "A wireless clock distribution system using an external antenna." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011385.
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Wei, Fangxing. "Submicron CMOS building blocks for high-speed frequency synthesis and clock recovery applications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq22130.pdf.
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Wei, Fangxing Carleton University Dissertation Engineering Electronics. "Submicron CMOS building blocks for high speed frequency synthesis and clock recovery applications." Ottawa, 1997.
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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.
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Sameni, Pedram. "Modelling and applications of MOS varactors for high-speed CMOS clock and data recovery." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/516.
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The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs.
We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.
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Bomstad, Wayne Roger. "An ultra-compact antenna test system and its analysis in the context of wireless clock distribution." [Gainesville, Fla.]: University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE0000507.
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Hong, Sung-Hwan (David) 1978. "High-speed and multi-bitrate clock and data recovery system based on half-rate clocking." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83867.
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Today's telecommunications infrastructures and consumer electronics rely largely on serial communications. Serial communications is a major form of transmitting information; therefore, faster and more cost effective methods of designing receivers are becom ing interesting research topics ([1]-[8]). This work focuses on the full design flow of an integrated clock and data recovery (CDR) system in CMOS technology, responding to this need of high-speed and cost effective circuit solutions.This thesis reports a full bottom-up design flow of a CDR system. The main challenge is to use an affordable and mainstream technology, such as the CMOS 0.18-micron technology, to implement a 6-Gbps serial receiver for land line applications. Unfortunately, the traditional full rate implementation is impossible with this CMOS technology; therefore, this problem is alleviated by exploring half-rate architectures.
The basic building blocks were first designed using TSMC's CMOS 0.18-micron technology. These gates were then assembled to create larger circuit blocks such as an edge-triggered flip flop, a double edge-triggered flip flop, a phase detectors, a phase/frequency detector, etc. Each component was characterized and then verified. The completely assembled system was simulated, verified, and then sent for fabrication. Finally, the system was tested and verified for analysis.
Eye diagram patterns were extracted from the CDR prototype circuit. Results show an opening in the eye, which suggests that the data pattern are properly recovered. The system was also successfully tested for lower bit rates. A top-down verification method was then executed in order to compare the experimental and simulation results.
The main contribution of this work is the full detailed documentation of the design flow of a CDR system using a bottom-up implementation with a top-down verification methodology. Verification methods were designed and applied in order to investigate some discrepancies in the results.
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Makon, Robert Elvis. "InP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links." Karlsruhe Univ.-Verl. Karlsruhe, 2006. http://www.uvka.de/univerlag/volltexte/2006/134/.
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Omar, Omar Jaber. "An On-Chip Memory for Testing of High-Speed Mixed-Signal Circuits." Thesis, Linköpings universitet, Elektroniska komponenter, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103800.
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Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 65 nm CMOS technology with additional requirement of 1-V supply. This design has been implemented using Cadence IC design environment. The additional advantage of the proposed testing strategy is that it requires lower number of I/O pins and avoids the large number of high speed I/O pads. It therefore also solves the problem of the bandwidth limitation that is associated with I/O transmission paths. The design of the on-chip tester based on memory contains no analog block and is implemented entirely in digital domain. In the proposed design, low frequency of 1 MHz has been used outside the chip to load the data into the memory during the write mode. During the read mode, the frequency of 625 MHz is used to read the data from the memory. A multiplexing system is used to reuse the stored data during read mode to test the intended functionality and performance. In order to convert the parallel data into serial data at high frequency at the memory output, serializer has been used. By using the frequencies of 1.25 GHz and 2.5 GHz, the serializer speeds up the data from the lower frequency of 625 MHz to the highest frequency of 5 GHz in order to test DAC at 5 GHz.
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Stridfelt, Arvid. "High Speed On-Chip Measurment Circuit." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2764.
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This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node.
It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range.
This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre.
The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.
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Calvert, John R. "Design of a synchronous pipelined multiplier and analysis of clock skew in high-speed digital systems." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2000. http://edocs.nps.edu/npspubs/scholarly/theses/2000/Dec/00Dec_Calvert.pdf.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 2000.Thesis advisors, Douglas J. Fouts, Herschel H. Loomis, Jr. Includes bibliographical references (p. 131). Also Available online.
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Kwan, Man Ho. "Electroabsorption-modulator based clock recovery circuit for high-speed optical non-return-to-zero (NRZ) signals /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20KWAN.
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Ren, Saiyu Dr. "BROAD BANDWIDTH HIGH RESOLUTION ANALOG TO DIGITAL CONVERTERS: THEORY, ARCHITECTURE AND IMPLEMENTATION." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1205948819.
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Makon, Robert Elvis [Verfasser]. "InP DHBT-based clock and data recovery circuits for ultra-high-speed optical data links / by Robert Elvis Makon." Karlsruhe : Univ.-Verl. Karlsruhe, 2006. http://d-nb.info/980655900/34.
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Angeli, Nico [Verfasser], Klaus [Akademischer Betreuer] Hofmann, and Chihao [Akademischer Betreuer] Xu. "All-Digital Clock Calibration for Source-Synchronous High-Speed I/O Links Based on Phase-to-Digital Conversion / Nico Angeli ; Klaus Hofmann, Chihao Xu." Darmstadt : Universitäts- und Landesbibliothek Darmstadt, 2020. http://d-nb.info/1216627509/34.
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Ait, Mansour El Houssain. "Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay." Thesis, Paris Sciences et Lettres (ComUE), 2018. http://www.theses.fr/2018PSLEO001/document.
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Le Radiohéliographe de Nançay est le seul instrument dédié à l'imagerie du soleil en ondes décimétriques-métriques. Il fonctionne sur le principe de l'interférométrie, en utilisant 47 antennes essentiellement réparties sur des axes est-ouest (3,2 km) et nord-sud (2,5 km). Cette étude a pour but d'explorer un nouveau concept de numérisation propre à la radioastronomie du futur, appliquée ici à l'interférométrie solaire. Elle porte sur la numérisation rapide d'un système synchronisé en sortie d'antennes. Ces aspects "numérisation rapide" et "synchronisation" sont d'une importance capitale pour les prochains radiotélescopes du futur. Ils permettent de simplifier les chaînes de réception radiofréquence et de diminuer la consommation électrique ainsi que les coûts d'entretien et de la maintenance. L'application à l'observation du soleil comporte cependant des contraintes originales, comme la grande dynamique des signaux, qui ne sont pas prises en compte actuellement dans les études en cours pour les radiotélescopes du futur. Le radiohéliographe actuel a une chaîne de réception analogique avec une numérisation centralisée. La commutation entre les différentes fréquences dans la bande 150-450~MHz est réalisée d'une façon analogique et temporelle. Ceci nécessite beaucoup de calibrations analogiques et oblige de figer la gamme des fréquences (10 fréquences de largeur 1~MHz). De plus, en interférométrie métrique, les très grandes longueurs de câbles coaxiales sont onéreuses. Les signaux transmis des antennes au récepteur sont toujours sources d'erreurs et des fluctuations importantes réduisent l'information radiofréquence. Toutefois, apporter une numérisation complète de la bande (300~MHz) permet d'avoir de la souplesse dans le traitement et l'analyse des données (résolution fréquentielle et la possibilité d'observer plusieurs bandes simultanément, traitement des parasites). Ceci engendre la nécessité d'avoir une très grande précision des horloges (0,7~ps d'erreur de phase) pour cadencer des ADC (Analog-to-Digital-Converter) large bande (1~GHz d'horloge). L'objectif principal de la thèse est d'étudier la synchronisation pour l'application à un réseau d'antennes multi-réparties. Le saut technologique ainsi induit et les concepts étudiés sont un enjeu grandissant dans les grands projets européens et internationauxThe Nançay Radioheliograph is the only instrument dedicated to the solar corona imaging in the 150-450 MHz frequency band. It operates on the principle of interferometry, using 47 antennas essentially distributed on the east-west (3.2 km) and north-south (2.5 km) axes. This study aims to explore a new technical concept for future radio astronomy, applied to solar interferometer. It deals with the rapid digitization of a synchronized system at the antenna sides. High speed digitization and high accuracy synchronization are the most important aspects for future radio telescopes. They make it possible to simplify radiofrequency reception chains and reduce their power consumption, as well as maintenance costs and complexity. The application to the observation of the sun, however, has some original constraints, such as the great dynamics of the signals, which are not taken into account in the current studies for future radio telescopes. The current radio telescope has an analog receiver with a centralized digitization. The switching time between each frequency (10 frequencies of 1 MHz width) in 150-450 MHz band analyzed introduce latency in solar images processing, also decrease the signal-to-noise ratio. In addition, in metric interferometry, the several lengths of coaxial cables in which the signal is transported from the antennas to the receiver always cause significant errors and fluctuations in the radiofrequency reception chains. Providing full digitization of the band (300 MHz) allows more flexibility in data processing and analyzing (frequency resolution and the ability to observe multiple bands simultaneously). This required high clock accuracy (0.7 ps of jitter) for ADCs clocks (1 GHz clock). Therefore, the main objective of this thesis is to reach a sub-ns global time synchronization of distributed networks such as radio interferometer array as the Nançay Radioheliograph. The technological leap thus induced is a growing challenge in major European and international projects
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Cook, Teresa L. "Developing Green One-Step Organic Reactions in the High Speed Ball Mill." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1397736534.
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Musa, Faisal. "High-speed Baud-rate Clock Recovery." Thesis, 2008. http://hdl.handle.net/1807/11120.
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Baud-rate clock recovery (CR) is gradually gaining popularity in modern serial data transmission systems since these CR techniques do not require edge-samples for extracting timing information. However, previous baud-rate techniques for high-speed serial links either rely on specific 4-bit patterns or uncorrelated random data. This work describes the modeling and design of analog filter front-end aided baud-rate CR schemes. Unlike other baud-rate schemes, this technique is not constrained by the properties of the input random data.
Firstly, the thesis develops a hardware-efficient baud-rate algorithm that requires only the slope information of the incoming random data. Called modified sign-sign minimum mean squared error (SSMMSE), this algorithm adjusts the clock sampling phase until the slope is zero through a bang-bang control loop. Secondly, the performance of a
modified SSMMSE phase detector is investigated and compared with a conventional edge-sampled phase detector. It is shown that, at severe noise levels, the proposed modified SSMMSE method has better performance compared to the edge-sampled method for equal loop bandwidths.Thirdly, the thesis investigates different hardware-efficient slope detection techniques. Both passive and active filter based slope detection techniques are demonstrated in this work. In addition to slope generation, the active filter performs linear equalization as well. However, the passive filter generates the slope information at higher speeds than the active filter and also consumes less power. The two filters are used to recover a 2-GHz clock by using an external bang-bang loop. In short, the thesis demonstrates that area and power savings can be achieved by utilizing slope information from front-end filters without compromising the performance of the CR unit.
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Li, David. "High-Speed Clocking Deskewing Architecture." Thesis, 2007. http://hdl.handle.net/10012/2993.
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As the CMOS technology continues to scale into the deep sub-micron regime, the demand
for higher frequencies and higher levels of integration poses a significant challenge for the clock generation and distribution design of microprocessors. Hence, skew optimization schemes are necessary to limit clock inaccuracies to a small fraction of the clock period. In this thesis, a crude deskew buffer (CDB) is designed to facilitate an adaptive deskewing scheme that reduces the clock skew in an ASIC clock network under manufacturing process,
supply voltage, and temperature (PVT)variations. The crude deskew buffer adopts a DLL structure and functions on a 1GHz nominal clock frequency with an operating frequency range of 800MHz to 1.2GHz. An approximate 91.6ps phase resolution is achieved for all simulation conditions including various process corners and temperature variation. When the crude deskew buffer is applied to seven ASIC clock networks with each under various
PVT variations, a maximum of 67.1% reduction in absolute maximum clock skew has been achieved. Furthermore, the maximum phase difference between all the clock signals in the seven networks have been reduced from 957.1ps to 311.9ps, a reduction of 67.4%. Overall, the CDB serves two important purposes in the proposed deskewing methodology: reducing the absolute maximum clock skew and synchronizes all the clock signals to a certain limit for the fine deskewing scheme. By generating various clock phases, the CDB can also be potentially useful in high speed debugging and testing where the clock duty cycle can be adjusted accordingly. Various positive and negative duty cycle values can be generated based on the phase resolution and the number of clock phases being “hot swapped”. For a
500ps duty cycle, the following values can be achieved for both the positive and negative duty cycle: 224ps, 316ps, 408ps, 592ps, 684ps, and 776ps.
30
Abiri, Behrooz. "High Speed Clock and Data Recovery Techniques." Thesis, 2011. http://hdl.handle.net/1807/30162.
Full textAbstract:
This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques.
The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly.
The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition it receives. The phase interpolator uses the inherent timing information in the data transition to rotate the phase of a reference clock and align it with the incoming data edge. The feasibility of the concept is demonstrated through fabrication and measurements.
31
Wang, Chih-Yong, and 王志傭. "Clock Synchronizer for High Speed Digital Systems." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/71191213067590937880.
Full textAbstract:
碩士國立臺灣大學
電機工程學系
86
In this thesis, two architectures of the clock synchronizer that delivers synchronous clock to multiple targets in high-speed digital systems are realized. Based on the consept of delay locked loop, a digital controlled delay line is used to compensate for the various clock propagation delay caused by various environmental conditions.
32
Chu, Shao-Cheng, and 朱劭正. "1-4GHz DLL-Based High Speed Clock Generator." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/95187919441115238455.
Full textAbstract:
碩士國立清華大學
電機工程學系
103
In this work we try to extend the maximum operating frequency achievable by all-digital delay-locked loop (DLL) based frequency multiplication circuit to support a high-speed range of 1GHz to 4GHz, to be used by our in-house radar system on chip (SoC). This goal is achieved by an innovative architecture in which an 8 phases of 1GHz clock signals pre-generated using techniques proposed in [12] and [13] are combined to form the waveform of the final target clock signal. Post-layout simulation result shows that the frequency error of the generated 4GHz clock signal is below 0.01% with a 7.48ps RMS-jitter, and the active area and the power consumption is 0.104mm2 and 12.67mW respectively.
33
Cheng, Sheng Huai, and 鄭聖懷. "A High Speed DLL-Based Clock Generator With High Multiplication Ratio." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/sq6wse.
Full textAbstract:
碩士華梵大學
電子工程學系碩士班
104
In recent year,Duo to the advence of technology and the scale integration development.Electronic products have increasing day by day.So the requirement of communication scale integration is increase.The Phase-Locked Loop have been used in these circuit.The electronic products: television,ratio...etcare controled by Phase-LockedLoop.The structure of Phase-Locked Loop as follow,Phase Frequency Detector,Charge Pump,Loop Filter,Voltage Control Oscillator,Frequency Divider. In this thesis,Section two is produce the Phase-Locked Loop in mathematical model;Section three is realize the basic of Phase-Locked Loop by TSMC 0.18um 1P6M CMOS.Loop Filter is Exteral the purposeis avoid some kind of the effect;Section four is Design A High Speed DLL-Based Clock Generator With High Multiplication Ratio by TSMC 0.18um 1P6M CMOS.This circuit use two Delay-Locked Loop.The point in thisthesis is the second of Edge Combiner,the structure is similar to Ring VCO.Comparing to the traditional Delay-Locked Loop,it can generate high frequence and the chip area is smaller than the traditional Delay-Locked Loop;Section five is conclusion.
34
Tyshchenko, Oleksiy. "Clock and Data Recovery for High-speed ADC-based Receivers." Thesis, 2011. http://hdl.handle.net/1807/27606.
Full textAbstract:
This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.
35
Cheng, Chun-Hua, and 程駿華. "Resource Binding of High-Speed Low-Power Nonzero Clock Skew Circuits." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/02553981352341947047.
Full textAbstract:
博士中原大學
電子工程研究所
97
High speed and low power are two important objectives in the design of edge-triggered circuits. It is well known that the clock skew can be utilized as a manageable resource for high speed and low power. To the best of our knowledge, the circuit is never optimized for utilizing the clock skew in the high-level synthesis stage. In this dissertation, we study resource binding of high-speed low-power nonzero clock skew circuits. First, we study the simultaneous application of clock scheduling and register binding for clock period minimization. Then, we study the simultaneous application of clock scheduling, power gating implementation selection, and resource binding for standby leakage current minimization. Finally, benchmark data consistently show that our approaches achieve very good results.
36
Liang, Che-Fu, and 梁哲夫. "Design of High-Speed CMOS Clock Generation and Data Recovery Circuits." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51660410063205011291.
Full textAbstract:
博士國立臺灣大學
電子工程學研究所
95
ABSTRACT With the progress of the CMOS technologies and the increasing demand for high-speed data communications, new specifications utilizing wider bandwidth than before spawns and the needs for high-performance analog circuits augment as well. The long-standing phase-locked loop (PLL) and its high-speed applications play major roles in these designs. Though relating techniques for PLL have prospered for years, new system architectures and circuit topologies are still desired to overcome the ever-increasing speed limitation. Hence, in this dissertation we focus on the design and application of phase-locked systems for high-speed wireless or wire-line applications, including clock generation and data recovery circuits. Several system architectures and circuit topologies are proposed to alleviate the design bottleneck on high-speed CMOS transceivers. First, a digital technique with auto-tracking ability is presented to calibrate the current mismatch of the charge pump in phase-locked systems. A 5GHz frequency synthesizer is used to justify the proposed calibration technique. It has been has been implemented in 0.18µm CMOS. The measured output spur is suppressed by 5.35dB at 5.2GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110dBc/Hz at an offset frequency of 1MHz. Next, a 14-band frequency synthesizer for ultra-wideband (UWB) applications has been implemented in 0.18µm CMOS. The unwanted spurs due to frequency mixing are at least –35dB lower than the output carriers by using a quadrature divide-by-3 circuit and a two-stage single-sideband mixer. The core circuit area is 1.5 mm2 and total power consumption is 160mW. Hereafter, a 10Gbps inductorless burst-mode clock and data recovery (BMCDR) circuit using a gated digital-controlled oscillator has been fabricated in 0.18µm CMOS. The digitally frequency-calibrated architecture is adopted to save the power consumption and chip area. The CDR circuit occupies an active area of 0.16mm2 and draws 36mW from a 1.8V supply. The measured rms jitter and peak-to-peak jitter is 8.5ps and 42.7ps, respectively. With the knowledge of BMCDR circuits, a jitter-tolerance-enhanced 10Gb/s clock and data recovery (CDR) circuit is presented. By using a gated-digital-controlled oscillator (GDCO), the proposed GDCO-based phase detector achieves a wide linear range and its jitter tolerance is enhanced by a factor of 2 without sacrificing the jitter transfer. The prototype chip has been fabricated in 0.13µm CMOS and consumes 60mW from a 1.5V supply. It occupies an active area of 0.36mm2. Measurements on the testchip demonstrate an rms jitter of 0.96ps and a peak-to-peak jitter of 7.11ps with a 27-1 PRBS. Finally, we conclude this dissertation.
37
Liu, Ming-Chung, and 劉明忠. "High-Speed Injection-Locking Burst-Mode Clock and Data Recovery Circuit." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/06481549798002062441.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
95
A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscillators. A frequency-monitoring mechanism is employed to ensure a close matching between the VCO natural frequency and data rate. Fabricated in 90-nm CMOS technology, this circuit achieves a bit error rate of less than 10-9 in both continuous (PRBS of 231-1) and burst modes while consuming 175 mW from a 1.5-V supply.
38
Silva, Nelson. "Power reduction of a CMOS high speed interface using Clock Gating." Dissertação, 2013. http://hdl.handle.net/10216/76306.
Full text
39
Liang, Che-Fu. "Design of High-Speed CMOS Clock Generation and Data Recovery Circuits." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1907200712393400.
Full text
40
Liu, Ming-Chung. "High-Speed Injection-Locking Burst-Mode Clock and Data Recovery Circuit." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1907200717110800.
Full text
41
Silva, Nelson Tiago Lopes da. "Power reduction of a CMOS high speed interface using Clock Gating." Dissertação, 2013. https://repositorio-aberto.up.pt/handle/10216/68024.
Full text
42
Silva, Nelson Tiago Lopes da. "Power reduction of a CMOS high speed interface using Clock Gating." Master's thesis, 2013. https://repositorio-aberto.up.pt/handle/10216/68024.
Full text
43
Li, Jinghua. "Design of clock data recovery IC for high speed data communication systems." 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2396.
Full textAbstract:
Demand for low cost Serializer and De-serializer (SerDes) integrated circuits has
increased due to the widespread use of Synchronous Optical Network (SONET)/Gigabit
Ethernet network and chip-to-chip interfaces such as PCI-Express (PCIe), Serial
ATA(SATA) and Fibre channel standard applications. Among all these applications,
clock data recovery (CDR) is one of the key design components. With the increasing
demand for higher bandwidth and high integration, Complementary metal-oxidesemiconductor
(CMOS) implementation is now a design trend for the predominant
products.
In this research work, a fully integrated 10Gb/s (OC-192) CDR architecture in
standard 0.18
μ
m CMOS is developed. The proposed architecture integrates the typically
large off-chip filter capacitor by using two feed-forward paths configuration to generate
the required zero and poles and satisfies SONET jitter requirements with a total power
dissipation (including the buffers) of 290mW. The chip exceeds SONET OC-192 jitter
tolerance mask, and high frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231-1.The implementation is the first fully integrated 10Gb/s
CDR IC which meets/exceeds the SONET standard in the literature.
The second proposed CDR architecture includes an adaptive bang-bang control
algorithm. For 6MHz sinusoidal jitter modulation, the new architecture reduces the
tracking error to 11.4ps peak-to-peak, versus that of 19.7ps of the conventional bangbang
CDR. The main contribution of the proposed architecture is that it optimizes the
loop dynamics by adjusting the bang-bang bandwidth adaptively to minimize the steady
state jitter of the CDR, which leads to an improved jitter tolerance performance.
According to simulation, the jitter performance is improved by more than 0.04UI,which
alleviates the stringent 0.1UI peak to peak jitter requirements in the PCIe/Fibre
channel/Sonet Standard.
44
Qi-Wei, Kuo. "Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1506200515305300.
Full text
45
Chen, Way-Yu, and 陳威宇. "SAW Based Half Rate Clock Recovery for High Speed Serial Data Transmission." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32295505920248976616.
Full textAbstract:
碩士國立交通大學
電信工程系所
96
The purpose of this thesis is to implement a clock and data recovery (CDR) for Stratum 3. The bit rate is 1.244Gb/s for OC-24 by using TSMC 0.18um CMOS process. The voltage controlled SAW Oscillator (VCSO) is designed for low phase noise application. The low pass loop filter and SAW resonator are external connected. The loop bandwidth is around 1KHz. The necessitate phase shift in VCSO is describe in two parts. The first is external connected π network and the other is internally integrated. The MATLAB and HSPICE are used for behavior and circuit level simulation, respectively. The VCSO is successfully combined into CDR. The measured RMS jitter of retime clock is 1.024ps and 0.88ps for external and integrated phase shifter, respectively. The power consumptions are 30mW and 143mW.
46
Kuo, Qi-Wei, and 郭其偉. "Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/59909025329939451082.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
93
In this thesis, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18um bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purposes, and use a post-manufacture tunable clock structure that manipulates the clock at post-fabrication stage to compensate for the process dependent violation to the timing. Simulation results have shown that the substrate-bias optimization results in a 37% of power delay improvement and utilization of tunable delay elements achieve 50 ps of almost linear clock tunability. A phase-locked loop and simple testing circuit also integrate into the chip for timing robustness and measurement purpose. Experiment results show the adder can successfully operate at 2.56GHz working frequency with 1.8V supply voltage.
47
Hung, Cheng-Liang, and 洪政亮. "On Techniques of Clock Generator Used in High-Speed Wireline Transmission Systems." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/z3tahe.
Full textAbstract:
博士國立中央大學
電機工程學系
103
Advance in integrated circuit (IC) fabrication technology facilitates the high-speed transmission of data to be upward evolved into several gigabits per second (Gb/s). The high-speed serial link technology is the major technique in modern data transmission. It is widely employed in wireline SerDes applications. In the overall high-speed serial link systems, however, the performance depends crucially on the quality and precision of the essential timing clock generator. Thus, a phase-locked loop (PLL) or a spread-spectrum clock generator (SSCG) plays an important role in such critical building block for clock generation. As the transmitted data rate has been upgraded into milti-Gb/s, the signal of the data launched by the transmitter (TX) accompanies the higher order harmonics. It results in the power-radiated electromagnetic interference (EMI) issue and may stringently affect the other equipment in the vicinity. To address this issue, this dissertation presents a 6-GHz triangular-modulated SSCG based on a fractional-N PLL in a 90-nm CMOS process. The proposed phase-rotating technique implements the spread-spectrum clocking (SSC) by modulating the fractional-N ratios. The presented technique effectively compensates the instantaneous timing error and shows the ignorable quantization error. Unlike the delta-sigma (ΔΣ) technique commonly used for SSCGs, the proposed SSCG realizes non- dithered fractional division ratios. It shows that the deliberate phase jump stemming from the ΔΣ control could be dismissed. In terms of SSC, this approach suppresses the RMS jitter to be less than 1 ps, showing a significant improvement in the jitter performance. In the current wireline SerDes application, it evolves the coexistence of several specification generations, and covers the data rate range of several Gb/s. As a result, a wide range clock generator to support multi-specification generations is desirable, and thus, the sub-building block of the clock generator, i.e., the voltage-controlled oscillator (VCO), plays the critical role. This dissertation presents a wide frequency tuning range inductor- capacitor-based VCO (LC-VCO) with an active inductor in a 90-nm CMOS process. The proposed LC-VCO is intended to be flexible without redesign for several new-generation wireline SerDes interfaces. The wide operating frequency makes the clock generator applicable to the multistandards. As a result, the proposed active inductor shows a quality factor, i.e., Q, enhancement technique for the reduction in the loss from the active inductor, deriving an appropriate phase noise of –105 to –118 dBc/Hz at a 1-MHz offset over the entire tuning range of 0.9 to 8 GHz (160%). In addition, the other essential sub-building block is the frequency divider (FD). It implies that the FD must process the signal operating at the highest clock frequency. Thus, this dissertation presents a high-speed power-efficient programmable frequency divider with a hybrid integer/fraction modulus steps in a 90-nm CMOS. Based on the proposed divider cell used in the multi-modulus divider (MMD), the FD easily realizes the flexible modulus 1- or 0.5-step-size MMD, showing the potential merit of the –6-dB suppressed quantization noise. In addition, by the embodiment of active-inductor-based digital logic cells with a self-power-saving scheme in the divider, the capabilities of high-speed, all-digital operation and good power-efficient are derived. Operating at 6.35 GHz, the perfectible power efficiency is 2.12 GHz/mW. As a result, integrating the advanced technique that presented, the dissertation also presents a 5-GHz, dual SSC mechanism SSCG. Meanwhile, a similar USB 3.1 10 Gb/s compliance test is set up for the demonstration of the SSCG jitter measurement. Such work might be appropriate for the new-generation of the high-speed wireline SerDes interfaces.
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Yang, Zong-Xi, and 楊宗熙. "A LOW POWER ADPLL-BASED FREQUENCY SYNTHESIZER FOR HIGH SPEED CLOCK GENERATION." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/99909741280710529747.
Full textAbstract:
碩士國立交通大學
電子工程系所
94
This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design. By using the new type digitally controlled delay element (DCDE), a digitally controlled oscillator (DCO) with characteristics of its monotonicity is presented, which makes the DCO design more straightforward. Besides, a new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is also presented. The proposed ADPLL-based frequency synthesizer has been designed with TSMC 0.13um technology model. It can operate from 300 MHz to 1 GHz, and achieve frequency acquisition within sixteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120 ps. Total power dissipation of the ADPLL-based frequency synthesizer is 3.1 mW at 1 GHz with a 1.2 V power supply. With the specification, it could be used for high speed clock generation in high speed DSPs applications.
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Bhatnagar, Rohit, S. Venkataramanaiah, and Anand Rajagopalan. "A Model for Contingent Manpower Planning: Insights from a High Clock Speed Industry." 2003. http://hdl.handle.net/1721.1/3747.
Full textAbstract:
Intense competitive pressures have led to compressed product life cycles and frequent introduction of new products. This creates demand volatility and a consequent pressure on manufacturing to meet this variable demand. In this paper we model the manpower planning issues for a computer manufacturer during the product introduction phase when a quick ramp-up of production to meet rapidly increasing demand is a key requirement. A mix of permanent and contingent workers with different skill sets is considered. Some important issues addressed in this research are (a) how to assign workers with different skills to maximize production (b) what is the induction rate of contingent workers to achieve the desired ramp-up and (c) what are the key decision factors that impact manufacturing performance An LP model is proposed to minimize overall costs subject to complex scheduling, skills, and learning rate requirements. Our analysis indicates that cost of induction of contingent workers, overtime cost premium, and the amount of overtime have significant impact on performance. The findings of the study will be useful to managers in planning and allocation of workers of different skills to various manufacturing processes and to determine the optimal number of contingent workers to induct.Singapore-MIT Alliance (SMA)
50
Lee, Chien-Hsi, and 李建錫. "All Digital Clock and Data Recovery Circuit Architecture for High Speed Serial Link." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/82174257562981596897.
Full textAbstract:
碩士國立中央大學
電機工程研究所
92
In recent years, communication networks can provide high bit-rate transport over a shared medium with a serial line or link, such as passive optical networks, cable television networks (fiber, coaxial or hybrid), digital television, and wireless networks. These shared-medium networks typically use time, frequency or code division multiplexing to transport data signals from a central terminal to several remote customer terminals and from the customer terminals to the central terminal. Among them, time division multiple access (TDMA) is characterized by non-continuous or burst mode data transmission. Traditionally, clock and data recovery (CDR) methodologies are provided for communications systems receiving continuous data streams that have enriched spectra at the sampling frequency. CDR is a useful functionality in high-speed transceivers. The received data are asynchronous and noisy, thus requiring that a clock be extracted for allowing synchronous operations. The data also need to be retimed so that jitter accumulated during data transmission can be removed. The over-sampling techniques and phase picking algorithm are applied in this work. In addition, we try to give more creativity in the changing the architectures. In other phase picking methods, multiple bits are sampled in parallel to form a sliding window and have an average effect on the phase detection. The size of such a window defines how much information is extracted from the input data. It is a fixed design parameter. The bigger window size is suitable for the high frequency noise environment; the smaller size window has a better acquisition speed. In this thesis, two all digital approaches of timing recovery techniques have been proposed. After the system level simulations of the two proposed methods, we can specify the system parameters and map to the real blocks in the circuit level. Both of them have been realized with tsmc 0.18μm 1P6M CMOS technology.