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Dissertations / Theses on the topic 'High speed DSP'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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1

Alexander, Steven Wilson. "Efficient arithmetic for high speed DSP implementation on FPGAs." Thesis, Connect to e-thesis, 2007. http://theses.gla.ac.uk/856/.

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Thesis (Eng.D.) - University of Glasgow, 2007.<br>Eng.D. thesis submitted to the Faculty of Engineering, Department of Civil Engineering, University of Glasgow, 2007. Includes bibliographical references. Print version also available.

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McBride, Justin D. (Justin Donald) 1980. "High speed DSP implementation in run-time partially reconfigurable FPGAs." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/16982.

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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Includes bibliographical references (leaves 99-100).<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architect

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3

Zhu, Qiwei. "BERT and FFT measurement systems for high-speed communications and magnetometry." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-149321.

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This master thesis presents the development and implementation of two digital systems based on Field-programmable Gate Array (FPGA): a Bit Error Rate Testing (BERT) system for an Optical Communication (OCOM) application, and a Digital Signal Processing (DSP) system for a Spin-Dependent Tunneling Magnetometer (SDTM). Both applications are intended for space and currently under development at the Ångström Space Technology Center (ÅSTC). The DSP system samples analog signals and applies a Fast Fourier Transform (FFT) for to provide frequency spectrum analysis. The report covers detailed system de

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4

Imran, Muneeb. "Contact-Less High Speed Measurement over Ground with 61 GHz Radar Sensor." Master's thesis, Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-212611.

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Conventional FMCW radar principle was implemented on Symeo 61 GHz LPR®-1DHP-R radar sensor system. There were few limitations of the FMCW implementation which needed to be removed. First, target separation in multi target environment was not possible for objects at same distance. For example, there are two targets, one is moving and one is static. When the moving target approaches the static target and becomes parallel to static target, which means they are at the same distance. At this point, the system is unable to distinguish between two targets. Second, high resolution in velocity measurem

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zhao, limei. "NEW OPTIMAL HIGH EFFICIENCY DSP-BASED DIGITAL CONTROLLER DESIGN FOR SUPER HIGH-SPEED PERMANENT MAGNET SYNCHRONOUS MOTOR." Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4071.

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This dissertation investigates digital controller and switch mode power supply design for super high-speed permanent magnet synchronous motors (PMSM). The PMSMs are a key component for the miniaturic cryocooler that is currently under development at the University of Central Florida with support from NASA Kennedy Space Center and the Florida Solar Energy Center. Advanced motor design methods, control strategies, and rapid progress in semiconductor technology enables production of a highly efficient digital controller. However, there are still challenges for such super high-speed controller des

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6

Elkhomri, Othman. "DSP IMPLEMENTATION OF DC VOLTAGE REGULATION USING ADAPTIVE CONTROL FOR 200 KW 62000 RPM INDUCTION GENERAT." Master's thesis, University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2926.

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The thesis discusses the development of closed loop system to control the DC voltage for 200 kW induction generator rated at a speed of 62000 RPM under different load conditions. The voltage regulation has been implemented using PI controller. A gain scheduling control algorithm has been developed to select the appropriate controller gains with respect to the generator load. Further, a relationship between the generator loads and the controller gains has been established. This relationship has been modeled using adaptive control technique to vary the gains automatically at any load condition.

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7

Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughp

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8

Xu, Tianhua. "DSP based Chromatic Dispersion Equalization and Carrier Phase Estimation in High Speed Coherent Optical Transmission Systems." Doctoral thesis, KTH, Optik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-94835.

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Coherent detection employing multilevel modulation formats has become one of the most promising technologies for next generation high speed transmission systems due to the high power and spectral efficiencies. Using the powerful digital signal processing (DSP), coherent optical receivers allow the significant equalization of chromatic dispersion (CD), polarization mode dispersion (PMD), phase noise (PN) and nonlinear effects in the electrical domain. Recently, the realizations of these DSP algorithms for mitigating the channel distortions in the coherent transmission systems are the most attra

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9

Bae, Cheolyong, and Madhur Gokhale. "Implementation of High-Speed 512-Tap FIR Filters for Chromatic Dispersion Compensation." Thesis, Linköpings universitet, Datorteknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-153435.

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A digital filter is a system or a device that modifies a signal. This is an essential feature in digital communication. Using optical fibers in the communication has various advantages like higher bandwidth and distance capability over copper wires. However, at high-rate transmission, chromatic dispersion arises as a problem to be relieved in an optical communication system. Therefore, it is necessary to have a filter that compensates chromatic dispersion. In this thesis, we introduce the implementation of a new architecture of the filter and compare it with a previously proposed architecture.

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10

Parks, Jeremy. "A Texas Instruments C33 DSP PCI platform for high-speed real-time implementation of IEEE802.11a Wireless LAN algorithms." [Gainesville, Fla.] : University of Florida, 2003. http://purl.fcla.edu/fcla/etd/UFE0002880.

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11

Kwong, Kelvin Kam Leung. "Implementation of DSP carrier recovery using all-digital phase-locked loop with vector rotation techniques for high speed 8-PSK modems." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ36046.pdf.

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12

Morávek, Lukáš. "Řídicí modul BLDC motoru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-242079.

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Diploma thesis describes design and realization of hardware and software for controlling and regulation of the high-speed drive with BLDC motor, which will serve as a spindle for CNC milling machine. The thesis described in detail the schematic design and the design of printed circuit board of the power part, control part and power supply part of the three-phase transistor inverter controlled by DSP processor. It is also described in detail program of DSP processor for controlling and regulation of the BLDC motors, which the function is verified by the final measurements. The result of Diploma

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13

Bengtson, Håkan. "High speed CMOS optical receiver /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek904s.pdf.

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14

Mu, Fenghao. "Design of large scale and high speed integrated systems /." Linköping : Univ, 1998. http://www.bibl.liu.se/liupubl/disp/disp98/tek564s.htm.

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15

Löwenborg, Per. "Asymmetric filter banks for mitigation of mismatch errors in high-speed analog-to-digital converters /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek787s.pdf.

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16

Andersson, Nils-Eric. "Structure and properties of thick plate and near surface properties after high speed machining af AA7010 /." Linköping : Univ, 2003. http://www.bibl.liu.se/liupubl/disp/disp2003/tek822s.pdf.

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17

Kuo, Chien-Nan, and 郭建男. "High-Speed and Low-Power Fixed-Width Multipliers for DSP Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/66816745053695683893.

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碩士<br>國立中正大學<br>電機工程研究所<br>92<br>Multiplier is an important kernel of Digital Signal Processors (DSP) because it typically determines the performance and area of the chips. In some DSP applications, precision can be sacrificed, and the multiplication can be performed by the so-called fixed-width multiplier, which has the advantage of small area. This thesis proposes the Left-to-Right Array-type Fixed-Width Multiplier, which owns the characteristics of small area, high speed and low power. When designed with a cell-based approach, a 32x32 Left-to-Right Fixed-Width Multipli

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18

Ho, Chang-Yu, and 何昌祐. "DSP-Based Fully Digital High Speed Control of AC Induction Motors." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/55358350141000679073.

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碩士<br>國立交通大學<br>控制工程系<br>82<br>This thesis presents the design and implementation of a fully digital-controlled ac induction servo drive by using a digital signal processor (DSP). A high speed control method is proposed to operate an ac induction motor up to triple its base speed with high performance of transient and steady-state responses. An indirect field-oriented vector control scheme with software current feedback loop is employed to perform the fast response current decoupling contro

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19

Cheng, Ying-Kuang, and 鄭螢光. "High-Speed DSP Circuit Design using Frequency Overscaling and Subword Detection Processing." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/37796099239938960195.

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碩士<br>國立清華大學<br>電機工程學系<br>97<br>The high speed circuit design is an imperative issue for advanced communication systems. Because of the requirement of high speed and high quality data transmission, high speed circuit design becomes an important research field. In the thesis, we utilize the frequency overscaling (FOS) technique to increase the operating frequency of the circuit. However, the FOS causes timing violation and degrades SNR performance greatly. In order to alleviate SNR degradation, we employ two techniques to combat the error noise generated by the timing violation. One is the sys

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20

Wu, Kai-Ping, and 吳凱平. "MAC Module Design and Implementation with DSP for High-speed Wireless LAN." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/7nm6jh.

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碩士<br>南台科技大學<br>電子工程系<br>90<br>In this thesis, we propose the design and implementation of MAC module with programmable DSP for a high-speed wireless LAN (WLAN). Our system operates in the 2.4 GHz ISM band and we employ DSP chip TMX320C6211 as the central controller to implement the MAC module which is based on IEEE 802.11b WLAN standard. Integrating MAC module with the baseband and RF front-end modules implemented with Intersil chips, a maximum speed of 11Mbps can be achieved. The high-speed and low cost properties of the programmable DSP chip TMX320C6211can meet the requirement of

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21

Chen, Chien-Hung, and 陳建宏. "Design and Implementation of High Speed Banknotes Recognition System Based on DSP Architecture." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/2s6u3n.

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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>101<br>The circulating currencies, there will be damaged or soiled situations. In order to reduce the waste of human resources and misjudgment, this study established a banknote recognition system based on DSP architecture to do denomination, into banknote direction, angular detection, and the old and the new banknotes recognition for NT dollars. There are six modules in this banknote recognition system, including feeding module, thickness of discrimination module, magnetic of discrimination module, image recognition module, delivery module and user interface modu

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22

Brocklesby, Andrew K. (Andrew Kenneth). "High speed DSP and A to D in an ice radar logging application." Thesis, 1999. https://eprints.utas.edu.au/19074/1/whole_BrocklesbyAndrewKenneth1999_thesis.pdf.

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For some time the Glaciology section of the Australian Antarctic Division has operated a land-based radar to measure the depth of glacial ice in Antarctica. The radar was mounted on a sled and towed around the Lambert glacier by bulldozer at 5km per hour. High power radio frequency pulses are transmitted down into the glacial ice, propagate through the ice and reflect off the bedrock below. The reflected pulses are picked up by a receiver, amplified and passed on to a signal processing section. The waveforms from the signal processing section are logged and displayed. The time taken fro

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23

Chen, Fu-Chin, and 陳福欽. "Design and Implementation of Adaptive High-Efficiency DSP-Based Induction Motor Speed Control System." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/15488428785310626332.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>89<br>An adaptive high-efficiency DSP-based induction motor speed control system is developed in this paper. A combination of an adaptive speed controller and an explicit efficiency control algorithm is proposed to control the speed and power efficiency of the induction motor. First, decoupling of the motor torque and rotor flux amplitude is based on the input-output linearization theory. Then, an adaptive speed controller is designed to control the speed of the induction motor. At steady-state light-load condition, the magnetizing current command is adjusted on the

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24

Yedid, Barba Erika. "Design and implementation of a high-speed data logging facility for a dual DSP system." Thesis, 2002. http://hdl.handle.net/2429/12279.

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This thesis has two main components: implementation and system evaluation. In the implementation phase, we port an existing real-time operating system, called ORTS, from a single processor version to a multiprocessor version, and integrate a DMA mechanism for data transfers, which has never been exploited in the previous ORTS versions. Two major disadvantages of the previous ORTS versions are: its incapability to sample at frequencies higher than 1 kHz, and the large amounts of data losses the system incurs when data is transferred between the DSP board and the host. With the aim of achi

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25

Κωτσόπουλος, Ανδρέας. "Σπειροειδής κίνηση και έλεγχος σε μικρο/νανο-ηλεκτρομηχανικά συστήματα αποθήκευσης πληροφορίας". Thesis, 2012. http://hdl.handle.net/10889/5956.

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Οι τεχνικές Μικροσκοπίας Ατομικής Δύναμης που χρησιμοποιούν ακίδες σάρωσης έχουν την ικανότητα όχι μόνο να παρατηρούν επιφάνειες σε ατομικό επίπεδο αλλά και να τις τροποποιούν σε πολύ μικρή κλίμακα. Αυτό αποτελεί και το κίνητρο για τη χρησιμοποίηση των τεχνικών αυτών στη δημιουργία συσκευών αποθήκευσης με πολύ μεγαλύτερη πυκνότητα από τις συμβατικές συσκευές. Σε διάφορα ερευνητικά προγράμματα αποθήκευσης δεδομένων τεχνολογίας MEMS/NEMS με ακίδες, η σχετική τροχιά κίνησης της ακίδας ως προς το αποθηκευτικό μέσο ακολουθεί ένα μοτίβο raster. Παρά την απλή υλοποίησή της, η προαναφερθείσα κίνηση σά

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26

Chen, Zhen-You, and 陳貞佑. "Study on Failure Factors of Bottom-up DLP High Speed 3D Printing." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/32e243.

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碩士<br>國立臺灣科技大學<br>機械工程系<br>107<br>In the bottom-up mask projection stereolithography technique, the problem of separation force has been in-depth discussion because it greatly affects the printing speed and limits the design of the size and features of printed objects. Until Carbon 3D developed CLIP technology in 2015, it solved the separation force problem, also achieved the concept of continuous printing. This study will use inhibition of radical polymerization and apply to bottom-up DLP system, but we found some defects on the cross-section of the printed object, which led to the failure of

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27

Chu, Chia-Hung, and 褚佳宏. "Research on the embankment filling for the method of Plat load test and DCP test (Case by the contract C220 of the Taiwan High Speed Railway engineering)." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/23759848622921327891.

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碩士<br>國立交通大學<br>工學院碩士在職專班工程技術與管理組<br>96<br>Abstract Recently, the domestic constructions have continuously promoted in Taiwan, especially in transportation constructions. During each engineering construction process, selecting an efficient and suitable testing method to maintain construction quality is essential and also provides positive assistance to the construction progress. Therefore, finding a way to speed up the test process and to achieve the project within the time schedule has become an important research topic as well as the aim of this study. For instance, after the base grade has

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