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Relevant bibliographies by topics / High Speed Parallel Adder

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Academic literature on the topic 'High Speed Parallel Adder'

Author: Grafiati

Published: 4 June 2021

Last updated: 12 February 2022

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Journal articles on the topic "High Speed Parallel Adder"

1

Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

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Hebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.

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Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only.

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Chen, H. P., H. J. Liao, and J. B. Kuo. "BiCMOS dynamic full adder circuit for high-speed parallel multipliers." Electronics Letters 28, no. 12 (1992): 1124. http://dx.doi.org/10.1049/el:19920709.

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

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Setia, Deepika, and Charu Madhu. "Novel Architecture of High Speed Parallel MAC using Carry Select Adder." International Journal of Computer Applications 74, no. 1 (2013): 32–38. http://dx.doi.org/10.5120/12851-9334.

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Thakur, Garima, Harsh Sohal, and Shruti Jain. "An Efficient Design of 8-bit High Speed Parallel Prefix Adder." Research Journal of Science and Technology 10, no. 2 (2018): 105. http://dx.doi.org/10.5958/2349-2988.2018.00015.3.

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Hobson, Richard F. "A framework for high-speed parallel-prefix adder performance evaluation and comparison." International Journal of Circuit Theory and Applications 43, no. 10 (2014): 1474–90. http://dx.doi.org/10.1002/cta.2020.

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Reddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.

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In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

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Et. al., Barma Venkata RamaLakshmi. "Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5673–83. http://dx.doi.org/10.17762/turcomat.v12i3.2242.

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This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

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Dissertations / Theses on the topic "High Speed Parallel Adder"

1

Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.

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Taesopapong, Somboom. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio University / OhioLINK, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183379787.

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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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<p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.</p>

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Kharbash, Fekri Q. Chaudhry Ghulam M. "High-speed redundant modular adder and multiplier." Diss., UMK access, 2004.

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Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2004.<br>"A thesis in electrical engineering." Typescript. Advisor: Ghulam M. Chaudhry. Vita. Title from "catalog record" of the print edition Description based on contents viewed Feb. 24, 2006. Includes bibliographical references (leaves 71-73). Online version of the print edition.

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Manjuladevi, Rajendraprasad Akshay. "High-Speed Testable Radix-2 N-Bit Signed-Digit Adder." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539.

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Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.<br>Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing.<br>A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion.<br>Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.

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高木, 直史, and Naofumi Takagi. "A high-speed reduced-size adder under left-to-right input arrival." IEEE, 1999. http://hdl.handle.net/2237/5290.

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Farley, Ryan Joseph. "Parallel firewall designs for high-speed networks /." Electronic thesis, 2005. http://etd.wfu.edu/theses/available/etd-12142005-194043/.

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9

Thomsen, Axel. "High speed high accuracy signal processing with parallel analog circuits." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13846.

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Kshirsagar, Shirish Purushottam. "High speed image processing system using parallel DSPs." Thesis, Liverpool John Moores University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.262245.

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Books on the topic "High Speed Parallel Adder"

1

PAX computer: High-speed parallel processing and scientific computing. Addison-Wesley Publishing Co., 1989.

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Heerah, Imtehaze. Kinematic architecture selection and analysis of a planar high-speed, high-precision parallel robot. National Library of Canada, 2002.

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3

Lin, Yu, Hans Hegt, Kostas Doris, and Arthur H. M. van Roermund. Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems. Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17680-2.

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Piras, Gabriel. Dynamic finite-element analysis of a planar high-speed, high-precision parallel manipulator with flexible links. National Library of Canada, 2003.

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Szuch, John R. Enhancing aeropropulsion research with high-speed interactive computing. National Aeronautics and Space Administration, Lewis Research Center, 1991.

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Paul, Casasent David, and Society of Photo-optical Instrumentation Engineers., eds. High speed computing: Part of the 1988 Innovative Science and Technology Symposium : 11-12 January 1988, Los Angeles, California. The Society, 1988.

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Parent, Bernard. Numerical study of high-speed hydrogen/air planar parallel turbulent mixing using the baldwin-lomax model. National Library of Canada, 1986.

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Parent, Bernard. Numerical study of high-speed hydrogen/air planar parallel turbulent mixing using the baldwin-lomax model. Dept. of Aerospace Science and Engineering, University of Toronto, 1998.

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Grigor'ev, Anatoliy, Evgeniy Isaev, and Pavel Tarasov. Transfer, storage and processing of large volumes of scientific data. INFRA-M Academic Publishing LLC., 2021. http://dx.doi.org/10.12737/1073525.

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The textbook examines large scientific projects and the amount of data generated by them, and provides an overview of scientific computer networks that allow high-speed transmission of large amounts of data for these projects. The article considers the computing systems offered by the leading manufacturers of computer equipment for processing large amounts of data and providing both the possibilities of storing large amounts of data, including distributed data, and the means of analytics and parallel data processing in real time. Special attention is paid to the security of the transmitted scientific information. Meets the requirements of the federal state educational standards of higher education of the latest generation. For students of technical specialties of bachelor's degree, master's degree, specialty, studying in the areas of "Applied Mathematics and Computer Science", "Business Computer Science" and "Computer Science and Computer Engineering".

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Shah, Parag Shantu. Low-power high-performance 32-bit 0.5[u]m CMOS adder. 1998.

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Book chapters on the topic "High Speed Parallel Adder"

1

Dimitrakopoulos, G., P. Kolovos, P. Kalogerakis, and D. Nikolos. "Design of High-Speed Low-Power Parallel-Prefix VLSI Adders." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_27.

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Venkatesh, Vutukuri, Balaji Yeswanth, Repala Akhil, and Ravi Kumar Jatoth. "An Efficient High-Speed CORDIC Algorithm Using Parallel-Prefix Adders (PPA)." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9775-3_73.

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Sundaresan, C., C. V. S. Chaitanya, P. R. Venkateswaran, Somashekara Bhat, and J. Mohan Kumar. "High Speed BCD Adder." In Advances in Intelligent and Soft Computing. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28308-6_15.

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Muragod, Varsha M., and J. M. Rudagi. "Design and Implementation of High Speed Signed Digit Adder." In Communications in Computer and Information Science. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-25734-6_116.

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Dostrašil, P., F. Hartig, M. Václavík, and P. Jirásko. "High-Speed Parallel Shaft Indexing Drive." In Advances in Mechanisms Design. Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-5125-5_14.

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Mowlika, Penumatsa Sushma Sri Naga, and Vemu Srinivasa Rao. "Energy-Efficient and High-Speed Hybrid 1-Bit Full Adder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7329-8_66.

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Björkman, M., and P. Gunningberg. "Parallel Processing of Protocols." In Architecture and Protocols for High-Speed Networks. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4757-4536-8_8.

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Narayan, V. S., S. M. Pratima, V. S. Saroja, and R. M. Banakar. "High Speed Low Power VLSI Architecture for SPST Adder Using Modified Carry Look Ahead Adder." In Advances in Intelligent Systems and Computing. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-0740-5_56.

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Planquelle, Benoôt, Jean-François Méhaut, and Nathalie Revol. "Multi-protocol Communications and High Speed Networks." In Euro-Par’99 Parallel Processing. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48311-x_15.

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Corsonello, Pasquale, Stefania Perri, and Giuseppe Cocorullo. "VLSI Implementation of a Low-Power High-Speed Self-Timed Adder." In Integrated Circuit Design. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_20.

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Conference papers on the topic "High Speed Parallel Adder"

1

Lakshmanan, Ali Meaamar, and Masuri Othman. "High-Speed Hybrid Parallel-Prefix Carry-Select Adder Using Ling's Algorithm." In 2006 IEEE International Conference on Semiconductor Electronics. IEEE, 2006. http://dx.doi.org/10.1109/smelec.2006.380702.

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Penchalaiah, U., and Siva Kumar VG. "Design of High-Speed and Energy-Efficient Parallel Prefix Kogge Stone Adder." In 2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCAN). IEEE, 2018. http://dx.doi.org/10.1109/icscan.2018.8541143.

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Al-Ibadi, Mohammed A. "Hardware Implementation for High-Speed Parallel Adder for QSD 2D Data Arrays." In 2020 International Conference on Electrical, Communication, and Computer Engineering (ICECCE). IEEE, 2020. http://dx.doi.org/10.1109/icecce49384.2020.9179398.

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Deo, S. "Design of high speed 32-bit parallel prefix adder for CMOS technology." In China-Ireland International Conference on Information and Communications Technologies (CIICT 2007). IEE, 2007. http://dx.doi.org/10.1049/cp:20070723.

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Thakur, Garima, Harsh Sohal, and Shruti Jain. "Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications." In 2020 International Conference on Computational Performance Evaluation (ComPE). IEEE, 2020. http://dx.doi.org/10.1109/compe49325.2020.9200064.

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Nehru, K., A. Shanmugam, and S. Vadivel. "Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits." In 2012 International Conference on Computing, Communication and Applications (ICCCA). IEEE, 2012. http://dx.doi.org/10.1109/iccca.2012.6179204.

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Neeraja, B., and R. Sai Prasad Goud. "Design of an Area Efficient Braun Multiplier using High Speed Parallel Prefix Adder in Cadence." In 2019 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT). IEEE, 2019. http://dx.doi.org/10.1109/icecct.2019.8869307.

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Liao, Qing, and Shuguo Li. "A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area." In ICDSP 2020: 2020 4th International Conference on Digital Signal Processing. ACM, 2020. http://dx.doi.org/10.1145/3408127.3408185.

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Simsek, Cemaleddin, and Kadir Turk. "Hardware optimization for belief propagation polar code decoder with early stopping criteria using high-speed parallel-prefix ling adder." In 2017 40th International Conference on Telecommunications and Signal Processing (TSP). IEEE, 2017. http://dx.doi.org/10.1109/tsp.2017.8075964.

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Yagain, Deepa, and A. Vijaya Krishna. "High speed digital filter design using register minimization retiming & parallel prefix adders." In 2012 Third International Conference on Emerging Applications of Information Technology (EAIT). IEEE, 2012. http://dx.doi.org/10.1109/eait.2012.6408014.

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Reports on the topic "High Speed Parallel Adder"

1

Xu, Xianfan. Equipment for Parallel High Speed Nano-Manufacturing. Defense Technical Information Center, 2006. http://dx.doi.org/10.21236/ada470798.

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Fermi Research Alliance, Fermi Alliance. Radiation-Hardened, High-Speed Parallel VCSEL Links for High-Energy Physics. Office of Scientific and Technical Information (OSTI), 2019. http://dx.doi.org/10.2172/1568826.

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Reif, John H. Very High Speed Holographic Message Routing for Parallel Machines. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada230965.

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Stevenson, Robert L., Andrew Lumsdaine, Jeffery M. Squires, and Micheal P. McNally. Parallel and Distributed Algorithms for High-Speed Image Processing. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada377689.

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Severance, C., T. J. Rosenau, and S. Pramanik. A High-Speed KDL-RAM File System for Parallel Computers. Defense Technical Information Center, 1990. http://dx.doi.org/10.21236/ada223299.

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Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada372678.

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Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada514601.

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