Dissertations / Theses: 'High Speed Parallel Adder'

1

Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.

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Taesopapong, Somboom. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio University / OhioLINK, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183379787.

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3

Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.

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Kharbash, Fekri Q. Chaudhry Ghulam M. "High-speed redundant modular adder and multiplier." Diss., UMK access, 2004.

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Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2004. "A thesis in electrical engineering." Typescript. Advisor: Ghulam M. Chaudhry. Vita. Title from "catalog record" of the print edition Description based on contents viewed Feb. 24, 2006. Includes bibliographical references (leaves 71-73). Online version of the print edition.

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Manjuladevi, Rajendraprasad Akshay. "High-Speed Testable Radix-2 N-Bit Signed-Digit Adder." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1566226346050539.

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6

Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

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Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate. Parallel optical transceiver modules running at several gigabits per second are commercially available nowadays. Parallel optical receivers are one of the key components of parallel interconnected systems. In this work, we describe how a low-power parallel CMOS preamplifier IC and a deskew IC have been designed and fabricated through the IBM 0.13mum CMOS technology. The performances of three different transimpedance amplifier (TIA) topologies are compared experimentally. The best of the three TIAs shows a differential gain of 56.2dBO, 2.6GHz bandwidth, and less than -16dBm sensitivity with a bit-error-rate (BER) less than 10-12. The TIA consumes 2.5mW of power from a 1.2V supply while the channel power is 22mW with a 400mV pp differential output swing. A novel method of accurately measuring the crosstalk power penalty with an on-chip PRBS generator is proposed and its implementation is described. The use of an on-chip PRBS generator to drive the dummy channels eliminates the data pattern dependence between the aggressors and the victim. The inevitable channel skew associated with parallel channels can be removed by a phase-locked loop (PLL) based deskew method. We investigated the skew compensation range of this method theoretically and our experimental results confirm our conclusion. Various practical design and test techniques such as photodiode modeling, AC coupling, low-pass filtering and continuous skew generation, and their implementations, are discussed and implemented in this thesis.

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高木, 直史, and Naofumi Takagi. "A high-speed reduced-size adder under left-to-right input arrival." IEEE, 1999. http://hdl.handle.net/2237/5290.

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Farley, Ryan Joseph. "Parallel firewall designs for high-speed networks /." Electronic thesis, 2005. http://etd.wfu.edu/theses/available/etd-12142005-194043/.

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9

Thomsen, Axel. "High speed high accuracy signal processing with parallel analog circuits." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13846.

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Kshirsagar, Shirish Purushottam. "High speed image processing system using parallel DSPs." Thesis, Liverpool John Moores University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.262245.

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11

Gray, Terrence Patrick 1954. "A parallel adapter for a high-speed serial bus." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277032.

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This paper describes the building of a parallel converter for a high-speed serial bus. The high-speed serial port of the Macintosh personal computer is used to implement the bus, while an MC68000 Educational Computer Board is used to perform the serial-to-parallel conversion. The device's performance is evaluated, and possible methods for improving its performance are discussed.

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Meruguboina, Dronacharya. "EFFICIENT DESIGN OF CARRY SELECT ADDER USING DOMINO MANCHESTER CARRY CHAIN." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/theses/2125.

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Significant characteristic of any VLSI design circuit is its power, reliability, operating frequency and implementation cost. Dynamic CMOS designs provide high operating speeds compared to static CMOS designs combined with low silicon area requirement. This thesis describes the design and the optimization of high performance carry select adder. Previous researchers believed that existing CSA designs has reached theoretical speed bound. But, only a considerable portion of hardware resources of traditional adders are used in worst case scenario. Based on this observation our proposed design will improve on theoretical limit. The major scope of this proposed design is to increase the speed of carry generation between intermediate blocks of Carry select Adder (CSA) by introducing fast multiple clock Domino Manchester carry chain (MCC) that generates carry outputs. This design technique will have some advantages compared to pre-existing implementations in operating speed and power delay product. Simulation has been done using GPDK (Generic Process Design Kits) technology using cadence virtuoso. Thus the proposed technique provides advantages over pre-existing techniques in terms of operating speed.

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Kopek, Christopher Vincent. "Parallel intrusion detection systems for high speed networks using the divided data parallel method." Electronic thesis, 2007. http://dspace.zsr.wfu.edu/jspui/handle/10339/191.

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Erdem, Oguzhan. "Parallel And Pipelined Architectures For High Speed Ip Packet Forwarding." Phd thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613543/index.pdf.

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A substantial increase in the number of internet users and the traffic volume bring new challenges for network router design. The current routers need to support higher link data rates and large number of line cards to accommodate the growth of the internet traffic, which necessitate an increase in physical space, power and memory use. Packet forwarding, which is one of the major tasks of a router, has been a performance bottleneck in internet infrastructure. In general, most of the packet forwarding algorithms are implemented in software. However, hardware based solutions has also been popular in recent years because of their high throughput performance. Besides throughput, memory efficiency, incremental/dynamic updates and power consumption are the basic performance challenges for packet forwarding architectures. Hardware-based packet forwarding engines for network routers can be categorized into two groups that are ternary content addressable memory (TCAM) based and dynamic/static random access memory (DRAM/SRAM) based solutions. TCAM-based architectures are simple and hence popular solutions for today&rsquo s routers. However, they are expensive, power-hungry, and oer little adaptability to new addressing and routing protocols. On the other hand, SRAM has higher density, lower power consumption, and higher speed. The common data structure used in SRAM-based solutions for performing longest prefix matching (LPM) is some type of a tree. In these solutions, multiple memory accesses are required to find the longest matched prefix. Therefore, parallel and pipelining techniques are used to improve the throughput. This thesis studies TCAM and SRAM based parallel and pipelined architectures for high performance packet forwarding. We proposed to use a memory efficient disjoint prefix set algorithm on TCAM based parallel IP packet forwarding engine to improve its performance. As a fundamental contribution of this thesis, we designed an SRAM based parallel, intersecting and variable length multi-pipeline array structure (SAFIL) for trie-based internet protocol (IP) lookup. We also proposed a novel dual port SRAM based high throughput IP lookup engine (SAFILD) which is built upon SAFIL. As an alternative to traditional binary trie, we proposed a memory efficient data structure called compact clustered trie (CCT) for IP lookup. Furthermore, we developed a novel combined length-infix pipelined search (CLIPS) architecture for high performance IPv4/v6 lookup on FPGA. Finally, we designed a memory efficient clustered hierarchical search structure (CHSS) for packet classification. A linear pipelined SRAM-based architecture for CHSS which is implemented on FPGA is also proposed.

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Dandu, Venkata Satyanarayana Raju. "Parallel processing and VLSI design a high speed efficient multiplier." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183753328.

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Harper, Scott Jeffery. "Design of a hardware interface for a high-speed parallel network." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-01102009-063929/.

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Bataineh, Abdulla. "Parallel logic and interconnection simulation algorithms for high-speed digital circuits /." The Ohio State University, 1992. http://rave.ohiolink.edu/etdc/view?acc_num=osu148775943632878.

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Wong, Kwan-po. "High-speed network interface for commodity SMP clusters." Hong Kong : University of Hong Kong, 2000. http://sunzi.lib.hku.hk/hkuto/record.jsp?B22505520.

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Nezhad, Mohammad Reza Reshadi, and Kaivan Navi. "High-speed Multiplier Design Using Multi-Operand Multipliers." IJCSN, 2012. http://hdl.handle.net/10150/219513.

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Multipliers are used in most arithmetic computing systems such as 3D graphics, signal processing, and etc. It is inherently a slow operation as a large number of partial products are added to produce the result. There has been much work done on designing multipliers [1]-[6]. In first stage, Multiplication is implemented by accumulation of partial products, each of which is conceptually produced via multiplying the whole multi-digit multiplicand by a weighted digit of multiplier. To compute partial products, most of the approaches employ the Modified Booth Encoding (MBE) approach [3]-[5], [7], for the first step because of its ability to cut the number of partial products rows in half. In next step the partial products are reduced to a row of sums and a row of caries which is called reduction stage. Multiplication is one of the major bottlenecks in most digital computing and signal processing systems, which depends on the word size to be executed. This paper presents three deferent designs for three-operand 4-bit multiplier for positive integer multiplication, and compares them in regard to timing, dynamic power, and area with classical method of multiplication performed on today architects. The three-operand 4-bit multipliers structure introduced, serves as a building block for three-operand multipliers in general

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20

Chan, Edmon. "Design and Implementation of a High Speed Cable-Based Planar Parallel Manipulator." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/835.

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Robotic automation has been the major driving force in modern industrial developments. High speed pick-and-place operations find their place in many manufacturing applications. The goal of this project is to develop a class of high speed robots that has a planar workspace. The presented robots are intended for pick-and-place applications that have a relatively large workspace. In order to achieve this goal, the robots must be both stiff and light. The design strategies adapted in this study were expanded from the research work by Prof Khajepour and Dr. Behzadipour. The fundamental principles are to utilize a parallel mechanism to enhance robot stiffness and cable construction to reduce moving inertia. A required condition for using cable construction is the ability to hold all cables under tension. This can only be achieved under certain conditions. The design phase of the study includes a static analysis on the robot manipulator that ensures certain mechanical components are always held under tension. This idea is extended to address dynamic situations where the manipulator velocity and acceleration are bounded. Two concept robot configurations, 2D-Deltabot, and 2D-Betabot are presented. Through a series of analyses from the robot inverse kinematic model, the dynamic properties of a robot can be computed in an effective manner. It was determined that the presented robots can achieve 4g acceleration and 4m/s maximum speed within their 700mm by 100mm workspace with a pair of 890W rotary actuators controlling two degrees of freedom. The 2D-Deltabot was chosen for prototype development. A kinematics calibration algorithm was developed to enhance the robot accuracy. Experimental test results had shown that the 2D-Deltabot was capable of running at 81 cycles per minute on a 730mm long pick-and-place path. Further experiments showed that the robot had a position accuracy of 0. 62mm and a position repeatability of 0. 15mm, despite a few manufacturing errors from the prototype fabrication.

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21

Anderson, Eric William. "Design of a low cost, high speed robot for poultry processing." Thesis, Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-06092004-082016/unrestricted/anderson%5eric%5w%5200408%5ms.pdf.

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Thesis (M.S.)--School of Mechanical Engineering, Georgia Institute of Technology, 2005. Directed by Harvey Lipkin. Imme Ebert-Uphoff, Committee Member ; Wayne Book, Committee Member ; Harvey Lipkin, Committee Chair. Includes bibliographical references.

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黃君保 and Kwan-po Wong. "High-speed network interface for commodity SMP clusters." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2000. http://hub.hku.hk/bib/B31225330.

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23

譚達俊 and Tat-chun Anthony Tam. "Performance studies of high-speed communication on commodity cluster." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2001. http://hub.hku.hk/bib/B31243642.

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Tam, Tat-chun Anthony. "Performance studies of high-speed communication on commodity cluster /." Hong Kong : University of Hong Kong, 2001. http://sunzi.lib.hku.hk/hkuto/record.jsp?B23501753.

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25

Karnick, Amol S. "High speed 3D ultrasound reconstruction : a comparative study between parallel and sequential processors." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0024/MQ50628.pdf.

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Davison, Christopher. "Development of a parallel access optical disk system for high speed pattern recognition." Thesis, Loughborough University, 1997. https://dspace.lboro.ac.uk/2134/14365.

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Pattern recognition is a rapidly expanding area of research, with applications ranging from character recognition and component inspection to robotic guidance and military reconnaissance. The basic principle of image recognition is that of comparing the unknown image with many known reference images or 'filters', until a match is found. By comparing the unknown image with a large data bank of filters, the diversity of the application can be extended. The work presented in this thesis details the practical development of an optical disk based memory system as applied in various optical correlators for pattern recognition purposes. The characteristics of the holographic optical disk as a storage medium are investigated in terms of information capacity and signal to noise ratio, where a fully automated opto-mechanical system has been developed for the control of the optical disk and the processing of the information recorded. A liquid crystal television has been used as a Spatial Light Modulator for inputting the image data, and as such, the device characteristics have been considered with regard to processing both amplitude and phase information. Three main configurations of optical correlator have been applied, specifically an image plane correlator, a VanderLugt correlator, and an Anamorphic correlator. Character recognition has been used to demonstrate correlator performance, where simple matched filtering has been applied, subsequent to which, an improvement in class discrimination has been demonstrated with the application of the Minimum Average Correlation Energy filter. The information processing rate obtained as a result of applying 2D parallel processing has been shown to be many orders of magnitude larger than that available with comparable serial based digital systems.

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Krasteva, Denitza Tchavdarova Jr. "Distributed Parallel Processing and Dynamic Load Balancing Techniques for Multidisciplinary High Speed Aircraft Design." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/37035.

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Multidisciplinary design optimization (MDO) for large-scale engineering problems poses many challenges (e.g., the design of an efficient concurrent paradigm for global optimization based on disciplinary analyses, expensive computations over vast data sets, etc.) This work focuses on the application of distributed schemes for massively parallel architectures to MDO problems, as a tool for reducing computation time and solving larger problems. The specific problem considered here is configuration optimization of a high speed civil transport (HSCT), and the efficient parallelization of the embedded paradigm for reasonable design space identification. Two distributed dynamic load balancing techniques (random polling and global round robin with message combining) and two necessary termination detection schemes (global task count and token passing) were implemented and evaluated in terms of effectiveness and scalability to large problem sizes and a thousand processors. The effect of certain parameters on execution time was also inspected. Empirical results demonstrated stable performance and effectiveness for all schemes, and the parametric study showed that the selected algorithmic parameters have a negligible effect on performance. Master of Science

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Qiao, Hao. "Sparse hierarchical model order reduction for high speed interconnects." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:8881/R/?func=dbin-jump-full&object_id=32359.

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Ellis, Robert H. "Long haul communications in the HF spectrum utilizing high speed modems." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/23289.

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Approved for public release; distribution is unlimited In the past ten years reliable high-speed satellite systems have pushed slower less reliable communication systems to the bottom of the list for development programs. Concern over reduced budgets, vulnerability of expensive satellite systems, and recent advances in HF technology are creating new interest in upgrading existing HF communication systems. Nondevelopment Items (NDI) are defined as the use of off-the-shelf commercial items instead of costly, time-consuming conventional research and development programs. The Navy Department's current policies are designed to insure the maximum use of NDI to fulfill Navy requirements. The speed of HF systems can be improved using current signaling and modulation techniques, and reliability can be increased by error-correcting codes or error detection used in conjunction with automatic repeat request (ARQ) schemes. Improved HF systems not only provide survivable back-up capability, but increased capacity for present communication needs. http://archive.org/details/longhaulcommunic00elli Lieutenant, United States Navy

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Parent, Bernard. "Numerical study of high-speed hydrogen/air planar parallel turbulent mixing using the Baldwin-Lomax model." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape17/PQDD_0008/MQ34106.pdf.

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31

Choudhury, Niren Ch. "Implementation of basic software tools to start a VLSI program at Ohio University with a high speed parallel multiplier as an example." Ohio : Ohio University, 1985. http://www.ohiolink.edu/etd/view.cgi?ohiou1183752120.

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32

Macpherson, Kenneth Noble. "Low hardware cost, high speed, full-parallel finite impulse response digital filters on field programmable gate arrays." Thesis, University of Strathclyde, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.405323.

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33

Broffel, Robert W. "USING THE AMD TAXI CHIPS IN A PARALLEL TO FIBER INTERFACE." International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/607272.

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International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada To meet the security constraints for mission control rooms; the rooms must interface to other systems via fiber optic cable. Analog data from DAC (Digital to Analog Converter) outputs were initially brought into the rooms on copper wire. This paper outlines the conversion to fiber optic cable using the AMD TAXI chips in our Optical Digital Interface (ODI).

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34

Alfredsson, Jon. "Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201.

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The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

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Chen, Xiaomin [Verfasser], and Ashwin [Akademischer Betreuer] Gumaste. "Performance Analysis of Parallel Transmission and Multipath Routing in High-Speed Network Systems / Xiaomin Chen ; Betreuer: Ashwin Gumaste." Braunschweig : Technische Universität Braunschweig, 2014. http://d-nb.info/117582075X/34.

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Solana, Gabriel A. "Modeling of Crosstalk in High Speed Planar Structure Parallel Data Buses and Suppression by Uniformly Spaced Short Circuits." FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/606.

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The aim of this thesis is to identify coupling mechanisms for three line microstrip, stripline and microstrip with dielectric overlay structures as either inductive or capacitive, quantify through simulation and measurement the amount of crosstalk to be expected in terms of scattering parameters. A new method of crosstalk suppression is implemented into each three line structure by placing uniformly spaced short circuits down the length of the center transmission line. All structures were simulated over various physical and electrical parameters. Select microstrip structures, shielded and unshielded, were fabricated and measured to validate the effectiveness of the shielding technique. Shielding effectiveness was calculated from the measurements, and their results showed that the isolation between lines was increased by up to 20dB.

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Kohout, James. "Design and performance analysis of MPI-SHARC a high-speed network service for distributed digital signal processor systems /." [Gainesville, Fla.] : University of Florida, 2001. http://etd.fcla.edu/etd/UF/anp4297/MASTER.pdf.

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Thesis (M.S.)--University of Florida, 2001. Title from first page of PDF file. Document formatted into pages; contains ix, 69 p.; also contains graphics. Vita. Includes bibliographical references (p. 66-68).

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Giunta, Anthony A. "Aircraft Multidisciplinary Design Optimization using Design of Experiments Theory and Response Surface Modeling Methods." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30613.

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Design engineers often employ numerical optimization techniques to assist in the evaluation and comparison of new aircraft configurations. While the use of numerical optimization methods is largely successful, the presence of numerical noise in realistic engineering optimization problems often inhibits the use of many gradient-based optimization techniques. Numerical noise causes inaccurate gradient calculations which in turn slows or prevents convergence during optimization. The problems created by numerical noise are particularly acute in aircraft design applications where a single aerodynamic or structural analysis of a realistic aircraft configuration may require tens of CPU hours on a supercomputer. The computational expense of the analyses coupled with the convergence difficulties created by numerical noise are significant obstacles to performing aircraft multidisciplinary design optimization. To address these issues, a procedure has been developed to create two types of noise-free mathematical models for use in aircraft optimization studies. These two methods use elements of statistical analysis and the overall procedure for using the methods is made computationally affordable by the application of parallel computing techniques. The first modeling method, which has been the primary focus of this work, employs classical statistical techniques in response surface modeling and least squares surface fitting to yield polynomial approximation models. The second method, in which only a preliminary investigation has been performed, uses Bayesian statistics and an adaptation of the Kriging process in Geostatistics to create exponential function-based interpolating models. The particular application of this research involves modeling the subsonic and supersonic aerodynamic performance of high-speed civil transport (HSCT) aircraft configurations. The aerodynamic models created using the two methods outlined above are employed in HSCT optimization studies so that the detrimental effects of numerical noise are reduced or eliminated during optimization. Results from sample HSCT optimization studies involving five and ten variables are presented here to demonstrate the utility of the two modeling methods. Ph. D.

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Yeh, Ho-Hsin. "Developments of 60 GHz Antenna and Wireless Interconnect inside Multi-Chip Module for Parallel Processor System." Diss., The University of Arizona, 2013. http://hdl.handle.net/10150/272872.

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In order to carry out the complicated computation inside the high performance computing (HPC) systems, tens to hundreds of parallel processor chips and physical wires are required to be integrated inside the multi-chip package module (MCM). The physical wires considered as the electrical interconnects between the processor chips, however, have the challenges on placements and routings because of the unequal progress between the semiconductor and I/O size reductions. The primary goal of the research is to overcome package design challenges - providing a hybrid computing architecture with implemented 60 GHz antennas as the high efficient wireless interconnect which could generate over 10 Gbps bandwidth on the data transmissions. The dissertation is divided into three major parts. In the first part, two different performance metrics, power loss required to be recovered (PRE) and wireless link budget, on evaluating the antenna's system performance within the chip to chip wireless interconnect are introduced to address the design challenges and define the design goals. The second part contains the design concept, fabrication procedure and measurements of implemented 60 GHz broadband antenna in the application of multi-chip data transmissions. The developed antenna utilizes the periodically-patched artificial magnetic conductor (AMC) structure associated with the ground-shielded conductor in order to enhance the antenna's impedance matching bandwidth. The validation presents that over 10 GHz -10 dB S11 bandwidth which indicates the antenna's operating bandwidth and the horizontal data transmission capability which is required by planar type chip to chip interconnect can be achieved with the design concept. In order to reduce both PRE and wireless link budget numbers, a 60 GHz two-element array in the multi-chip communication is developed in the third part. The third section includes the combined-field analysis, the design concepts on two-element array and feeding circuitry. The simulation results agree with the predicted field analysis and demonstrate the 5dBi gain enhancement in the horizontal direction over a single 60 GHz AMC antenna to further reduce both PRE and wireless link budget numbers.

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40

Detofsky, Abram Maximilian. "A multi-wavelength optical content-addressable parallel processor (MW-OCAPP) for high-speed relational database processing: Free-space experimental implementation and monolithic adaptation based on guided-wave technology." Thesis, The University of Arizona, 1999. http://hdl.handle.net/10150/291970.

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This thesis explores the five-space experimental implementation and monolithic adaptation of the Equality subsystem from a parallel relational database optical machine called the Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP). MW-OCAPP uses a novel polarization- and wavelength-encoding scheme to achieve an input/output-limited experimental peak bit comparison rate of 96,000/sec. Recognizing the severe diffraction-limit penalty for using a free-space optical processor with relatively long path lengths, a system based on guided-wave optics called the Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC) was developed. Although algorithmically identical to MW-OCAPP's equality operation, EP3IC's peak bit comparison rate for a similarly configured machine is over six orders of magnitude faster. It achieves this substantial performance advantage by making use of integrated high-speed detectors and electro-optic modulators. This integrated circuit solution provides relatively low-power operation, fast switching speed, a compact system footprint, vibration tolerance, and a design that is highly manufacturable.

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41

De, Silva Weeraddana Manjula Kumara. "Correlation Imaging for Real-time Cardiac MRI." University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471346206.

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Viebke, André. "Accelerated Deep Learning using Intel Xeon Phi." Thesis, Linnéuniversitetet, Institutionen för datavetenskap (DV), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-45491.

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Deep learning, a sub-topic of machine learning inspired by biology, have achieved wide attention in the industry and research community recently. State-of-the-art applications in the area of computer vision and speech recognition (among others) are built using deep learning algorithms. In contrast to traditional algorithms, where the developer fully instructs the application what to do, deep learning algorithms instead learn from experience when performing a task. However, for the algorithm to learn require training, which is a high computational challenge. High Performance Computing can help ease the burden through parallelization, thereby reducing the training time; this is essential to fully utilize the algorithms in practice. Numerous work targeting GPUs have investigated ways to speed up the training, less attention have been paid to the Intel Xeon Phi coprocessor. In this thesis we present a parallelized implementation of a Convolutional Neural Network (CNN), a deep learning architecture, and our proposed parallelization scheme, CHAOS. Additionally a theoretical analysis and a performance model discuss the algorithm in detail and allow for predictions if even more threads are available in the future. The algorithm is evaluated on an Intel Xeon Phi 7120p, Xeon E5-2695v2 2.4 GHz and Core i5 661 3.33 GHz using various architectures and thread counts on the MNIST dataset. Findings show a 103.5x, 99.9x, 100.4x speed up for the large, medium, and small architecture respectively for 244 threads compared to 1 thread on the coprocessor. Moreover, a 10.9x - 14.1x (large to small) speed up compared to the sequential version running on Xeon E5. We managed to decrease training time from 7 days on the Core i5 and 31 hours on the Xeon E5, to 3 hours on the Intel Xeon Phi when training our large network for 15 epochs

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Pateloup, Sylvain. "Modélisations et aptitudes à l'emploi des machines-outils à structure parallèle : vers une optimisation dirigée du processus." Phd thesis, Université Blaise Pascal - Clermont-Ferrand II, 2011. http://tel.archives-ouvertes.fr/tel-00609682.

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Les travaux de recherche présentés dans ce mémoire concernent la prédiction et l'amélioration des performances des machines-outils à structure parallèle dans le but de produire des pièces conformes à la qualité requise en un temps minimal. Le problème abordé permet de déterminer l'influence de la structure sur la productivité et la qualité de la pièce usinée dans le contexte de l'Usinage à Grande Vitesse de pièces automobiles et aéronautiques. Ce travail propose alors des avancées suivant deux axes fondamentaux : - la modélisation du comportement anisotrope de la cellule d'usinage ; - la proposition de nouvelles méthodes d'adaptation du processus.Ces deux axes sont dans un premier temps abordés vis-à-vis d'un objectif d'amélioration des temps de déplacement d'outil hors matière. La méthode développée nécessite l'élaboration d'un modèle cinématique des déplacements hors matière spécifique à chaque structure de machine outil et basé sur l'utilisation d'une loi de commande articulaire. Un outil d'aide à la mise en place d'un usinage sur machine-outil à structure parallèle est ensuite proposé. Cet outil repose sur un modèle numérique de comportement cinématique utilisant une loi de commande de déplacement dans le repère lié à la pièce permettant de prédire le temps d'usinage en fonction des trajectoires. L'optimisation du processus d'usinage s'appuie également sur la prédiction de la qualité d'usinage. Pour cela, un modèle expérimental basé sur une campagne de mesures effectuée sur la machine-outil considérée a été développé. Ces approches sont appliquées à des usinages de pièces industrielles sur la machine-outil PCI Tripteor X7. Leur originalité réside dans l'amélioration des performances des machines-outils à structure parallèle à partir de l'analyse du comportement durant l'usinage et permet, par conséquent, d'étendre leur domaine d'application.

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Rong-Jong, Fan. "The High-Speed Segment Adders in Parallel Computation." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0016-1303200709302763.

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Fan, Rong-Jong, and 范容榕. "The High-Speed Segment Adders in Parallel Computation." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/35143670417045845888.

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碩士 國立清華大學 電機工程學系 94 The speed of a digital arithmetic processor for addition, subtraction, multiplication, and division is heavily dependent on the speed of the adders used in the system. In the system on chip (SoC) generation, faster speed and smaller area electric devices are required to build the large circuit. In order to increase the speed of ALU, increasing the speed of adders is a useful and efficient method. This thesis proposes a segment parallel adder (SA) as a choice for various high speed addition techniques. This segment parallel adder consists of horizontal and vertical segments those are executed the addition in parallel. When the horizontal segment starts addition from the LSB to the MSB, the vertical segment is also active simultaneously from the top to the bottom such that the time delay from the top to the bottom should be equal to that of the horizontal segment of the carry propagation from the LSB to the MSB. In this way, an optimal matched addition is obtained. From the simulation result, the proposed variable segment parallel adder reveals the fewest delay and fastest speed. The delay of the variable segmented parallel adder can be reduced to 29% compared with the CSA at the cost of larger area of 72%. The AT2 in this case is also reduced to 14%.

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Fong, Yi-Zeng, and 馮翊展. "High-Speed Area-Minimized Reconfigurable Adder Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/20789065061731490137.

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碩士 國立交通大學 電子工程系所 94 Binary addition is one of the fundamental arithmetic operations in digital system design. Consequently, several adder architectures have been proposed to meet different design requirements in the past. Various architectures like carry-select, parallel-prefix, and carry-lookahead lead to different performance among area, delay, and power. In general, Kogge-Stone parallel-prefix adders provide a good solution to optimize delay and regular structure for VLSI implementation. The proposed architecture uses Ling addition to reduce one logic level delay in parallel-prefix structure for the carry generation. Furthermore, using hybrid parallel-prefix/carry-select architecture and some special function blocks can reduce overall area. Experimental results reveal that the proposed architecture achieves 25% area reduction when compared to traditional Kogge-Stone parallel-prefix adders. Recently, the multimedia plays an important role in our life. Multimedia signal processing usually needs a fast reconfigure adder, which can be run-time reconfigured to handle the operations with different precisions. However, the extra overhead of partition scheme for the purpose of reconfigurability is unavoidable. Therefore, we present a new reconfigurable approach by modifying our original architecture without introducing significant extra area and timing penalty. Finally, experimental results show that the new reconfigurable adder needs only 5.12% delay penalty and 3.98% area penalty. In brief, the proposed adders do our utmost to reduce area without affecting speed and extent to reconfigurable scheme easily.

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Ho, Cheng-che, and 何政哲. "High Speed and Energy Efficient 10-Transistor Full Adder Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/47514434326546544285.

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碩士 國立雲林科技大學 電子與資訊工程研究所 93 How to handle the balance of the performance and power consumption in layout area reduced design is the most important issue for designer. In this paper, we proposed a novel full adder design featuring both low voltage and low energy ( power delay product ) operation using as few as 10 transistors per bit. To achieve low voltage operation, the design adopts inverter based XOR/XNOR designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from direct cascading if no extra buffering is employed. The proposed design successfully embeds the buffering circuit in the full adder design so that the transistor count is kept as minimum. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both DC and AC performances of the proposed design are evaluated against various full adder designs via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35μm process models, indicate that the proposed design has the lowest working Vdd ( 1.9V ) and highest working frequency ( 1300MHz @ 3.3V ) among all designs using 10 transistors. It also features the highest frequency and lowest energy consumption per addition in the application of ripple carry adder.

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Shah, Jaspal Singh. "Design of Soft Error Robust High Speed 64-bit Logarithmic Adder." Thesis, 2008. http://hdl.handle.net/10012/4202.

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Continuous scaling of the transistor size and reduction of the operating voltage have led to a significant performance improvement of integrated circuits. However, the vulnerability of the scaled circuits to transient data upsets or soft errors, which are caused by alpha particles and cosmic neutrons, has emerged as a major reliability concern. In this thesis, we have investigated the effects of soft errors in combinational circuits and proposed soft error detection techniques for high speed adders. In particular, we have proposed an area-efficient 64-bit soft error robust logarithmic adder (SRA). The adder employs the carry merge Sklansky adder architecture in which carries are generated every 4 bits. Since the particle-induced transient, which is often referred to as a single event transient (SET) typically lasts for 100~200 ps, the adder uses time redundancy by sampling the sum outputs twice. The sampling instances have been set at 110 ps apart. In contrast to the traditional time redundancy, which requires two clock cycles to generate a given output, the SRA generates an output in a single clock cycle. The sampled sum outputs are compared using a 64-bit XOR tree to detect any possible error. An energy efficient 4-input transmission gate based XOR logic is implemented to reduce the delay and the power in this case. The pseudo-static logic (PSL), which has the ability to recover from a particle induced transient, is used in the adder implementation. In comparison with the space redundant approach which requires hardware duplication for error detection, the SRA is 50% more area efficient. The proposed SRA is simulated for different operands with errors inserted at different nodes at the inputs, the carry merge tree, and the sum generation circuit. The simulation vectors are carefully chosen such that the SET is not masked by error masking mechanisms, which are inherently present in combinational circuits. Simulation results show that the proposed SRA is capable of detecting 77% of the errors. The undetected errors primarily result when the SET causes an even number of errors and when errors occur outside the sampling window.

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LIN, YI-MIN, and 林億民. "High speed parallel resonant power supply." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/58152648137105152741.

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Qi-Wei, Kuo. "Substrate Bias Optimized 32bit High Speed Adder with Post-Manufacture Tunable Clock." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1506200515305300.

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