Journal articles on the topic 'High Speed Parallel Adder'
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Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.
Full textHebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.
Full textNirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.
Full textChen, H. P., H. J. Liao, and J. B. Kuo. "BiCMOS dynamic full adder circuit for high-speed parallel multipliers." Electronics Letters 28, no. 12 (1992): 1124. http://dx.doi.org/10.1049/el:19920709.
Full textB Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.
Full textSetia, Deepika, and Charu Madhu. "Novel Architecture of High Speed Parallel MAC using Carry Select Adder." International Journal of Computer Applications 74, no. 1 (2013): 32–38. http://dx.doi.org/10.5120/12851-9334.
Full textThakur, Garima, Harsh Sohal, and Shruti Jain. "An Efficient Design of 8-bit High Speed Parallel Prefix Adder." Research Journal of Science and Technology 10, no. 2 (2018): 105. http://dx.doi.org/10.5958/2349-2988.2018.00015.3.
Full textHobson, Richard F. "A framework for high-speed parallel-prefix adder performance evaluation and comparison." International Journal of Circuit Theory and Applications 43, no. 10 (2014): 1474–90. http://dx.doi.org/10.1002/cta.2020.
Full textReddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.
Full textEt. al., Barma Venkata RamaLakshmi. "Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5673–83. http://dx.doi.org/10.17762/turcomat.v12i3.2242.
Full textAkbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (2021): 1791. http://dx.doi.org/10.3390/electronics10151791.
Full textGanjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Full textPerri, Stefania, Marco Lanuzza, and Pasquale Corsonello. "Design of high-speed low-power parallel-prefix adder trees in nanometer technologies." International Journal of Circuit Theory and Applications 42, no. 7 (2013): 731–43. http://dx.doi.org/10.1002/cta.1886.
Full textWEI, SHUGANG, and KENSUKE SHIMIZU. "MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 129–44. http://dx.doi.org/10.1142/s0218126606002976.
Full textDimitrakopoulos, G., and D. Nikolos. "High-speed parallel-prefix VLSI Ling adders." IEEE Transactions on Computers 54, no. 2 (2005): 225–31. http://dx.doi.org/10.1109/tc.2005.26.
Full textProf. Shweta Jain. "Design and Analysis of Low Power Hybrid Braun Multiplier using Ladner Fischer Adder." International Journal of New Practices in Management and Engineering 6, no. 03 (2017): 07–12. http://dx.doi.org/10.17762/ijnpme.v6i03.59.
Full textjarani, S. V. Padma, and Dr M. Murali dhar. "Implementation of High Speed, Low Power and Area Efficient Parallel Prefix Adder in an FPGA." International Journal of Engineering Trends and Technology 25, no. 4 (2015): 212–18. http://dx.doi.org/10.14445/22315381/ijett-v25p239.
Full textLOKESH, P., U. SOMALATHA, and S. CHANDANA. "VLSI DESIGN OF LOW POWER HIGH SPEED PARALLEL SELF TIMED ADDER FOR ALU PROCESSING CIRCUITS." i-manager's Journal on Circuits and Systems 5, no. 4 (2017): 27. http://dx.doi.org/10.26634/jcir.5.4.13942.
Full textIbrahim, Salah Hasan, Sawal Hamid Md Ali, and Md Shabiul Islam. "Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/131568.
Full textV.Padmajarani, S., and M. Muralidhar. "Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA." International Journal of Computer Applications 58, no. 1 (2012): 17–21. http://dx.doi.org/10.5120/9246-3410.
Full textRashid, Muhammad, Malik Imran, and Asher Sajid. "An Efficient Elliptic-Curve Point Multiplication Architecture for High-Speed Cryptographic Applications." Electronics 9, no. 12 (2020): 2126. http://dx.doi.org/10.3390/electronics9122126.
Full textBASHAGHA, A. E., and M. K. IBRAHIM. "NONRESTORING RADIX-2k SQUARE ROOTING ALGORITHM." Journal of Circuits, Systems and Computers 06, no. 03 (1996): 267–85. http://dx.doi.org/10.1142/s0218126696000200.
Full textBabu, A. Madhu. "Evaluation of High Speed and Low Memory Parallel Prefix Adders." IOSR Journal of Electrical and Electronics Engineering 8, no. 4 (2013): 13–20. http://dx.doi.org/10.9790/1676-0841320.
Full textKalampoukas, L., D. Nikolos, C. Efstathiou, H. T. Vergos, and J. Kalamatianos. "High-speed parallel-prefix module 2/sup n/-1 adders." IEEE Transactions on Computers 49, no. 7 (2000): 673–80. http://dx.doi.org/10.1109/12.863036.
Full textPenchalaiah, U., and Siva Kumar VG. "Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder." International Journal of Engineering & Technology 7, no. 2.32 (2018): 243. http://dx.doi.org/10.14419/ijet.v7i2.32.13519.
Full textN., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.
Full textMADHAVI, K., and P. DIVYA. "High –Speed Implementation of Design and Analysis by Using Parallel Prefix Adders." IOSR Journal of Electronics and Communication Engineering 12, no. 02 (2017): 44–49. http://dx.doi.org/10.9790/2834-1202024449.
Full textElango, S., and P. Sampath. "Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems." Journal of Circuits, Systems and Computers 29, no. 13 (2020): 2050214. http://dx.doi.org/10.1142/s021812662050214x.
Full textCui, Xiaoping, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander, and Fabrizio Lombardi. "Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders." Journal of Signal Processing Systems 90, no. 3 (2017): 409–19. http://dx.doi.org/10.1007/s11265-017-1249-3.
Full textMOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.
Full textUma, R., and P. Dhavachelvan. "Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs." Research Journal of Applied Sciences, Engineering and Technology 7, no. 13 (2014): 2705–10. http://dx.doi.org/10.19026/rjaset.7.589.
Full textDe, Mallika, and Bhabani P. Sinha. "Fast Parallel Multiplication Using Redundant Quarternary Number System." Parallel Processing Letters 07, no. 01 (1997): 13–23. http://dx.doi.org/10.1142/s0129626497000048.
Full textMirzaei, Shahnam, Ryan Kastner, and Anup Hosangadi. "Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs." International Journal of Reconfigurable Computing 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/697625.
Full textRastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.
Full textWang, Wen Xing, and Xing Lin Cao. "Research on Multiform Circuit Multi-Carrier Transmitter in Smart Grid." Advanced Materials Research 204-210 (February 2011): 2214–16. http://dx.doi.org/10.4028/www.scientific.net/amr.204-210.2214.
Full textDivakara, S. S., Sudarshan Patilkulkarni, and Cyril Prasanna Raj. "Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic." International Journal of Image and Graphics 20, no. 03 (2020): 2050017. http://dx.doi.org/10.1142/s0219467820500175.
Full textJain, Shivkaran, and Arun Kr Chatterjee. "Nand gate architectures for memory decoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 2 (2013): 610–14. http://dx.doi.org/10.24297/ijct.v7i2.3464.
Full textWeymouth, Gabriel David, Robert Vance Wilson, and Frederick Stern. "RANS Computational Fluid Dynamics Predictions of Pitch and Heave Ship Motions in Head Seas." Journal of Ship Research 49, no. 02 (2005): 80–97. http://dx.doi.org/10.5957/jsr.2005.49.2.80.
Full textIsobe, Daishin, Noriyuki Hori, Shin Kawai, Keisuke Yagi, and Triet Nguyen-Van. "Digital Control of a Stepping Motor for Eliminating Rotation Speed Fluctuations Using Adaptive Gains." Electronics 10, no. 11 (2021): 1335. http://dx.doi.org/10.3390/electronics10111335.
Full textKrim, Saber, Soufien Gdaim, and Mohamed Faouzi Mimouni. "Robust Direct Torque Control with Super-Twisting Sliding Mode Control for an Induction Motor Drive." Complexity 2019 (June 24, 2019): 1–24. http://dx.doi.org/10.1155/2019/7274353.
Full textKowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.
Full textAITHAL, GANESH, K. N. HARI BHAT, and U. SRIPATI ACHARYA. "HIGH-SPEED AND SECURE ENCRYPTION SCHEMES BASED ON CHINESE REMAINDER THEOREM FOR STORAGE AND TRANSMISSION OF MEDICAL INFORMATION." Journal of Mechanics in Medicine and Biology 10, no. 01 (2010): 167–90. http://dx.doi.org/10.1142/s0219519410003307.
Full textSheharyar, A., O. Bouhali, and A. Castaneda. "Speeding Up and Parallelizing the GARFIELD++." EPJ Web of Conferences 174 (2018): 06004. http://dx.doi.org/10.1051/epjconf/201817406004.
Full textSKAVANTZOS, ALEXANDER, MOHAMMAD ABDALLAH, and THANOS STOURAITIS. "LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS." Journal of Circuits, Systems and Computers 16, no. 02 (2007): 267–86. http://dx.doi.org/10.1142/s0218126607003666.
Full textSolomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.
Full textPanjeta, Ashwani. "Synthesis of High Speed Full Adder." International Journal of Engineering Trends and Technology 9, no. 5 (2014): 223–27. http://dx.doi.org/10.14445/22315381/ijett-v9p245.
Full textNaga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.
Full textPrihozhy, A. A. "Synthesis of parallel adders from if-decision diagrams." «System analysis and applied information science», no. 2 (August 18, 2020): 61–70. http://dx.doi.org/10.21122/2309-4923-2020-2-61-70.
Full textShraim, H., Y. Harkouss, and H. Bazzi. "A novel hybrid back-stepping and fuzzy logic control strategy for a quadcopter." Aeronautical Journal 121, no. 1244 (2017): 1444–63. http://dx.doi.org/10.1017/aer.2017.70.
Full textKameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.
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