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Journal articles on the topic 'High Speed Parallel Adder'

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Published: 4 June 2021

Last updated: 12 February 2022

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Yagain, Deepa, Vijaya Krishna A, and Akansha Baliga. "Design of High-Speed Adders for Efficient Digital Design Blocks." ISRN Electronics 2012 (September 26, 2012): 1–9. http://dx.doi.org/10.5402/2012/253742.

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The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

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Hebbar, Abhishek R., Piyush Srivastava, and Vinod Kumar Joshi. "Design of High Speed Carry Select Adder using Modified Parallel Prefix Adder." Procedia Computer Science 143 (2018): 317–24. http://dx.doi.org/10.1016/j.procs.2018.10.402.

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Nirlakalla, Ravi, Rao Subba, and Talari Jayachandra-Prasad. "Performance evaluation of high speed compressors for high speed multipliers." Serbian Journal of Electrical Engineering 8, no. 3 (2011): 293–306. http://dx.doi.org/10.2298/sjee1103293n.

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This paper describes high speed compressors for high speed parallel multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). This paper presents 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. These compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, but the proposed 5-3 takes only 2 steps. These compressors are simulated with H-Spice at a temperature of 25?C at a supply voltage 2.0V using 90nm MOSIS technology. The Power, Delay, Power Delay Product (PDP) and Energy Delay Product (EDP) of the compressors are calculated to analyze the total propagation delay and energy consumption. All the compressors are designed with half adder and full Adders only.

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Chen, H. P., H. J. Liao, and J. B. Kuo. "BiCMOS dynamic full adder circuit for high-speed parallel multipliers." Electronics Letters 28, no. 12 (1992): 1124. http://dx.doi.org/10.1049/el:19920709.

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these two regarding area and power is Carry Select Adder (CSA). Parallel prefix adders are used to obtain quick results. In this course work, a new methodology to Modified Square Root Brent Kung adder (MSR-BK-A) is proposed to design an optimized adder and to calculate various performance parameters like area, power and delay for square root adder designs. By optimizing the structure of Binary-to-Excess-1 converter(BEC) and using it in Square Root BK adder, the power and delay can be reduced with a trade of in area. The simulated results conclude that, the MSR-BK-A with Modified BEC gives better performance in terms of power and delay. These designs have been simulated, verified and synthesized using Xilinx ISE 14.7 tool.

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Setia, Deepika, and Charu Madhu. "Novel Architecture of High Speed Parallel MAC using Carry Select Adder." International Journal of Computer Applications 74, no. 1 (2013): 32–38. http://dx.doi.org/10.5120/12851-9334.

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Thakur, Garima, Harsh Sohal, and Shruti Jain. "An Efficient Design of 8-bit High Speed Parallel Prefix Adder." Research Journal of Science and Technology 10, no. 2 (2018): 105. http://dx.doi.org/10.5958/2349-2988.2018.00015.3.

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Hobson, Richard F. "A framework for high-speed parallel-prefix adder performance evaluation and comparison." International Journal of Circuit Theory and Applications 43, no. 10 (2014): 1474–90. http://dx.doi.org/10.1002/cta.2020.

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Reddy Hemantha, G., S. Varadarajan, and M. N. Giriprasad. "DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications." International Journal of Engineering & Technology 7, no. 2.24 (2018): 197. http://dx.doi.org/10.14419/ijet.v7i2.24.12030.

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In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method. And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.

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Et. al., Barma Venkata RamaLakshmi. "Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (2021): 5673–83. http://dx.doi.org/10.17762/turcomat.v12i3.2242.

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This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computational speed multiplier plays a key role in performance of digital system. But the major drawback is it consumes more power , area and delay. To enhance the performance and decrease the area consumption and delay there are many algorithms and techniques. In this paper we designed a radix-8 Booth Multiplier using two parallel prefix adders and compared them for best optimized multiplier. The number of parital products generation can be reduced by n/3 by using radix-8 in the multiplier encoding. To further reduce the additions we have used booth recoding mechanism .We have implemented the design using Kogge stone adder and Brent kung adder. We observed that by using parallel prefix adders reduces the delay further more which results in significant increase in speed of the digital systems. The simulation results are carried out on XILINX VIVADO software.

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (2021): 1791. http://dx.doi.org/10.3390/electronics10151791.

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Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan, and M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics." Journal of Low Power Electronics 15, no. 3 (2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.

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Perri, Stefania, Marco Lanuzza, and Pasquale Corsonello. "Design of high-speed low-power parallel-prefix adder trees in nanometer technologies." International Journal of Circuit Theory and Applications 42, no. 7 (2013): 731–43. http://dx.doi.org/10.1002/cta.1886.

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WEI, SHUGANG, and KENSUKE SHIMIZU. "MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 129–44. http://dx.doi.org/10.1142/s0218126606002976.

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In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial products can be added to the sum at the same time. Two kinds of Booth recoding methods are also proposed to reduce the partial products from p to p/2. Therefore, the performance of a parallel modular multiplier can be modified by reducing half of the modular SD adders in the adder tree. For a serial modular multiplication, two partial products are generated from two Booth recoders and added to the sum by using one three-operand modular SD adder, so that the speed of the modular multiplication is three times as fast as the speed without using the three-operand modular SD adder and the Booth recoding method. A very large-scale integration (VLSI) implementation method by VHDL is also discussed. The design and simulation results show that high-speed modular multipliers can be obtained by the algorithms presented.

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Dimitrakopoulos, G., and D. Nikolos. "High-speed parallel-prefix VLSI Ling adders." IEEE Transactions on Computers 54, no. 2 (2005): 225–31. http://dx.doi.org/10.1109/tc.2005.26.

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Prof. Shweta Jain. "Design and Analysis of Low Power Hybrid Braun Multiplier using Ladner Fischer Adder." International Journal of New Practices in Management and Engineering 6, no. 03 (2017): 07–12. http://dx.doi.org/10.17762/ijnpme.v6i03.59.

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Multiplier is important in many DSP systems and in many hardware blocks. Multiplier are used in various DSP application like digital filtering, digital communication. This needs parallel array multiplier to attain high speed for execution and better performance. A specific array multiplier is implemented known as Braun design. Braun multiplier is the one which is a kind of parallel multiplier. It contains different CSA count of AND gates. Braun multiplier employing Ripple Carry Adder is developed here having high speed PPA. It will reduce the delay and implemented using Tanner EDA tool.

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jarani, S. V. Padma, and Dr M. Murali dhar. "Implementation of High Speed, Low Power and Area Efficient Parallel Prefix Adder in an FPGA." International Journal of Engineering Trends and Technology 25, no. 4 (2015): 212–18. http://dx.doi.org/10.14445/22315381/ijett-v25p239.

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LOKESH, P., U. SOMALATHA, and S. CHANDANA. "VLSI DESIGN OF LOW POWER HIGH SPEED PARALLEL SELF TIMED ADDER FOR ALU PROCESSING CIRCUITS." i-manager's Journal on Circuits and Systems 5, no. 4 (2017): 27. http://dx.doi.org/10.26634/jcir.5.4.13942.

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Ibrahim, Salah Hasan, Sawal Hamid Md Ali, and Md Shabiul Islam. "Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/131568.

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The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

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V.Padmajarani, S., and M. Muralidhar. "Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA." International Journal of Computer Applications 58, no. 1 (2012): 17–21. http://dx.doi.org/10.5120/9246-3410.

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Rashid, Muhammad, Malik Imran, and Asher Sajid. "An Efficient Elliptic-Curve Point Multiplication Architecture for High-Speed Cryptographic Applications." Electronics 9, no. 12 (2020): 2126. http://dx.doi.org/10.3390/electronics9122126.

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This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

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BASHAGHA, A. E., and M. K. IBRAHIM. "NONRESTORING RADIX-2k SQUARE ROOTING ALGORITHM." Journal of Circuits, Systems and Computers 06, no. 03 (1996): 267–85. http://dx.doi.org/10.1142/s0218126696000200.

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This paper presents a new high radix square rooting algorithm where a number of square root bits (one digit) are generated in one step. Therefore, the proposed algorithm offers a higher speed than that of the conventional bit parallel binary one. This algorithm can be considered as a generalisation of the conventional bit parallel binary algorithm, and therefore it can be implemented using the existing simple binary elements. The proposed algorithm makes use only of the odd values of the square root to generate the possible values of the radicand and therefore, it requires less area than the conventional restoring high radix algorithm which uses all the values of the square root. This algorithm is general for any radix. Any adder can be used in the basic cell, it can be a carry ripple adder or a carry lookahead adder. As an example of a radix-2k square root architecture, a 9-bit radix-23 architecture is presented in this paper.

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Babu, A. Madhu. "Evaluation of High Speed and Low Memory Parallel Prefix Adders." IOSR Journal of Electrical and Electronics Engineering 8, no. 4 (2013): 13–20. http://dx.doi.org/10.9790/1676-0841320.

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Kalampoukas, L., D. Nikolos, C. Efstathiou, H. T. Vergos, and J. Kalamatianos. "High-speed parallel-prefix module 2/sup n/-1 adders." IEEE Transactions on Computers 49, no. 7 (2000): 673–80. http://dx.doi.org/10.1109/12.863036.

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Penchalaiah, U., and Siva Kumar VG. "Survey: Performance Analysis of FIR Filter Design Using Modified Truncation Multiplier with SQRT based Carry Select Adder." International Journal of Engineering & Technology 7, no. 2.32 (2018): 243. http://dx.doi.org/10.14419/ijet.v7i2.32.13519.

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A recent years of technology development in Signal processing application a FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio processing, signal processing, software define radio and so on. Now a days in our environment will have more signal noises, and fluctuation due to technology development, here the Filter design is mainly configuring the priority to reduce the signal noises and fluctuation in all type of gadgets. In this project, the design contains Transpose form of high performance and high speed filter design using finite impulse response (FIR) filter with technique of pipelined inherently and supported multiple constant multiplication (MCM) in significant with saving power computation. In digital signal processing, the multiplier is a highly required thing, the example of parallel multiplier provide a high-speed and highly reliable method for multiplication, but this parallel multiplier will take large area and also power consumption. In the FIR filter design, multiplier and adders is the maximum priority will take to give the performance, but this MCM multiplier and Adders tree architecture will take large area and maximum power consumption in signal processing. So our Proposed approach of this work, will have replace the MCM multiplier to Truncated Multiplier and using the technique of Truncated based both Signed and Unsigned Operation with SQRT based Carry Select Adder (CSLA), and also replace the normal adders in FIR Filter to SQRT based Carry Select Adder (CSLA). In the proposed system of FIR Filter design results to be analysis with signed and unsigned Truncation using modified technique of HSCG-SCS based SQRT-CSLA and hence proved its more efficient than existing design, such as FIR filter for Truncation multiplier with SQRT-CSLA based Adders, FIR filter for Truncation multiplier with BEC based Adders, FIR filter for Truncation multiplier with RCA, and FIR filter for Truncation multiplier with Common Boolean logic based RCA, and finally implemented this design on VHDL with help of Xilinx FPGA-S6LX9 and shown the performance of proposed design in terms of delay, area, and power.

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N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.

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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

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MADHAVI, K., and P. DIVYA. "High –Speed Implementation of Design and Analysis by Using Parallel Prefix Adders." IOSR Journal of Electronics and Communication Engineering 12, no. 02 (2017): 44–49. http://dx.doi.org/10.9790/2834-1202024449.

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Elango, S., and P. Sampath. "Implementation of High Performance Hierarchy-Based Parallel Signed Multiplier for Cryptosystems." Journal of Circuits, Systems and Computers 29, no. 13 (2020): 2050214. http://dx.doi.org/10.1142/s021812662050214x.

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Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180[Formula: see text]nm, 90[Formula: see text]nm and 45[Formula: see text]nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo [Formula: see text] and [Formula: see text] signed arithmetic modules are implemented.

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Cui, Xiaoping, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander, and Fabrizio Lombardi. "Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders." Journal of Signal Processing Systems 90, no. 3 (2017): 409–19. http://dx.doi.org/10.1007/s11265-017-1249-3.

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MOHANA KANNAN, LOGANATHAN, and DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION." DYNA 96, no. 5 (2021): 505–11. http://dx.doi.org/10.6036/10214.

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Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

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Uma, R., and P. Dhavachelvan. "Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs." Research Journal of Applied Sciences, Engineering and Technology 7, no. 13 (2014): 2705–10. http://dx.doi.org/10.19026/rjaset.7.589.

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De, Mallika, and Bhabani P. Sinha. "Fast Parallel Multiplication Using Redundant Quarternary Number System." Parallel Processing Letters 07, no. 01 (1997): 13–23. http://dx.doi.org/10.1142/s0129626497000048.

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In this paper, we propose a high-speed VLSI multiplication scheme using redundant radix-4 representation of numbers. For m-digit by m-digit redundant radix-4 integer multiplication, we first generate m partial products, each of (m+1) digits in redundant radix-4 (RR-4) number system. These partial products are then added up four at a time by means of redundant quarternary adders. Parallel addition of four (m+1)-digit redundant radix-4 numbers can be performed in a constant time independent of m without any carry propagation. With these adders, multiplication of two m-digit numbers in RR-4 number system can be performed in ⌈(1/2)log2 m ⌉ + 1 steps of such additions of four RR-4 numbers. The number of computational elements of an m-digit multiplier based on the proposed algorithm is O(m2). Since the multiplier has a regular cellular array structure, it is suitable for VLSI implementation with O(m2 log m) AT-value.

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Mirzaei, Shahnam, Ryan Kastner, and Anup Hosangadi. "Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs." International Journal of Reconfigurable Computing 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/697625.

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We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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Wang, Wen Xing, and Xing Lin Cao. "Research on Multiform Circuit Multi-Carrier Transmitter in Smart Grid." Advanced Materials Research 204-210 (February 2011): 2214–16. http://dx.doi.org/10.4028/www.scientific.net/amr.204-210.2214.

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Transmitter is one of the communications-equipment in modern industrial. The basic principles of the transmitter is described in this article at fist, and then the multi-carrier multiple smart grid electricity transmitter is proposed. The transmitter takes advantage of multi-carrier communication technology and more effective solution to solve measurement data transmission problems in smart grid. In the carrier module, the source information with high-rate is changed into low-rate parallel data streams, and then is modulated, the modulation signal is added and changed into transmitted signal, and each carrier can use different modulation. Low-speed data is demodulated by appropriate demodulation mode at the receiving end, and then original data stream is synthesized by parallel -to-serial conversion.

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Divakara, S. S., Sudarshan Patilkulkarni, and Cyril Prasanna Raj. "Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic." International Journal of Image and Graphics 20, no. 03 (2020): 2050017. http://dx.doi.org/10.1142/s0219467820500175.

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Novel high-speed memory optimized distributed arithmetic (DA)-based architecture is developed and modeled for 3D discrete wavelet transform (DWT). The memory requirement for the proposed architecture is designed to [Formula: see text] pixel dynamic memory space and [Formula: see text] ROM. The proposed 3D-DWT architecture implements 9/7 Daubechies wavelet filters, synthesizes 7127 bytes of memory for temporary storage and uses 758 adders, 36 multiplexers of 16:1 and 36 up counter to realize the 3D-DWT hardware. The 3D-DWT engine is implemented and tested in a Xilinx FPGA Vertex5 XC5VLX155T with high area and power efficiency. The maximum delay in the timing path is 2.676[Formula: see text]ns and the 3D-DWT works at maximum frequency of 381[Formula: see text]MHz clock.

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Jain, Shivkaran, and Arun Kr Chatterjee. "Nand gate architectures for memory decoder." INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 7, no. 2 (2013): 610–14. http://dx.doi.org/10.24297/ijct.v7i2.3464.

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This paper presents some nand gate design styles which when used in decoder reduces energy consumption and delay. Basically conventional, nor style nand, source coupled nand is discussed. The three designs conventional, nor style nand, source coupled nand, ranges in area, speed and power. In nor style nand transistors are added in parallel so high fan-in is obtained and logical effort is reduced. In source coupled nand number of transistors are reduced it give speed of operation compared to an inverter. When simulated and compared it is found that nor style nand is 35% faster and 67 % more power efficient than conventional. Source coupled nand is found to be 36% faster and 82% more power efficient than conventional nand gate.

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Weymouth, Gabriel David, Robert Vance Wilson, and Frederick Stern. "RANS Computational Fluid Dynamics Predictions of Pitch and Heave Ship Motions in Head Seas." Journal of Ship Research 49, no. 02 (2005): 80–97. http://dx.doi.org/10.5957/jsr.2005.49.2.80.

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This work extends the previous effort in unsteady Reynolds averaged Navier-Stokes (RANS) simulations developed by the ship hydrodynamics group of the University of Iowa Iowa Institute of Hydraulic Research to the capability to predict pitch and heave motions of ships with forward speed in regular head seas. The simulations are performed with CFDSHIP-IOWA, which is a general-purpose, multiblock, high-performance parallel computing RANS code. Numerical verification studies in space and time demonstrate convergence for nearly all variables. The modified Wigley hull form experimental data presented in Journee (1992) are compared with simulation results over a range of Froude numbers, wavelengths, and wave amplitudes and found to give accurate results, with uncertainties less than 2%. Viscous ship motions characteristics are investigated by decomposing the full nonlinear problem into the forward speed diffraction and pitch and heave radiation problems, in the manner of strip theory. Comparisons between the current viscous RANS solutions and those from experiments, strip theory, and nonlinear potential flow simulations show the RANS method to predict damping and added mass coefficients with a high degree of accuracy.

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Isobe, Daishin, Noriyuki Hori, Shin Kawai, Keisuke Yagi, and Triet Nguyen-Van. "Digital Control of a Stepping Motor for Eliminating Rotation Speed Fluctuations Using Adaptive Gains." Electronics 10, no. 11 (2021): 1335. http://dx.doi.org/10.3390/electronics10111335.

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Nowadays, stepping motors are usually used as precise actuators in various new scientific fields, such as syringe pumps, blood analyzers, and bio-3D printers. Controlling rotation of the stepping motor without speed fluctuation under no-load conditions plays an important role in improving the accuracy of the machine’s drive. This paper proposes a digital control method for a five-phase hybrid stepping motor. The proposed controller includes an original control loop and a PI adaptive integration gain control loop. The original digital control loop is redesigned from the analog controller by using the direct PIM method. The PI adaptive control loop is added to the original control loop in a parallel way to remove a steady deviation of the motor and suppress a physical saturation factor inside the plant. Lyapunov stability theory is used to prove a stability condition of the PI regulator gains. Experimental results show that the proposed controller can suppress the chattering caused by the switching structure and gives performances as good as that of the commercial analog controller in a high rotation speed range without fluctuation.

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Krim, Saber, Soufien Gdaim, and Mohamed Faouzi Mimouni. "Robust Direct Torque Control with Super-Twisting Sliding Mode Control for an Induction Motor Drive." Complexity 2019 (June 24, 2019): 1–24. http://dx.doi.org/10.1155/2019/7274353.

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A field-programmable gate array- (FPGA-) based nonlinear Direct Torque Control (DTC) associated with Space Vector Modulation (SVM), Input-Output Feedback Linearization (IOFL), and second-order super-twisting speed controller is proposed to control an induction motor drive. First, the nonlinear IOFL is proposed to achieve a decoupled flux and torque control and the SVM technique is used to control the inverter switching frequency which reduces the torque ripples and noise. Next, to enhance the speed regulation, a super-twisting speed controller is added to an SVM-DTC-IOFL scheme. The nonlinear SVM-DTC-IOFL ensures a high dynamic response, good robustness under the external load disturbances. The Lyapunov theory is used to analyze the system stability. Then, this paper presents the interest of implementing the suggested SVM-DTC-IOFL using a Field-Programmable Gate Array (FPGA) circuit. The main interest of the FPGA-implementation is the reduction of the control loop delay, which is evaluated to a few microseconds, thanks to the parallel processing offered by the FPGA. The performances of the proposed control algorithm are investigated by digital simulation using the Xilinx system generator tool and an experimental implementation utilizing an FPGA-Virtex-5-ML507.

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Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

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AITHAL, GANESH, K. N. HARI BHAT, and U. SRIPATI ACHARYA. "HIGH-SPEED AND SECURE ENCRYPTION SCHEMES BASED ON CHINESE REMAINDER THEOREM FOR STORAGE AND TRANSMISSION OF MEDICAL INFORMATION." Journal of Mechanics in Medicine and Biology 10, no. 01 (2010): 167–90. http://dx.doi.org/10.1142/s0219519410003307.

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Medical records generated in hospitals often contain private and sensitive information. This privileged information must be prevented from falling into wrong hands. Thus, there is a strong need for developing a secure cryptographic scheme that can be adapted to use in conjunction with transmission and storage of medical information. Previous approaches have proposed the use of the advanced encryption standard (AES) algorithm for this purpose. In this article, we are proposing a new robust, high-speed, and secure cryptographic scheme that has the added advantage of being immune to side-channel attacks. In our article, we have shown that the performance of this scheme is superior in certain aspects to that of the A5/1 system used in global system for mobile (GSM) systems. The parallel architecture employed in this scheme makes it suitable to use in systems where the data-processing operations have to be carried out in real time. Residue number systems (RNS) based on Chinese remainder theorem (CRT) permits the representation of large integers in terms of combinations of smaller ones. The set of all CRT number system representation of an integer from 0 to M-1 with component wise modular addition and multiplication constitutes a direct sum of smaller commutative rings. An encryption and decryption algorithm based on the properties of direct sum of smaller rings offers distinct advantages over decimal or fixed radix arithmetic. We have utilized the representation of integers using CRT to successfully design additive, multiplicative, and affine stream cipher systems. The use of number system based on CRT allows speeding up the encryption/decryption algorithms, reduces the time complexity, and provides immunity to side-channel, algebraic, and known plain text attacks. In this article, the characteristics of additive, multiplicative, and affine stream cipher systems based on CRT number system representation have been studied and analyzed.

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Sheharyar, A., O. Bouhali, and A. Castaneda. "Speeding Up and Parallelizing the GARFIELD++." EPJ Web of Conferences 174 (2018): 06004. http://dx.doi.org/10.1051/epjconf/201817406004.

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Garfield++ is a toolkit for the simulation of particle detectors that use gas and semi-conductors as sensitive medium. It takes enormous amount of time to complete the simulation of complex scenarios such as those involving high detector voltages, gases with large gains, or electric field meshes with large number of elements. We observed that most of the simulation time is being consumed in finding the correct element in the electric field mesh. We optimized the element search operation and achieved significant boost in the speed up. In addition, We added the parallel computing support in the toolkit to simulate multiple events simultaneously over multiple machines. In this paper, we present our approach of speeding up the computations and benchmark results.

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SKAVANTZOS, ALEXANDER, MOHAMMAD ABDALLAH, and THANOS STOURAITIS. "LARGE DYNAMIC RANGE RNS SYSTEMS AND THEIR RESIDUE TO BINARY CONVERTERS." Journal of Circuits, Systems and Computers 16, no. 02 (2007): 267–86. http://dx.doi.org/10.1142/s0218126607003666.

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The Residue Number System (RNS) is an integer system appropriate for implementing fast digital signal processors. It can be used for supporting high-speed arithmetic by operating in parallel channels without need for exchanging information among the channels. In this paper, two novel RNS are proposed. First, a new RNS system based on the modulus set {2n+1, 2n - 1, 2n + 1, 2n + 2(n+1)/2 + 1, 2n - 2(n+1)/2 + 1}, n odd, is developed, along with an efficient implementation of its residue-to-weighted converter. The new RNS is a balanced five-modulus system, appropriate for large dynamic ranges. The proposed residue-to-binary converter is fast and hardware efficient and is based on a one's complement multi-operand adder that adds operands of size only 80% of the size dictated by the system's dynamic range. Second, a new class of multi-modulus RNS systems is proposed. These systems are based on sets consisting of two groups of moduli with the modulus product within one group being of the form 2a(2b - 1), while the modulus product within the other group is of the form 2c - 1. Their RNS-to-weighted converters are based on efficient combinations of the Chinese Remainder Theorem and Mixed Radix Conversion decoding techniques. Systems based on four, five, and seven moduli are constructed and analyzed. The new systems allow efficient implementations for their RNS-to-weighted decoders, imply fast and balanced RNS arithmetic, and may achieve large dynamic ranges. The presented residue-to-weighted converters for these systems rely on simple mod (2x - 1) hardware, which can be easily implemented as one's complement hardware.

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Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

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Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

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Panjeta, Ashwani. "Synthesis of High Speed Full Adder." International Journal of Engineering Trends and Technology 9, no. 5 (2014): 223–27. http://dx.doi.org/10.14445/22315381/ijett-v9p245.

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Naga Babu, Ch, P. Naga Siva Sai, Ch Priyanka, K. Hari Kishore, M. Bindu Bhargavi, and K. Karthik. "Comparative Analysis of High Speed Carry Skip Adders." International Journal of Engineering & Technology 7, no. 2.24 (2018): 121. http://dx.doi.org/10.14419/ijet.v7i2.24.12015.

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In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer.

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Prihozhy, A. A. "Synthesis of parallel adders from if-decision diagrams." «System analysis and applied information science», no. 2 (August 18, 2020): 61–70. http://dx.doi.org/10.21122/2309-4923-2020-2-61-70.

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Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. Since traditional binary decision diagrams does not match perfectly with the task of modelling adder architectures, other types of diagram were proposed. If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n) and area complexity of Ο(n×log2n). The paper propose a technique, which produces adder diagrams with such properties by systematically cutting the diagram’s longest paths. The if-diagram based adders are competitive to the known efficient Brent-Kung adder and its numerous modifications. We propose a blocked structure of the parallel if-diagram-based adders, and introduce an adder table representation, which is capable of systematic producing if-diagram of any bit-width. The representation supports an efficient mapping of the adder diagrams to VHDL-modules at structural and dataflow levels. The paper also shows how to perform the adder space exploration depending on the circuit fan-out. FPGA-based synthesis results and case-study comparisons of the if-diagram-based adders to the Brent-Kung and majority-invertor gate adders show that the new adder architecture leads to faster and smaller digital circuits.

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Shraim, H., Y. Harkouss, and H. Bazzi. "A novel hybrid back-stepping and fuzzy logic control strategy for a quadcopter." Aeronautical Journal 121, no. 1244 (2017): 1444–63. http://dx.doi.org/10.1017/aer.2017.70.

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ABSTRACTThis article aims to present a novel control strategy for quadrotor helicopter. It is composed of three main parts constituting the system modelling, the integral back-stepping control, and fuzzy logic compensator. In the first part, a non-linear model is presented taking in consideration some non-linearities and variables that are usually neglected. In the second part, a controller based on the integral back-stepping algorithm has been developed for the system in order to make the system follows a desired path. However, due to complexity of paths and to the presence of unknown disturbances, a fuzzy logic compensator is added in parallel to the integral back-stepping controller to improve trajectory tracking in some critical conditions (high wind speed, mass variation, etc.). Simulation results have been presented to show the effectiveness of the proposed approach.

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Kameyama, Michitaka. "Special Issue on Computer Architecture for Robotics." Journal of Robotics and Mechatronics 2, no. 6 (1990): 417. http://dx.doi.org/10.20965/jrm.1990.p0417.

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In the realization of intelligent robots, highly intelligent manipulation and movement techniques are required such as intelligent man-machine interfaces, intelligent information processing for path planning and problem solutions, practical robot vision, and high-speed sensor signal processing. Thus, very high-speed processing to cope with vast amounts of data as well as the development of various algorithms has become important subjects. To fulfill such requirements, the development of high-performance computer architecture using advanced microelectronics technology is required. For these purposes, the development of implementing computer systems’ for robots will be classified as follows: (a) Use of general-purpose computers As the performance of workstations and personal computers is increased year by year, software development is the major task without requiring hardware development except the interfaces with peripheral equipment. Since current high-level languages and software can be applied, the approach is excellent in case of system development, but the processing performance is limited. (b) Use of commercially available (V) LSI chips This is an approach to design a computer system by the combination of commercially available LSIs. Since the development of both hardware and software is involved in this system development, the development period tends to be longer than in (a). These chips include general-purpose microprocessors, memory chips, digital signal processors (DSPs) and multiply-adder LSIs. Though the kinds of available chips are limited to some degree, the approach can cope with a considerably high-performance specifications because a number of chips can be flexibly used. (c) Design, development and system configuration of VLSI chips This is an approach to develop new special-purpose VLSI chips using ASIC (Application Specific Integrated Circuit) technology, that is, semicustom or full-custom technology. If these attain practical use and are marketed, they will be widely used as high-performance VLSI chips of the level (b). Since a very high-performance specification must be satisfied, the study of very high performance VLSI computer architecture becomes very important. But this approach involving chip development requires a very long period in the design-development from the determination of processor specifications to the system configuration using the fabricated chips. For the above three approaches, the order from the viewpoint of ease of development will be (a), (b) and (c), while that from the viewpoint of performance will be (c), (b) and (a). Each approach is not exclusive but is complementary each other. For example, the development of new chips by (c) can also give new impact as the components of (a) and (b). Further, the common point of these approaches is that performance improvement by highly parallel architecture becomes important. This special edition introduces, from the above standpoint, the latest information on the present state and' future prospects of the computer techniques in Japan. We hope that this edition will contribute to the development of this field.

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