Relevant bibliographies by topics / High-speed receiver / Dissertations / Theses
To see the other types of publications on this topic, follow the link: High-speed receiver.

Dissertations / Theses on the topic 'High-speed receiver'

Author: Grafiati
Published: 7 June 2025
Last updated: 2 August 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 dissertations / theses for your research on the topic 'High-speed receiver.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.

1

Bengtson, Håkan. "High speed CMOS optical receiver /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek904s.pdf.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Lu, Dongtian. "High speed CMOS ADC for UWB receiver /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LUD.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

AMIN, HANJANI AMIR H. "HIGH-SPEED OPTICAL INTERCONNECTS FOR VIDEO MEMORY." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin980789378.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Chiu, Chin-Yung. "A High Speed Digital Receiver for An Instrumentation Radar System." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu985236061.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Schow, Clint Lee. "Development of a high-speed, monolithically integrated silicon optical receiver /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Bai, Yun. "High-speed energy-efficient on-chip interconnect driver and receiver /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Wan, Wen-Jyh. "An implementation of the SNR high speed network communication protocol (receiver part)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA294602.

Full text
Abstract:
Thesis (M.S. in Electrical Engineering and M.S. in Computer Science) Naval Postgraduate School, March 1995.<br>"March 1995." Thesis advisor(s): G. M. Lundy, S. B. Shukla. Includes bibliographical references. Also available online.
APA, Harvard, Vancouver, ISO, and other styles
8

Korhonen, Juha Olavi. "MIMO receiver processing for high speed downlink packet access in 3G wireless." Thesis, University of Cambridge, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.613737.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Claussen, Holger. "Low complexity receiver architectures for high-speed wireless multiple-input multiple-output (MIMO) systems." Thesis, University of Edinburgh, 2004. http://hdl.handle.net/1842/13431.

Full text
Abstract:
In modern wireless networks the demand for high-speed transmissions is ever increasing to provide access to data and enable new services anywhere and anytime. Mobile internet, video telephony, music and video on demand are examples for the possible applications which demand high data rates. However, the available frequency spectrum is limited and expensive. To satisfy the demand for high data-rates, turbo-encoded multiple-input multiple-output (MIMO) radio links have been recently proposed for the support of high-speed downlink packet access (HSDPA) in UMTS, where the re-use of spreading codes
APA, Harvard, Vancouver, ISO, and other styles
10

Isautier, Pierre Paul Roger. "Autonomous receivers for next-generation of high-speed optical communication networks." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54418.

Full text
Abstract:
Advances in fiber optic communications and the convergence of the optical-wireless network will dramatically increase the network heterogeneity and complexity. The goal of our research is to create smart receivers that can autonomously identify and demodulate, without prior knowledge, nearly any signal emerging from the next-generation of high-speed optical communication networks.
APA, Harvard, Vancouver, ISO, and other styles
11

Chabata, Tichakunda Valentine. "Higher order modulation formats for high speed optical communication systems with digital signal processing aided receiver." Thesis, Nelson Mandela Metropolitan University, 2016. http://hdl.handle.net/10948/4775.

Full text
Abstract:
The drastic increase in the number of internet users and the general convergence of all other communication systems into an optical system have brought a sharp rise in demand for bandwidth and calls for high capacity transmission networks. Large unamplified transmission reach is another contributor in reducing deployment costs of an optical communication system. Spectrally efficient modulation formats are suggested as a solution to overcome the problems associated with limited channels and bandwidth of dense wavelength division multiplexing (DWDM) optical communication systems. Higher order mo
APA, Harvard, Vancouver, ISO, and other styles
12

Zhao, Shaohua, and 趙少華. "The design of transmitter/receiver and high speed analog to digital converters in wireless communication systems: a convex programming approach." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B41290525.

Full text
APA, Harvard, Vancouver, ISO, and other styles
13

Zhao, Shaohua. "The design of transmitter/receiver and high speed analog to digital converters in wireless communication systems : a convex programming approach /." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B41290525.

Full text
APA, Harvard, Vancouver, ISO, and other styles
14

Platt, Simon Philip. "Very high speed photodetectors." Thesis, University of Leeds, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.277891.

Full text
APA, Harvard, Vancouver, ISO, and other styles
15

Tang, Wei 1976. "High-speed parallel optical receivers." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103298.

Full text
Abstract:
Parallel optical interconnects (POI) have attracted a great deal of attention in the past two decades as the system bandwidth continues to increase. Optical interconnects are known to have more advantages than their electrical counterparts in many aspects such as crosstalk, bandwidth distance product, power consumption, and RC time delay. The parallelization of several optical links is also an effective method to increase the aggregate data rate while keeping the component count manageable and to reduce the unit cost of optics, electronics, and packaging at lower line rate.<br>Parallel optical
APA, Harvard, Vancouver, ISO, and other styles
16

Zargaran, Yazd Arash. "Design techniques for high-speed low-power wireline receivers." Thesis, University of British Columbia, 2013. http://hdl.handle.net/2429/44660.

Full text
Abstract:
High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal. In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation registe
APA, Harvard, Vancouver, ISO, and other styles
17

Zicha, Nicholas. "High-speed optical receivers in nanometer complementary metal-oxide-semiconductor (CMOS)." Thesis, McGill University, 2009. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=40665.

Full text
Abstract:
Optical interconnects have attracted great interest as data rates continue to increase. When compared with their electrical counterparts, optical interconnects have significant advantages in terms of crosstalk, bandwidth, distance, and latency. Many applications stand to benefit from low-cost, high-speed integrated optical transceivers with single-channel gigabit data rates. As in the case of RF wireless designs, using CMOS technology is of special interest due to the potential of lower cost and higher integration. The analog frontend is a key component in optical receivers due to its import
APA, Harvard, Vancouver, ISO, and other styles
18

Newaskar, Puneet Prashant 1978. "High-speed data conversion for digital ultra-wide-band radio receivers." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87359.

Full text
Abstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.<br>Includes bibliographical references (leaves 115-117).<br>by Puneet Prashant Newaskar.<br>S.M.
APA, Harvard, Vancouver, ISO, and other styles
19

Haroun, Mostafa. "Low-power high-speed high-resolution delta-sigma modulators for digital TV receivers in nanometer CMOS." Thesis, McGill University, 2014. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=123106.

Full text
Abstract:
The use of high-speed high-resolution analog-to-digital converters (ADCs) allows part of the signal processing to be done in the digital domain allowing for higher system integration and cheaper fabrication. Becoming more in use, hand-held devices have low-power requirements to allow for longer battery life. Also, designing ADCs in nanometer digital CMOS technologies make them more integrable with digital processing blocks and cheaper. This thesis aims at designing a high-speed (16MS/s conversion rate) high-resolution (12bits) Delta-Sigma modulator with low-power consumption in nanometer CMOS.
APA, Harvard, Vancouver, ISO, and other styles
20

Gu, Zheng [Verfasser]. "High Speed CMOS ICs for 10 Gbit/s Optical Fiber Communication Receivers / Zheng Gu." Aachen : Shaker, 2005. http://d-nb.info/1186588381/34.

Full text
APA, Harvard, Vancouver, ISO, and other styles
21

Ferreira, João Manuel Graça. "An high-speed parametric ADC and a co-designed mixer for CMOS RF receivers." Master's thesis, Faculdade de Ciências e Tecnologia, 2009. http://hdl.handle.net/10362/3933.

Full text
Abstract:
Dissertação apresentada na faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores<br>The rapid growth of wireless communications and the massive use of wireless end-user equipments have created a demand for low-cost, low-power and low-area devices with tight specifications imposed by standards. The advances in CMOS technology allows, nowadays, designers to implement circuits that work at high-frequencies, thus, allowing the complete implementation of RF front ends in a single chip. In this work, a
APA, Harvard, Vancouver, ISO, and other styles
22

Varzaghani, Aida. "Analog to digital conversion with embedded channel equalization for high-speed serial link receivers." Diss., Restricted to subscribing institutions, 2007. http://proquest.umi.com/pqdweb?did=1568170451&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

Full text
APA, Harvard, Vancouver, ISO, and other styles
23

BOZORGI, MOOZIRAJI FARHAD. "High Speed 3D-Integrated Silicon Photonic Optical Receivers in PIC25G and BiCMOS-55nm Technology." Doctoral thesis, Università degli studi di Pavia, 2020. http://hdl.handle.net/11571/1329173.

Full text
Abstract:
This thesis presents 2 versions of 3D-integrated Opto-Electrical Receiver (RX) front-end: RX-I and the RX-II. The Electronic Integrated Circuit (EIC) in both RX is fabricated in a BiCMOS-55nm technology, flipped and placed on top of the Photonic Integrated Circuits (PIC) die through copper pillars. In RX-I chain, a Fully Differential Shunt-Feedback Trans-Impedance Amplifier (FD-SF TIA) is followed by a Limiting Amplifiers (LA) with embedded equalization, output driver and an automatic offset cancellation loop. The whole receiver provides a Trans-Impedance (TI) gain of 76dBΩ with 30GHz bandwid
APA, Harvard, Vancouver, ISO, and other styles
24

Chuah, Alan E. L. "Design and implementation of high-speed transmitters and receivers for optical interconnects in CMOS technology." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=33964.

Full text
Abstract:
Optoelectronic very-large scale integrated (OE-VLSI) technology provides for the integration of photonic devices, such as the laser-diode and the photodiode, with silicon VLSI electronics. This technology is capable of providing high bandwidth and high-density optical input/output (I/O) to silicon VLSI chips, with an aggregate data bit rate of over a Terabit per second. The development of the vertical-cavity surface-emitting laser (VCSEL) and the high-speed p-i-n photodiode has made this technology possible. Optical transmitter and receiver circuits are responsible for the interfacing between
APA, Harvard, Vancouver, ISO, and other styles
25

Kim, Seokjin. "High-speed analog-to-digital converters for modern satellite receivers design verification test and sensitivity analysis /." College Park, Md.: University of Maryland, 2008. http://hdl.handle.net/1903/7864.

Full text
Abstract:
Thesis (Ph. D.) -- University of Maryland, College Park, 2008.<br>Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
APA, Harvard, Vancouver, ISO, and other styles
26

Chan, Kwong Hang Kevin. "An Analysis of Wireless High-speed Data Services for Cellular CDMA Systems." Thesis, University of Waterloo, 2002. http://hdl.handle.net/10012/860.

Full text
Abstract:
The interest in the development of wireless high-speed data services is in response to the strong market demand for high-speed wireless Internet access. Current standards aim at delivering a peak data rate greater than 2Mbps on the forward link. Since data services and voice services are fundamentally different, new concepts were introduced in the design of the forward data channel. In addition, methods of evaluating the performance of a cellular CDMA system have to be revisited. This thesis proposes a method which can be used to find the forward link peak and average data rates, throu
APA, Harvard, Vancouver, ISO, and other styles
27

Carlowitz, Christian, Thomas Girg, Hatem Ghaleb, and Xuan-Quang Du. "Efficient Ultra-High Speed Communication with Simultaneous Phase and Amplitude Regenerative Sampling (SPARS)." De Gruyter, 2017. https://tud.qucosa.de/id/qucosa%3A38596.

Full text
Abstract:
For ultra-high speed communication systems at high center frequencies above 100 GHz, we propose a disruptive change in system architecture to address major issues regarding amplifier chains with a large number of amplifier stages. They cause a high noise figure and high power consumption when operating close to the frequency limits of the underlying semiconductor technologies. Instead of scaling a classic homodyne transceiver system, we employ repeated amplification in single-stage amplifiers through positive feedback as well as synthesizer-free self-mixing demodulation at the receiver to simp
APA, Harvard, Vancouver, ISO, and other styles
28

HUANG, JUN-ZHONG, and 黃俊中. "High speed optical receiver using discrete components." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/88172126067732066317.

Full text
APA, Harvard, Vancouver, ISO, and other styles
29

Huang, Sheng-Yao, and 黃聖堯. "A High-gain High-speed Fully-integrated CMOS Optical Receiver." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/20175329597308832334.

Full text
Abstract:
碩士<br>國立雲林科技大學<br>電子工程系<br>103<br>A high-gain high-speed fully-integrated CMOS optical receiver designed in UMC 0.18μm 1P6M CMOS process technology for visible light wireless communications is presented in this thesis. The regulated cascade (RGC) gain stage is adopted before the transimpedance amplifier (TIA) to reduce the effect of the input photodiode capacitance (CPD). The equalizer (EQ) and the post amplifier (PA) are adopted to increase the bandwidth and gain, respectively. The optical receiver achieves a total transimpedance gain of 124dBΩ and the bandwidth of 3.02GHz in the presence of
APA, Harvard, Vancouver, ISO, and other styles
30

Chen, Kuan-Chang. "Energy-Efficient Receiver Design for High-Speed Interconnects." Thesis, 2022. https://thesis.library.caltech.edu/14318/9/chen_kuan-chang_2022_thesis_final.pdf.

Full text
Abstract:
<p>High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise
APA, Harvard, Vancouver, ISO, and other styles
31

Abiri, Behrooz. "High Speed Clock and Data Recovery Techniques." Thesis, 2011. http://hdl.handle.net/1807/30162.

Full text
Abstract:
This thesis presents two contributions in the area of high speed clock and data recovery systems. These contributions are focused on the fast phase recovery and adaptive equalization techniques. The first contribution of this thesis is an adaptive engine for a 2x blind sampling receiver. The proposed adaptation engine is able to find the phase-dependent DFE coefficients of the receiver on the fly. The second contribution is a burst-mode clock and data recovery architecture which uses an analog phase interpolator. The proposed burst-mode CDR is capable of locking to the first data transition
APA, Harvard, Vancouver, ISO, and other styles
32

Chow, Jeffrey. "A VLSI receiver architecture for high speed ATM computer networks." Thesis, 1994. http://hdl.handle.net/2429/5199.

Full text
Abstract:
Network communication bandwidths are surpassing the computational power of host systems. This improvement in communications bandwidth creates a need to develop ded icated communications processors which service the network without serious degradation of throughput. Asynchronous Transfer Mode(ATM) is a new Broadband Integrated Services Digital Network(BISDN) protocol specified to operate over fibre lines at rates of 155 Mbps or 622 Mbps. As the high-speed ATM networking protocol gains widespread acceptance in the networking community, dedicated high-speed protocol processing hardware is r
APA, Harvard, Vancouver, ISO, and other styles
33

曹太和. "High speed CMOS receiver for non-directive infrared wireless data communication." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/21030087557040026406.

Full text
APA, Harvard, Vancouver, ISO, and other styles
34

Chien, Feng-Tso, and 簡鳳佐. "High Speed Transimpedance Amplifier Design and ITs Application on Optical Receiver." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/38312714071329115718.

Full text
Abstract:
博士<br>國立中央大學<br>電機工程研究所<br>88<br>ABSTRACT Monolithic GaAs MESFETs transimpedance (TZ) amplifier has been designed, fabricated, and characterized. Symmetric and asymmetric TZ amplifiers are fabricated and described. Two different active feedback architectures, CG-FET and GS-FET, are compared with each other. By using a GS-FET TZ amplifier, the gain linearity and bandwidth of TZ amplifier could be improved but the tunable capability would be sacrificed. A capacitive-peaking method to improve the bandwidth of TZ amplifier was proposed and investigated. By using
APA, Harvard, Vancouver, ISO, and other styles
35

LIAO, CHUAN-YU, and 廖泉裕. "Fabrication of 400-Gb/s High-speed PAM-4 Optical Receiver Module." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/v9d2t6.

Full text
Abstract:
碩士<br>國立高雄應用科技大學<br>電子工程系<br>106<br>This thesis successfully developed a small form-factor pluggable (SFP-LR) optical transceiver and a 4-level pulse amplitude modulation (PAM-4) optical receiver. For SFP-LR optical transceiver, the distributed feedback (DFB) laser diode (LD) at 1310nm was used in the TO-56 coaxial packaged transmitter optical subassembly (TOSA) module that was used at the transmitter. For the receiver, the photodiode (PD) and transimpedance amplifier (TIA) were used in the TO-46 coaxial packaged receiver optical subassembly (ROSA) module. And the transceiver modules can be co
APA, Harvard, Vancouver, ISO, and other styles
36

Dong, Yunzhi. "A High-speed Fiber-optic Receiver for Plastic Optical Fiber Applications in 65 nm CMOS process." Thesis, 2012. http://hdl.handle.net/1807/33978.

Full text
Abstract:
This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers
APA, Harvard, Vancouver, ISO, and other styles
37

LI, XUN-CHENG, and 李訓誠. "Design of timing recovery and pulse regeneration circuits for high speed optical receiver." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/92519387789762676129.

Full text
APA, Harvard, Vancouver, ISO, and other styles
38

Huang, Wen-Chieh, and 黃文杰. "Clock and Data Recovery Circuit and Equalizer for High-Speed Serial-Link Receiver." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/90238237373551825752.

Full text
Abstract:
碩士<br>國立交通大學<br>電子研究所<br>100<br>With the advances in information technology, the demand of high speed transmission increase with each passing day. But the limitation bandwidth of the channel will causes the inter-symbol interference (ISI) when the data passes through the channel. ISI may cause wrong symbol detection. Therefore, the equalizer, which can be used to compensate for the channel loss, play an important role in high speed transmission. In this thesis, we propose a high speed serial link receiver that operates at 8 Gbps. The receiver includes an analog equalizer, a decision feedback e
APA, Harvard, Vancouver, ISO, and other styles
39

Lai-li, KANG, and 康來利. "Wideband Code Division Multiple Access Downlink Baseband Receiver for High Speed Downlink Packet Access." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/60504448823847292828.

Full text
Abstract:
碩士<br>國立臺灣大學<br>電機工程學研究所<br>91<br>We are now in an epoch of mobile communication. According to the report of newspaper, the ratio of people owning mobile phones in Taiwan has reached 93%. Among numerous wireless communication technologies, WCDMA (Wideband Code Division Multiple Access) is a more advanced technology. The specification of WCDMA has been set by Third Generation Partner Project (3GPP) organization. The main feature of WCDMA is the Orthogonal Variable Spreading Factor (OVSF) codes that are used to preserve the orthogonality between different physical channels, and furthermore they
APA, Harvard, Vancouver, ISO, and other styles
40

Yin, Wei-Shun, and 殷偉舜. "A high-speed optical receiver with a noise cancellation network in 0.18um CMOS technology." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/59007617914737211799.

Full text
Abstract:
碩士<br>國立雲林科技大學<br>電子工程系<br>103<br>This thesis presents a high-speed optical receiver with Noise Cancellation Network (NCN) for optical wireless communications implemented in UMC 0.18μm 1P6M CMOS process technology. By employing the noise cancellation network, the optical receiver can filter the low-frequency ambient photocurrent noise. The bandwidth and gain of the optical receiver are further enhanced by adopting the equalizer (EQ) and limiting amplifier (LA), respectively. The proposed optical receiver shows the total transimpedance gain of 91.7dBΩ and the bandwidth of 2.71GHz in the presenc
APA, Harvard, Vancouver, ISO, and other styles
41

Lai, Jecy, and 賴俊傑. "The Start-up Timing Recovery on Single-Pair High-Speed Digital Subscriber Line (SHDSL) Receiver." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/04782636175770815127.

Full text
Abstract:
碩士<br>國立交通大學<br>電信工程系所<br>93<br>We will confer the timing recovery of the SHDSL by the Recommendation G994.1 handshake procedure. This Recommendation provides a flexible mechanism for various Digital Subscriber Line (DSL) transceivers at the start-up procedure. SHDSL technology was available over a single pair copper line with single tone carrier frequency, for the implement of the timing recovery by the Recommendation, we provide architecture that base on the Non-linear Spectral Line method and non-data aided with all-digital way without additional control circuit adjusting the real clock tim
APA, Harvard, Vancouver, ISO, and other styles
42

Tripathi, Samarth. "FPGA Based Low Cost JTOL & BER Platform for Receiver Characterization of A High Speed Serial Link PHY." Thesis, 2016. http://ethesis.nitrkl.ac.in/9204/1/2016_MT_STripathi.pdf.

Full text
Abstract:
In the field of VLSI there has always been three main factors of concern i.e. Cost, Area, Speed. In High Speed applications with the increase in data rates there is always an issue surrounding the Signal Integrity of the signal being transmitted and received across the receiver side. At high frequencies there are possibilities of the data being transferred is not a pure signal but a jittered one with some Error Rate. In the industries Receiver Characterization is based on loopback methodology which involves the utilization of some High end Instruments which is costly and also Time to market is
APA, Harvard, Vancouver, ISO, and other styles
43

Tahmoureszadeh, Tina. "Analog Front-end Design for 2x Blind ADC-based Receivers." Thesis, 2010. http://hdl.handle.net/1807/29988.

Full text
Abstract:
This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward
APA, Harvard, Vancouver, ISO, and other styles
44

Herath, Vijitha Rohana [Verfasser]. "High-speed MOS ICs for an signal processor input interface of an optical synchronous QPSK receiver and related clock distribution issues / von Vijitha Rohana Herath." 2009. http://d-nb.info/993617948/34.

Full text
APA, Harvard, Vancouver, ISO, and other styles
45

Sarvari, Siamak. "A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS." Thesis, 2010. http://hdl.handle.net/1807/29987.

Full text
Abstract:
This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation
APA, Harvard, Vancouver, ISO, and other styles
46

Dunwell, Dustin. "Adaptive Receivers for High-speed Wireline Links." Thesis, 2013. http://hdl.handle.net/1807/35810.

Full text
Abstract:
This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal
APA, Harvard, Vancouver, ISO, and other styles
47

Lee, Chihun, and 李志虹. "CMOS High-Speed Analog Key Components for Broadband Receivers." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/00701825746384056864.

Full text
Abstract:
博士<br>國立臺灣大學<br>電子工程學研究所<br>95<br>Moore’s law has driven CMOS technologies toward broadband communication systems, which contains high-data-rate wireless communications (ISI/mm-Wave band and Radar), and high-capacity wireline communications (SONET/SDH, Fiber Channel, and Gigabit Ethernet). To realize Gb/s broadband transceivers, both front-end and clock generator play one of the critical roles. In this dissertation, CMOS high-speed analog key components for broadband receivers are presented. Even though III-V or bipolar processes had been widely used in 40Gb/s and 60GHz transceivers, they may
APA, Harvard, Vancouver, ISO, and other styles
48

Huang, Shih-Hao, and 黃世豪. "High-Speed CMOS Optical Receivers with Monolithically Integrated Photodiode." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/54178705580229038996.

Full text
Abstract:
博士<br>國立交通大學<br>電子工程學系 電子研究所<br>103<br>To sustain the high-throughput requirements of the data center, more and more data bandwidth of short-reach optical-links are required. They should achieve the performance, such as low cost, small-form factor, high energy efficiency, high bandwidth, high sensitivity, and high integration. To achieve these design goals, two PDs and three optical receivers are proposed. By using CMOS technology, the PD bandwidth generally dominates the receiver operating speed. In this dissertation, two high-speed PDs are proposed for Gb/s operation. One is Lateral PIN dete
APA, Harvard, Vancouver, ISO, and other styles
49

Lee, Chihun. "CMOS High-Speed Analog Key Components for Broadband Receivers." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1607200717241200.

Full text
APA, Harvard, Vancouver, ISO, and other styles
50

Sankaralingam, Rajkumar. "High-speed photodetectors and receivers for long-haul communication systems." 2005. http://etd.nd.edu/ETD-db/theses/available/etd-10102005-140811/.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the bibliographies on the topic 'High-speed receiver' for other source types:
Journal articles Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography