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Journal articles on the topic 'High-speed receiver'

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1

Bulbakov, I. S., E. V. Atkin, and A. G. Voronin. "High speed SLVS transmitter and receiver." Journal of Physics: Conference Series 675, no. 4 (2016): 042035. http://dx.doi.org/10.1088/1742-6596/675/4/042035.

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2

Woo, S. H., K. W. Yoon, Y. K. Moon, et al. "High Speed Receiver for Capsule Endoscope." Journal of Medical Systems 34, no. 5 (2009): 843–47. http://dx.doi.org/10.1007/s10916-009-9298-1.

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3

Williams, K. J., M. L. Dennis, I. N. Duling, C. A. Villarruel, and R. D. Esman. "A simple high-speed high-output voltage digital receiver." IEEE Photonics Technology Letters 10, no. 4 (1998): 588–90. http://dx.doi.org/10.1109/68.662603.

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4

Luo, Pu. "DLL-Based Receiver for High Speed Data Transmission." Advanced Materials Research 753-755 (August 2013): 2471–74. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2471.

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For modern high speed DAC, receiving data reliably from FPGA is a big challenge, data-independent skew is the major problem. usually system employ data clock while transmitting LVDS data from FPGA. then LVDS data is latched by delayed data clock which generated by DLL in chip. Because DLL has a negative feedback loop, system suffer small effect of PVT variations, robustness is guaranteed. The receiving circuits were implemented in a all-digital 0.18μm CMOS technology ,occupies 0.7 mm2 of area. It operates in the frequency range of 20 MHz~600 MHz.
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5

Dazeng Feng, Wei Qian, Hong Liang, B. J. Luff, and M. Asghari. "High-Speed Receiver Technology on the SOI Platform." IEEE Journal of Selected Topics in Quantum Electronics 19, no. 2 (2013): 3800108. http://dx.doi.org/10.1109/jstqe.2012.2213804.

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6

Dutta, Aloke K. "High Speed Receiver Circuit Designs for Fiber Optic Communications." IETE Journal of Education 38, no. 3-4 (1997): 213–23. http://dx.doi.org/10.1080/09747338.1997.11415679.

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7

Pi Yang Chiang and Ming-Seng Kao. "High-speed optical receiver with soft decision ISI cancellation." Journal of Lightwave Technology 11, no. 2 (1993): 343–50. http://dx.doi.org/10.1109/50.212546.

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8

Ko, Young-Ho, Joong-Seon Choe, Won Seok Han, et al. "High-speed waveguide photodetector for 64 Gbaud coherent receiver." Optics Letters 43, no. 3 (2018): 579. http://dx.doi.org/10.1364/ol.43.000579.

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9

Aiki, M. "Low-noise optical receiver for high-speed optical transmission." IEEE Transactions on Electron Devices 32, no. 12 (1985): 2693–98. http://dx.doi.org/10.1109/t-ed.1985.22400.

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10

Aiki, M. "Low-noise optical receiver for high-speed optical transmission." Journal of Lightwave Technology 3, no. 6 (1985): 1301–6. http://dx.doi.org/10.1109/jlt.1985.1074345.

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11

Da Silva, Marco Jose, Eduardo N. Dos Santos, and Tiago P. Vendruscolo. "High-speed multichannel impedance measuring system." ACTA IMEKO 1, no. 1 (2012): 36. http://dx.doi.org/10.21014/acta_imeko.v1i1.18.

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In this paper, a novel high-speed multichannel impedance measuring system in presented. The measurements are based on simultaneous excitation with two distinct frequencies to interrogate the multiple sensing point of a given sensor. Received signals are analogue-to-digital converted (with a DAQ card) and the amplitudes of each frequency are determined using FFT implemented in LabVIEW. The capacitive and conductive parts of impedance are calculated based on amplitude measurements. The developed system can operate 8 transmitter and 8 receiver electrodes at a frame repetition frequency of up to 7
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12

Jin-Sung Youn, Hyo-Soon Kang, Myung-Jae Lee, Kang-Yeob Park, and Woo-Young Choi. "High-Speed CMOS Integrated Optical Receiver With an Avalanche Photodetector." IEEE Photonics Technology Letters 21, no. 20 (2009): 1553–55. http://dx.doi.org/10.1109/lpt.2009.2029869.

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13

Ragab, Ahmed, Yang Liu, Kangmin Hu, Patrick Chiang, and Samuel Palermo. "Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links." Journal of Electrical and Computer Engineering 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/982314.

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High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be
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14

Govindarajan, M., S. Siala, and R. N. Nottenburg. "Optical receiver systems for high speed parallel digital data links." Journal of Lightwave Technology 13, no. 7 (1995): 1555–65. http://dx.doi.org/10.1109/50.400724.

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15

Lee, Moon Ho. "Matrix Inversion Algorithm: Applications in High Speed MIMO LTE Receiver." American Journal of Networks and Communications 1, no. 1 (2012): 1. http://dx.doi.org/10.11648/j.ajnc.20120101.11.

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16

Fischer, J. K., R. Ludwig, L. Molle, et al. "High-Speed Digital Coherent Receiver Based on Parallel Optical Sampling." Journal of Lightwave Technology 29, no. 4 (2011): 378–85. http://dx.doi.org/10.1109/jlt.2010.2090132.

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17

Yasuoka, N., T. Sanada, H. Hamaguchi, et al. "High-speed monolithic coherent optical receiver integrated on InP substrate." Electronics Letters 27, no. 22 (1991): 2020. http://dx.doi.org/10.1049/el:19911251.

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18

Ke, Shao, Lu Bo, Xia Lingli, and Hong Zhiliang. "A high speed sampler for sub-sampling IR-UWB receiver." Journal of Semiconductors 31, no. 4 (2010): 045004. http://dx.doi.org/10.1088/1674-4926/31/4/045004.

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19

Pountourakis, I. E., and P. A. Baziana. "Markovian receiver collision analysis of high-speed multi-channel networks." Mathematical Methods in the Applied Sciences 29, no. 5 (2006): 575–93. http://dx.doi.org/10.1002/mma.701.

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20

Ning, Jie, Guanjun Gao, Zhang Jia Liang, He Peng, and Yonggang Guo. "Adaptive Receiver Control for Reliable High-Speed Underwater Wireless Optical Communication With Photomultiplier Tube Receiver." IEEE Photonics Journal 13, no. 4 (2021): 1–7. http://dx.doi.org/10.1109/jphot.2021.3089781.

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21

BINDU, MADDI. "Design and Implementation of High-Speed Universal Asynchronous Receiver and Transmitter (UART)." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–9. https://doi.org/10.55041/ijsrem40371.

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The Universal Asynchronous Receiver and Transmitter (UART) are described, which is essentially a serial data transfer protocol used in digital circuit applications. The UART transmitter architecture has a baud rate generator, a parity generator, a transmitter finite state machine (FSM), and a parallel in serial out (PISO) register. The UART receiver is composed of a baud rate generator, a negative edge detector, a parity checker, a receiver Finite State Machine (FSM), and a serial in parallel out (SIPO) register. The transmitter and the receiver have the same baud rate generator; therefore, th
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22

Sun, Da, Yue Gang Fu, Jing Yuan Duan, and An Cun Shi. "A Novel Receiver in Visible Light Communication Based on RGB LEDs." Applied Mechanics and Materials 543-547 (March 2014): 2283–87. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.2283.

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In this paper, we demonstrate a novel receiver in visible light communication system based on RGB LEDs. It contains three major parts the collimating lens, the spectro-device and the photodetector. The mixed RGB signal lights are captured, separated and received by the collimating lens the spectro-device and the photodetector respectively. Through the adjustment of the collimating lens, the receiver can receive enough light even if the distance between the signal light source and the receiver is changed. The receiver has the advantages of strong mobility and strong ability of receiving signal
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23

Fayadh, Rashid Ali, Mohd Fareq Abd Malek, Hilal Adnan Fadhil, and Norshafinash Saudin. "Performance Evaluation of Adaptive Indoor Matched Rake Receiver Using Multiple-Combining Techniques." Applied Mechanics and Materials 699 (November 2014): 921–30. http://dx.doi.org/10.4028/www.scientific.net/amm.699.921.

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This paper discusses the enhancement of the wireless rake receiver for high speed and short distance indoor ultra wideband (UWB) propagation with line-of sight (LOS) and non line-of sight (NLOS) channel models. The proposed matched rake receiver uses three main combining techniques, maximum ratio combining (MRC), equal gain combining (EGC), and selective combining (SC) to capture most of the energy of the multi-path components (MPCs). When the wireless communication systems work with high capacity and high speed in transmission and reception scenarios, there will be a serious challenge defined
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24

Kou, Zhengchang, and Michael L. Oelze. "Implementation of real-time high-speed ultrasound communications through tissue." Journal of the Acoustical Society of America 151, no. 4 (2022): A245. http://dx.doi.org/10.1121/10.0011208.

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In this work, we propose a novel implementation of both a transmitter and receiver with field programmable gate arrays (FPGAs) to achieve real-time continuous high-definition (HD) video transmission through tissue, which can enable HD and higher frame rate wireless capsule endoscopy. We used a Texas Instruments AFE58JD48EVM 16 channel analog front end (AFE) evaluation board as the receiver connected to a Xilinx ZCU106 Zynq Ultrascale MPSoC development board in which we implemented a digital down converter (DDC), OFDM demodulator, maximum ratio combiner and low-density parity-check (LDPC) decod
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25

Jiang, Lin, Lianshan Yan, Anlin Yi, et al. "Integrated Components and Solutions for High-Speed Short-Reach Data Transmission." Photonics 8, no. 3 (2021): 77. http://dx.doi.org/10.3390/photonics8030077.

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According to different transmission distances, application scenarios of a data center mainly include intra- and inter-data center optical interconnects. The intra-data center optical interconnect is considered as a few kilometers optical interconnect between servers and racks inside a data center, which accounts for nearly 80% of data traffic of a data center. The other one, inter-data center optical interconnect, is mainly applied in tens of kilometers data transmission among different data centers. Since data exchange in data centers generally occurs between many servers and racks, and a lot
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26

Chaudhary, Muhammad Waqas, and Andy Heinig. "High Speed Serial Interfaces in 2.5D Integrated Systems." International Symposium on Microelectronics 2016, no. 1 (2016): 000155–59. http://dx.doi.org/10.4071/isom-2016-wa21.

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Abstract High speed communication has been a topic of great interest in the last decade due to excessively high data rates required between chips especially pushed by the measurement equipment industry to support extremely high bandwidth data sampling. Serial communication is chosen to support these data rates which are pushing further and further into higher data rate regimes. It is important to understand how the 2.5D integration of chips on the interposer can support serial communication and what the designer can do to leverage the special features of interposer channel to achieve lower pow
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27

Li, Jiehui, Peng Zou, Xinming Ji, Xia Guo, and Nan Chi. "High-speed visible light communication utilizing monolithic integrated PIN array receiver." Optics Communications 494 (September 2021): 127027. http://dx.doi.org/10.1016/j.optcom.2021.127027.

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28

Jeon, Young-Il, Ki-Min Sung, Sang-Geun Hong, and In-Seok Na. "Design of High-speed Adaptive Band Selection RF Receiver for DRFM." Journal of the Institute of Electronics and Information Engineers 56, no. 8 (2019): 74–80. http://dx.doi.org/10.5573/ieie.2019.56.8.74.

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29

Lu, Mingzhi, Hyun-Chul Park, Abirami Sivananthan, et al. "Monolithic Integration of a High-Speed Widely Tunable Optical Coherent Receiver." IEEE Photonics Technology Letters 25, no. 11 (2013): 1077–80. http://dx.doi.org/10.1109/lpt.2013.2259474.

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30

Li, Bowen, Brandon Jiao, Chih-Hsun Chou, Romi Mayder, and Paul Franzon. "Self-Evolution Cascade Deep Learning Model for High-Speed Receiver Adaptation." IEEE Transactions on Components, Packaging and Manufacturing Technology 10, no. 6 (2020): 1043–53. http://dx.doi.org/10.1109/tcpmt.2020.2992186.

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31

Fischer, J. H., J. L. Sonntag, J. S. Lavranchuk, et al. "Line and receiver interface circuit for high-speed voice-band modems." IEEE Journal of Solid-State Circuits 22, no. 6 (1987): 982–89. http://dx.doi.org/10.1109/jssc.1987.1052846.

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32

Trommer, D., and G. Unterbörsch. "Monolithically integrated polarisation-insensitive high-speed balanced mixer receiver on InP." Electronics Letters 31, no. 5 (1995): 362–63. http://dx.doi.org/10.1049/el:19950267.

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33

Alic, N., G. C. Papen, S. Radic, and Y. Fainman. "Receiver structure trade-offs in equalized high-speed fiber-optic links." IEEE Photonics Technology Letters 18, no. 17 (2006): 1810–12. http://dx.doi.org/10.1109/lpt.2006.881147.

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34

Li, Junze, Suge Yue, Maoxin Chen, and Xiaojing Song. "Single Event Effect Characterization of High Speed Serial JESD204B Data Receiver." Journal of Physics: Conference Series 1345 (November 2019): 022016. http://dx.doi.org/10.1088/1742-6596/1345/2/022016.

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35

Rao, P. Vijaya Sankara, and Pradip Mandal. "A new current-mode receiver for high-speed electrical/optical link." AEU - International Journal of Electronics and Communications 65, no. 2 (2011): 107–16. http://dx.doi.org/10.1016/j.aeue.2010.01.018.

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36

Huang, Zhe-Yang, Chun-Chieh Chen, and Chung-Chih Hung. "Ultra-wideband wireless receiver front-end for high-speed indoor applications." Journal of Engineering 2014, no. 12 (2014): 626–33. http://dx.doi.org/10.1049/joe.2014.0189.

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37

Yano, H., G. Sasaki, M. Murata, and H. Hayashi. "An ultra-high-speed optoelectronic integrated receiver for fiber-optic communications." IEEE Transactions on Electron Devices 39, no. 10 (1992): 2254–59. http://dx.doi.org/10.1109/16.158796.

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38

Li, XianBo, Bin Li, and ZhaoHui Wu. "Compact low-power CMOS squarer for high-speed noncoherent UWB receiver." Electronics Letters 48, no. 19 (2012): 1237. http://dx.doi.org/10.1049/el.2012.2384.

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39

Sindgi, Anuapam, and Udigala Basavaraju Mahadevaswamy. "FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS." Bulletin of Electrical Engineering and Informatics 13, no. 2 (2024): 1069–79. http://dx.doi.org/10.11591/eei.v13i2.6543.

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Communication systems at millimeter-wave (mm-wave) frequencies with high propagation losses use radio frequency (RF) budget analysis. RF system gains and losses ensure the receiver can recover the broadcast signal. Modern communication systems use compressive sensing (CS) and discrete wavelet transform (DWT). Hardware implementation is hard. Fieldprogrammable gate arrays (FPGA) adaptability, configurability, and processing speed make them popular. More mm-wave transceivers use FPGAs and advanced signal processing. FPGA-based mm-wave transceivers use compressed sensing and dual-tree complex wav
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40

Rajan, Abhinav, and K. S. Reddy. "Estimation of convective heat losses from conical cavity receiver of solar parabolic dish collector under wind conditions and receiver orientations." E3S Web of Conferences 313 (2021): 11001. http://dx.doi.org/10.1051/e3sconf/202131311001.

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The parabolic dish collector is one of the recognized concentrated solar power systems based on point focusing, which provides high-temperature heat, high concentration ratio, and low heat loss. This system consists of a parabolic reflector and a cavity receiver situated in the focus line. In this work, the conical cavity receiver with an aperture diameter of 0.5 m is considered for a 100 m2 parabolic reflector having a focal to diameter ratio of 0.48. Due to the complexity of flow and temperature profile, the estimation of convective heat loss is a difficult task in a cavity receiver. More he
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41

Prof. Madhuri Zambre. "Automatic Vehicle Over speed Controlling System using Microcontroller Unit and ARCAD." International Journal of New Practices in Management and Engineering 5, no. 04 (2016): 01–05. http://dx.doi.org/10.17762/ijnpme.v5i04.47.

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The main purpose of this paper is to develop a system that avoid accidents because of vehicles with high speed. Also, authorizes the pedestrians and public to cross the highway road with no risk from vehicles which are moving with high speed. Generally, drivers of the vehicles with high speed drives in an uncontrollable manner even in speed limited areas without taking into consideration about the public. Even traffic policemen could not able to control them and attain good response from the high speed vehicle drivers. Also, we cannot monitor them to limit their speed at all times in those are
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42

Chen, Kai-Sheng, Yi-Chang Chen, and Long-Guang Liao. "Advancing High-Speed Transmissions over OCDMA Networks by Employing an Intelligently Structured Receiver for Noise Mitigation." Applied Sciences 8, no. 12 (2018): 2408. http://dx.doi.org/10.3390/app8122408.

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We propose an intelligently structured receiver to achieve high-speed transmissions over optical code-division multiple access (OCDMA) networks. Employing spectral-amplitude coding (SAC) reduces multiuser interference (MUI) in OCDMA, but the network bit-rate is limited by phase-induced intensity noise (PIIN) coming from the incoherency of light sources. To mitigate PIIN, the receiver performs interference estimations and regenerations through consecutive stages. The MUI is removed by subtracting the estimated interference term from the received multiplexed signals. For PIIN variance, it is bot
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43

FUKAISHI, MUNEO, KAZUYUKI NAKAMURA, and MICHIO YOTSUYANAGI. "HIGH-SPEED AND HIGH-DATA-BANDWIDTH TRANSMITTER AND RECEIVER FOR MULTI-CHANNEL SERIAL DATA COMMUNICATION WITH CMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 11, no. 01 (2001): 1–33. http://dx.doi.org/10.1142/s0129156401000770.

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This paper briefly reviews recent research on CMOS gigahertz-rate communication circuits and design innovations for overcoming device performance limitations. A multi-channel transmitter and receiver chip set operating at 5 Gb/s has been developed using 0.25-μm CMOS technology. To achieve high-speed operation, the chip set features: (1) a tree-type demultiplexer and frequency conversion architecture, (2) a self-aligning phase detector for clock and data recovery circuit, and (3) a fully pipelined 8-bit to 10-bit encoder. The features contributing to the achievement of high-data bandwidth for m
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44

Silva Valdecasa, Guillermo, Jose A. Altabas, Monika Kupska, Jesper Bevensee Jensen та Tom K. Johansen. "A 5–50 GHz SiGe BiCMOS Linear Transimpedance Amplifier with 68 dBΩ Differential Gain towards Highly Integrated Quasi-Coherent Receivers". Electronics 10, № 19 (2021): 2349. http://dx.doi.org/10.3390/electronics10192349.

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Quasi-coherent optical receivers have recently emerged targeting access networks, offering improved sensitivity and reach over direct-detection schemes at the expense of a higher receiver bandwidth. Higher levels of system integration together with sufficiently wideband front-end blocks, and in particular high-speed linear transimpedance amplifiers (TIAs), are currently demanded to reduce cost and scale up receiver data rates. In this article, we report on the design and testing of a linear TIA enabling high-speed quasi-coherent receivers. A shunt-feedback loaded common-base topology is adopte
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45

Wang, Ling, Bo Mo, and Ke Gao. "A New Design of Laser Pulse Receiver in the Automatic Control System." Applied Mechanics and Materials 496-500 (January 2014): 1434–37. http://dx.doi.org/10.4028/www.scientific.net/amm.496-500.1434.

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The existing problem of current laser pulse receiving system is that the laser pulses width is too narrow to be directly collected. And the consistency of the four signals acquisition is very strict. To deal with these problems, a new design of laser pulse receiver will be introduced in this article. This laser pulse receiving system includes the following structures: new high-speed laser pulse receiving hardware based on CPLD and Four-Quadrant Detectors, new peak-hold circuit of laser pulse, high-speed parallel ADC system, and processing data with fast interpolation algorithm in a Floating-Po
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46

Zhang, Geng, Mingche Lai, and Fangxu Lyu. "A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects." Electronics 11, no. 18 (2022): 2864. http://dx.doi.org/10.3390/electronics11182864.

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This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The receiver adopts forward clock (FCK) architecture of the high-density transmission standard, which consists of 16 high-speed data paths and a pair of low-speed differential clocks for 512 Gbps BW. To reduce the chip area and power consumption, a common minimal phase-locked loop (MINI-PLL) and data adjustment (CDA) circuit to replaces the clock data recovery circuit (CDR) in the traditional receiver. A delay-matching circuit is adopted to combat PVT variation and lane sk
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47

Wang, Wei, and Guangliang Ren. "Multiuser Receiver Scheme with SIC for PUCCH in High Speed Train Environment." Communications and Network 05, no. 03 (2013): 308–11. http://dx.doi.org/10.4236/cn.2013.53b2057.

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48

Deng, Jun, Lin Tao Liu, Yu Jing Li, Xiao Zong Huang, Xu Huang, and Lun Cai Liu. "Design of a SoC With High-Speed DDC for Software Radio Receiver." Advanced Materials Research 605-607 (December 2012): 1875–79. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1875.

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This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the ma
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49

Basar, Md Rubel, Mohd Fareq Bin Abd Malek, Khairudi Mohd Juni, Mohd Shaharom Idris, and Mohd Iskandar Mohd Saleh. "HIGH-SPEED, SIMPLIFIED DESIGN OF AN IMAGE RECEIVER FOR WIRELESS CAPSULE ENDOSCOPY." Progress In Electromagnetics Research B 53 (2013): 223–39. http://dx.doi.org/10.2528/pierb13052012.

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50

Sun, Weiwei, Laura Vertatschitsch, and John D. Sahr. "Development design and demonstration of very high‐speed multi‐antenna digital receiver." IET Radar, Sonar & Navigation 12, no. 5 (2018): 523–29. http://dx.doi.org/10.1049/iet-rsn.2017.0383.

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