Relevant bibliographies by topics / High voltage charge-pump

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'High voltage charge-pump'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 February 2022

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Journal articles on the topic "High voltage charge-pump"

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Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Tin Fang Zheng, and Chie Nan Lai. "High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique." Applied Mechanics and Materials 145 (December 2011): 557–61. http://dx.doi.org/10.4028/www.scientific.net/amm.145.557.

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This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.
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Toft, Jakob K., and Ivan H. H. Jorgensen. "Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications." Elektronika ir Elektrotechnika 27, no. 2 (April 29, 2021): 31–39. http://dx.doi.org/10.5755/j02.eie.28827.

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This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.
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Chen, Yung Chin. "High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique." Applied Mechanics and Materials 764-765 (May 2015): 506–10. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.506.

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This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.
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Cao, Yi Jiang, Hao De, Jia Mu Cao, Xing Hua Tang, and Qian Cui. "High-Efficiency Charge Pump LED Driver Circuit Design." Applied Mechanics and Materials 389 (August 2013): 612–17. http://dx.doi.org/10.4028/www.scientific.net/amm.389.612.

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In this paper, Using CSMC 0.5μm CMOS process to design each sub-module, the circuit simulation, and adjustment and validation of parameters have been carried out by simulation tools. The low static power and high conversion efficiency charge pump LED driver circuit has been designed. The circuits nucleus module is adaptive charge pump (1x/1.5x/2x charge pump), to converse a wider range of input voltage to a constant output voltage with high efficiency. This circuit only needs some external capacitors, and dont need inductor. So it reduces EMI electromagnetic interference and application cost, etc.
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Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Kai Wei Chang, and Chie Nan Lai. "High-Efficiency CTS Charge Pump Using Three-Level Addressing Method." Applied Mechanics and Materials 145 (December 2011): 562–66. http://dx.doi.org/10.4028/www.scientific.net/amm.145.562.

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This paper proposes a new addressing method for high-efficiency switching-capacitor DC-DC voltage converter based on combination of CTS (charge-transfer-switch) charge pump and cross-coupled output stage is proposed in order to get a high output power and pump-efficiency. By using three level addressing methods, it can increase both of pump-efficiency and power-efficiency. The proposed three level addressing mixed-structure charge pump can operate at as high as 1MHz switching-frequency on the 0.1 μF pump-capacitors. Simulation by using HSPICE level 3 model shows that our work can convert the input low DC-voltage (Vin=1.5V) up near to 11.26 times of it (VOUT=16.9V), so that more output power can be generated with a little power loss. The newly proposed addressing method for DC-DC charge pump circuit is suitable for various low-voltage applications.
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Zhao, Jun, Kyung Ki Kim, and Yong-Bin Kim. "Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure." Journal of Integrated Circuits and Systems 10, no. 3 (December 28, 2015): 158–65. http://dx.doi.org/10.29292/jics.v10i3.418.

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In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.
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Moisiadis, Y., I. Bouras, and A. Arapoyanni. "Charge Pump Circuits for Low-voltage Applications." VLSI Design 15, no. 1 (January 1, 2002): 477–83. http://dx.doi.org/10.1080/1065514021000012084.

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In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.
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LIN, HONGCHIN, NAI-HSIEN CHEN, and JAINHAO LU. "DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES." Journal of Circuits, Systems and Computers 11, no. 04 (August 2002): 393–403. http://dx.doi.org/10.1142/s0218126602000537.

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A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.
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Anil, Aamna. "A High Efficiency Charge Pump for Low Voltage Devices." International Journal of VLSI Design & Communication Systems 3, no. 3 (June 30, 2012): 43–56. http://dx.doi.org/10.5121/vlsic.2012.3305.

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Lee, Choongkeun, Taegun Yim, and Hongil Yoon. "A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM." Electronics 9, no. 11 (October 26, 2020): 1769. http://dx.doi.org/10.3390/electronics9111769.

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As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.
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Dissertations / Theses on the topic "High voltage charge-pump"

1

Huang, Weixing. "Design of a Radial Mode Piezoelectric Transformer for a Charge Pump Electronic Ballast with High Power Factor and Zero Voltage Switching." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31818.

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In a conventional electronic ballast for a fluorescent lamp, inductor-capacitor-transformer tank circuit is used. A Piezoelectric Transformer (PT) can potentially be used to replace such a tank circuit to save space and cost. In the past, ballast design using a PT requires selecting a PT from available samples which are normally not matched to specific application and therefore resulting in poor performance. In this thesis, a design procedure was proposed for designing a PT tailored for a 120-V 32-W electronic ballast with high power factor, high efficiency and Zero-Voltage-Switching (ZVS) of the inverter transistors that drive the lamp. This involves selection of PT materials, determination of geometries and the number of physical layers of the PT. A radial mode piezoelectric transformer prototype based on this design process was fabricated by Face Electronics Inc. and was tested experimentally, the results showed that the ballast using this custom-made PT achieved high power factor, Zero-Voltage-Switching and a 83% overall efficiency.
Master of Science
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LiuPo-Chin and 劉柏志. "High Voltage Charge Pump Circuits of Design and Analysis." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/98466176971323926270.

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碩士
崑山科技大學
電子工程研究所
95
There are four new charge pump circuits were presented in thesis. These four new circuits were base on the voltage-doubler clock generator. The first one was constituted by connecting many stages of voltage-doubler clock generator and which was called VDCP-1. The second charge pump circuit, VDCP-2, was a modification of VDCP-1. A complement-paralleled pMOSFET was used to replace the nMOSFET of the output. For the other two charge pump circuits, the multi-stages voltage doubler was used to be clock generator, which providing clock voltage to transfer MOS diode. The two circuits showed little difference in connection with each other, and call MVDCP-1 and MVDCP-2, respectively. The above four circuits were simulated by HSpice in TSMC 0.35μm process. They all showed batter results than conventional charge pump circuit. The Layout design of VDCP-1 was also realized through TSMC 0.35μm Mixed-Signal process. In the chip, the area is 1.0404 × 1 (mm2) and the power consumption of the circuit is 5.84mW.
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Lai, Sheng Yeh, and 賴昇業. "Design of High Performance-Low Voltage Charge Pump Circuits and Applications." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/99571379281874004460.

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碩士
國立中正大學
電機工程研究所
88
The work analyzes advantages and disadvantages of traditional Charge Pump at first, in which NCP2 and SP7 have improved the disadvantages of DICKSON. However, we know that, by way of analysis, there are still some aspects needing improving. The thesis introduces the structure and design skills for new High Performance & Low Supply Charge Pump, We propose High Performance Charge Pump and High Performance Charge Pump for Low Supply. By simulation, it is found out that the High Performance Charge Pump introduced in the thesis has the best performance among all systems when over 2V, and High Performance Charge Pump for Low Supply has the best performance when under 2V. The penalty for increasing area of these two new circuits is small, so that they are suitable for practical applications. In addition, the thesis introduces the low-supply circuit design for Charge Pump with Variable Threshold Voltage Scheme. The scheme skillfully changes substrate bias voltage to promote threshold voltage and, furthermore, lower leakage current. Besides, the thesis applies it to Personal Access Communication System to lower leakage current and satisfy the need for low power design.
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Chang, Chih-Cheng, and 張智程. "A Regulated High Voltage Charge Pump Circuit for White LED Driver." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/38153716231078403645.

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碩士
國立雲林科技大學
電子與光電工程研究所碩士班
102
This study presents a new regulated charge pump circuit for driving multiple white LEDs. Most of the LED driver circuits use inductors for energy storage, but inductors have some disadvantages, including large size, high cost and electromagnetic interference. Therefore, a charge pump circuit that only uses capacitors for energy storage is applied in study. The charge pump circuit has many advantages, surch as small size, low cost and no electromagnetic interference, so it can totally replace the LED driver with inductors. However, most of the traditional charge pumps has no regulatory function, which made the output voltage unstable and output current has not precise enough. This study uses feedback circuit to control the charging voltage, and it also uses a precise current source circuit and a P-type transistor as charge transfer switch, which can enhance the accuracy of output voltage and the stability of output current. The feedback circuit could hold the output voltage with three digital code under four potentials, which makes the charge pump as a LED driver has more advantages. The chip was patronized by National Chip Implementation Center(CIC), and used Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS High Voltage Mixed Signal General Purpose IIA Based BCD 2.5/5/7/12/20/24/40/45/60V process to implement the High voltage charge pump circuit, which can converse the 5V input voltage to 30V, 24V, 18V and 12V output voltage under the 20mA output current, and reach steady-state in 1.45ms. The efficiency of high voltage charge pump circuit is 71% and the die area of the proposed chip is 1.9×1.4"m" "m" ^"2" . In circuit simulation, we apply for HSPICE, and the simulation results is our expected.
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CHENG, CHUN-YUAN, and 鄭竣元. "The Research on High-Efficiency Low-ripple-voltage CMOS Regulated Charge Pump." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/85874808790585503910.

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CHU, YEN-JUI, and 朱彥睿. "The design of CMOS high-efficiency low-ripple-voltage regulated charge pump." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/64223771565188913678.

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Lu, Wan-Ying, and 呂婉熒. "Low Supply Noise High Output Current Voltage Charge Pump for Embedded Non-Volatile Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/58504327885945151254.

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碩士
國立清華大學
產業研發碩士積體電路設計專班
98
Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices. Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.
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CHANG, CHIA-YUAN CHANG, and 張嘉元. "The Design of CMOS High-Efficiency Low-Ripple-Voltage Highly Integrated Regulated Charge Pump." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8ur667.

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碩士
國立雲林科技大學
電子工程系
106
The thesis proposed a design of CMOS high-efficiency low-ripple-voltage highly integrated regulated charge pump. The charge pump exploits an automatic pumping control scheme to provide small output ripple voltage. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. A regulated charge pump circuit is designed in a TSMC 3.3-V 0.18-μm CMOS process. The circuit provides 30-mA load current and generates a regulated 4.53-V to 5.62-V output voltage from a supply voltage of 3.3-V with a flying capacitor of 330-nF.The circuit area is 1.26-mm2 and the simulated output ripple voltage is less than 2.5-mV with the variable load resistor and a 2-μF load capacitor. The simulated power efficiency is greater than 74% when the load current is varied from 1-mA to 30-mA.
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Wu, Geng-yi, and 吳耿毅. "A Self-Regulated Charge Pump with High Drive Current and Small Output Ripple Voltage." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/71309610072403955378.

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碩士
國立雲林科技大學
電子與資訊工程研究所
95
A self-regulated charge pump circuit is proposed. The charge pump exploits an automatic pumping control scheme to provide small output ripple voltage. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an improved automatic pumping frequency control scheme. We utilized a Range-programmable Voltage-controlled Oscillator which has four different frequency band outputs depended on load current value. The output frequency of the VCO varies from 400KHz to 10MHz. The improved automatic pumping frequency control scheme generates high pumping frequency when the system provides the great load current, and also reduce the output ripple voltage. The improved charge pump is designed in a TSMC 0.18 CMOS process. The fabricated circuit occupies an area of 734.54um*794.805um, operating at 1.8V power supply with a flying capacitor of 330nF. For the variable load resistor and the load capacitor of 2μF. The circuit offers load current from 1mA to 30mA. The improved charge pump delivers 2.05-V output voltage, and the output ripple voltage is less than 1mV, and the power efficiency is 51.5%, while providing 30mA of load current.
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Veale, Gerhardus Ignatius Potgieter. "Low phase noise 2 GHz Fractional-N CMOS synthesizer IC." Diss., 2010. http://hdl.handle.net/2263/27921.

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Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2.
Dissertation (MEng)--University of Pretoria, 2010.
Electrical, Electronic and Computer Engineering
unrestricted
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Book chapters on the topic "High voltage charge-pump"

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Tanzawa, Toru. "Charge Pump Circuit Theory." In On-chip High-Voltage Generator Design, 15–95. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-3849-6_2.

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Tanzawa, Toru. "Charge Pump State of the Art." In On-chip High-Voltage Generator Design, 97–114. New York, NY: Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4614-3849-6_3.

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Arul Murugan, C., B. Banuselvasaraswathy, and K. Gayathree. "High-Voltage Gain CMOS Charge Pump at Subthreshold Operation Regime for Low Power Applications." In Lecture Notes in Networks and Systems, 417–26. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-3765-9_44.

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Merchant, Marty. "High voltage inverting charge pump produces low noise positive and negative supplies." In Analog Circuit Design, 343–44. Elsevier, 2015. http://dx.doi.org/10.1016/b978-0-12-800001-4.00163-0.

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Conference papers on the topic "High voltage charge-pump"

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Taufik, Mohammad, Taufik Taufik, Afarulrazi Abubakar, and Wahyu Utomo. "Multiple Charge Pump for High Output Voltage." In Software Engineering and Applications/ 831: Advances in Power and Energy Systems. Calgary,AB,Canada: ACTAPRESS, 2015. http://dx.doi.org/10.2316/p.2015.831-009.

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Li, Bo, Lichao Hao, and Dengyun Lei. "A High Performance Parallel Negative Voltage Charge Pump." In 2020 IEEE 3rd International Conference on Electronics Technology (ICET). IEEE, 2020. http://dx.doi.org/10.1109/icet49382.2020.9119609.

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Yim, Taegun, Seungjin Lee, Choongkeun Lee, and Hongil Yoon. "A Low-Voltage Charge Pump with High Pumping Efficiency." In TENCON 2018 - 2018 IEEE Region 10 Conference. IEEE, 2018. http://dx.doi.org/10.1109/tencon.2018.8650247.

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Huang, Wen Chang, Jin Chang Cheng, and Po Chih Liou. "A Charge Pump Circuit --- Cascading High-Voltage Clock Generator." In 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008). IEEE, 2008. http://dx.doi.org/10.1109/delta.2008.94.

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Zhang, Liang, Xu Cheng, Tong Xiaodong, and Xianjin Deng. "High voltage charge pump circuit using vertical parallel plate capacitors." In 2017 IEEE 12th International Conference on ASIC (ASICON). IEEE, 2017. http://dx.doi.org/10.1109/asicon.2017.8252587.

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Xueqiang Wang, Dong Wu, Fengying Qiao, Peng Zhu, Kan Li, Liyang Pan, and Runde Zhou. "A high efficiency CMOS charge pump for low voltage operation." In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351437.

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Xia, Tian, and Stephen Wyatt. "High Output Resistance and Wide Swing Voltage Charge Pump Circuit." In 2008 9th International Symposium of Quality of Electronic Design (ISQED). IEEE, 2008. http://dx.doi.org/10.1109/isqed.2008.4479709.

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Yu, Jun, Kevin Tshun Chuan Chai, Yat Hei Lam, and Muthukumaraswamy Annamalai Arasu. "Half-bridge driver with charge pump based high-side voltage regulator." In 2016 International Symposium on Integrated Circuits (ISIC). IEEE, 2016. http://dx.doi.org/10.1109/isicir.2016.7829724.

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Yan, Na, and Hao Min. "A High Efficiency ALL-PMOS Charge Pump for Low-Voltage Operations." In 2005 IEEE Asian Solid-State Circuits Conference. IEEE, 2005. http://dx.doi.org/10.1109/asscc.2005.251740.

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Qiang, Fan, Fu Xiansong, Niu Pingjuan, Yang Guanghua, and Gao Tiecheng. "A novel low voltage and high speed CMOS charge pump circuit." In 2010 2nd International Conference on Signal Processing Systems (ICSPS). IEEE, 2010. http://dx.doi.org/10.1109/icsps.2010.5555828.

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