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Journal articles on the topic 'High voltage charge-pump'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 February 2022

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1

Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Tin Fang Zheng, and Chie Nan Lai. "High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique." Applied Mechanics and Materials 145 (December 2011): 557–61. http://dx.doi.org/10.4028/www.scientific.net/amm.145.557.

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This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.

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2

Toft, Jakob K., and Ivan H. H. Jorgensen. "Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications." Elektronika ir Elektrotechnika 27, no. 2 (April 29, 2021): 31–39. http://dx.doi.org/10.5755/j02.eie.28827.

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This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

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3

Chen, Yung Chin. "High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique." Applied Mechanics and Materials 764-765 (May 2015): 506–10. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.506.

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This paper proposed an improved bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump in order to get a higher pumping efficiency. It is not only avoid the threshold voltage drop in conventional Dickson charge pump circuits but enable them to generate a higher output voltage. Simulation by HSPICE shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.76 times of it (VOUT=7.14V), the pump efficiency can reaches as high as 95.2%.

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4

Cao, Yi Jiang, Hao De, Jia Mu Cao, Xing Hua Tang, and Qian Cui. "High-Efficiency Charge Pump LED Driver Circuit Design." Applied Mechanics and Materials 389 (August 2013): 612–17. http://dx.doi.org/10.4028/www.scientific.net/amm.389.612.

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In this paper, Using CSMC 0.5μm CMOS process to design each sub-module, the circuit simulation, and adjustment and validation of parameters have been carried out by simulation tools. The low static power and high conversion efficiency charge pump LED driver circuit has been designed. The circuits nucleus module is adaptive charge pump (1x/1.5x/2x charge pump), to converse a wider range of input voltage to a constant output voltage with high efficiency. This circuit only needs some external capacitors, and dont need inductor. So it reduces EMI electromagnetic interference and application cost, etc.

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5

Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Kai Wei Chang, and Chie Nan Lai. "High-Efficiency CTS Charge Pump Using Three-Level Addressing Method." Applied Mechanics and Materials 145 (December 2011): 562–66. http://dx.doi.org/10.4028/www.scientific.net/amm.145.562.

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This paper proposes a new addressing method for high-efficiency switching-capacitor DC-DC voltage converter based on combination of CTS (charge-transfer-switch) charge pump and cross-coupled output stage is proposed in order to get a high output power and pump-efficiency. By using three level addressing methods, it can increase both of pump-efficiency and power-efficiency. The proposed three level addressing mixed-structure charge pump can operate at as high as 1MHz switching-frequency on the 0.1 μF pump-capacitors. Simulation by using HSPICE level 3 model shows that our work can convert the input low DC-voltage (Vin=1.5V) up near to 11.26 times of it (VOUT=16.9V), so that more output power can be generated with a little power loss. The newly proposed addressing method for DC-DC charge pump circuit is suitable for various low-voltage applications.

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6

Zhao, Jun, Kyung Ki Kim, and Yong-Bin Kim. "Negative High Voltage DC-DC Converter Using a New Cross-Coupled Structure." Journal of Integrated Circuits and Systems 10, no. 3 (December 28, 2015): 158–65. http://dx.doi.org/10.29292/jics.v10i3.418.

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In this paper, a negative high voltage DC-DC converter using a new cross-coupled charge pump structure has been proposed, which can solve the shoot-through current problem of the conventional charge pump by using a four clock phase scheme. Also, by switching the power supply to each stage based on the supply voltage, a variable voltage gain can be obtained. A complete analysis of the interaction between the power efficiency, area, and frequency have been presented. The proposed negative charge pump is designed to deliver 40μA with a widesupply range from 2.5V to 5.5V using 0.18μm high voltage LDMOS technology.

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7

Moisiadis, Y., I. Bouras, and A. Arapoyanni. "Charge Pump Circuits for Low-voltage Applications." VLSI Design 15, no. 1 (January 1, 2002): 477–83. http://dx.doi.org/10.1080/1065514021000012084.

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In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

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8

LIN, HONGCHIN, NAI-HSIEN CHEN, and JAINHAO LU. "DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES." Journal of Circuits, Systems and Computers 11, no. 04 (August 2002): 393–403. http://dx.doi.org/10.1142/s0218126602000537.

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A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.

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9

Anil, Aamna. "A High Efficiency Charge Pump for Low Voltage Devices." International Journal of VLSI Design & Communication Systems 3, no. 3 (June 30, 2012): 43–56. http://dx.doi.org/10.5121/vlsic.2012.3305.

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10

Lee, Choongkeun, Taegun Yim, and Hongil Yoon. "A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM." Electronics 9, no. 11 (October 26, 2020): 1769. http://dx.doi.org/10.3390/electronics9111769.

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As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

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11

LIN, CHANGLONG, XINZHUO SUN, SHILIANG MA, XIN LU, KE LIANG, and GUOFENG LI. "ULTRA-LOW-VOLTAGE GAIN-ENHANCED FOUR-PHASE CHARGE PUMP WITHOUT BODY EFFECT." Journal of Circuits, Systems and Computers 23, no. 07 (June 2, 2014): 1450104. http://dx.doi.org/10.1142/s0218126614501047.

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In this paper, an ultra-low-voltage gain-enhanced four-phase charge pump is proposed. The proposed charge pump is designed in 0.18 μm 1.8 V standard CMOS process with high voltage boosting efficiency when the supply voltage is between 0.5 V and 1.8 V. Moreover, it eliminates the body effect by means of adding two auxiliary substrate switching PMOS transistor. The simulation results show that the proposed charge pump has higher efficiency than the other two low voltage charge pumps when the resistive load is 100 M ohm and the supply voltage is between 0.5 and 1.8 V. A test chip has been realized in a 0.18 μm 1.8 V standard CMOS process. The test results show perfect performance when the supply voltage is between 0.7 and 1.8 V. The proposed charge pump is quite suitable for low power applications.

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12

Hasan, T., T. Lehmann, and C. Y. Kwok. "On-chip high voltage charge pump in standard low voltage CMOS process." Electronics Letters 41, no. 15 (2005): 840. http://dx.doi.org/10.1049/el:20051488.

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13

Peng, Hui, Pieter Bauwens, Herbert De Pauw, and Jan Doutreloigne. "A high-efficiency and compact charge pump with charge recycling scheme and finger boost capacitor." MATEC Web of Conferences 292 (2019): 01020. http://dx.doi.org/10.1051/matecconf/201929201020.

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A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. The proposed four-stage charge pump with finger capacitor can achieve 14.2 V output voltage from a 3 V power supply. The finger capacitor can increase the power efficiency of the charge pump to 60.5% and save chip area as well.

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14

Li, Jiayang. "Applications of Wireless Communication in a New Dual Branch CTS Charge Pump Based on Employing Clock Matched Technology." Wireless Communications and Mobile Computing 2021 (August 14, 2021): 1–9. http://dx.doi.org/10.1155/2021/4014795.

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With the increase in communication requirements, new communication technologies and implementation methods have developed rapidly. The rise of emerging markets such as the Internet of Things, smart homes, smart cities, and wearables has promoted the development of wireless communication integrated circuits in the direction of monolithic, low energy consumption, and high energy efficiency. This paper proposes a new dual branch charge pump based on CTS charge pump with enhanced current drive capability and undesired charge transfer completely eliminated. Clock matched technology is proposed to completely eliminate undesired charge transfer caused by delay turn on and off of the auxiliary transistors in the traditional CTS charge pump. The current drive capability is enhanced by employing NMOS transistors with 2Vdd gate drive voltage, while traditional dual branch CTS charge pumps are based on PMOS with 1Vdd gate drive voltage. The output voltage ripple is also reduced resulting from a dual branch structure. Simulation results of output voltage gain and power efficiency for the proposed charge pump and other traditional charge pumps are provided. Comparisons are made to show the improvement of the proposed charge pump compared with other traditional charge pumps.

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15

Woong Park, Jung, Munkhsuld Gendensuren, Ho-Yong Choi, and Nam-soo Kim. "Integrated high voltage boost converter with LC filter and charge pump." Microelectronics International 31, no. 1 (December 20, 2013): 54–60. http://dx.doi.org/10.1108/mi-05-2013-0023.

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Purpose – The paper aims to design of dual-mode boost converter with integrated low-voltage control circuit is introduced in this paper. The paper aims to discuss these issues. Design/methodology/approach – The converter is operated either with LC filter or with charge pump circuit by the switch control. The control stage with error amplifier, comparator, and oscillator is designed with the supply voltage of 3.3 V and the operating frequency of 5.5 MHz. The compensator circuit exploits a pole compensation for a stable operation. Findings – The simulation test in 0.35 μm CMOS process shows that the charge pump regulator and DC-DC boost converter are accurately controlled with the variation of number of stages and duty ratio. The output-voltage is obtained to be 6-15 V within the ripple ratio of 5 percent. Maximum power consumption is about 0.65 W. Originality/value – This dual-mode is useful in the converter with a wide load-current variation. The advantage of the dual-mode converter is that it can be used in either high or low load current with a simple switch control. Furthermore, in charge pump regulator, there is no degradation of output voltage because of the feedback control circuit.

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16

Cabrini, A., A. Fantini, and G. Torelli. "High-efficiency regulator for on-chip charge pump voltage elevators." Electronics Letters 42, no. 17 (2006): 972. http://dx.doi.org/10.1049/el:20061165.

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17

Yan, N., and H. Min. "High efficiency all-PMOS charge pump for low-voltage operations." Electronics Letters 42, no. 5 (2006): 277. http://dx.doi.org/10.1049/el:20063662.

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18

Li, Xiang, Rui Li, Chunge Ju, Bo Hou, Qi Wei, Bin Zhou, Zhiyong Chen, and Rong Zhang. "A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes." Sensors 19, no. 19 (September 25, 2019): 4149. http://dx.doi.org/10.3390/s19194149.

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Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

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19

P. Nithin and Dr. R. Rajeswari. "High Gain DC-DC Converter Integrating Dickson Charge Pump with Coupled Inductor Technique." International Journal for Modern Trends in Science and Technology 7, no. 6 (September 9, 2021): 272–77. http://dx.doi.org/10.46501/ijmtst0706046.

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In this paper, a novel high voltage gain DC-DC converter based on coupled inductor and voltage multiplier technique is proposed. The benefits of the proposed converter are ultra-high voltage gain, low voltage stress across the power switch and very low input current ripple by employing a low current ripple structure (LCR) at the input side. A low on state resistance (RDS(on)) of the power switch can be employed since the voltage stress is a maximum of 25% of the output voltage and the conduction losses of the switch is also reduced. Design of a 1.9kW, 48V at the low voltage side and 430V at the high voltage side is done and verified by simulation. Simulation results show an efficiency of over 93% when operating in continuous conduction mode (CCM).

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20

Cheng, Li-Ye, and Xin-Quan Lai. "A Stable Mode-Selectable Oscillator with Variable Duty Cycle and High-Efficiency." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550132. http://dx.doi.org/10.1142/s0218126615501327.

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A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V IN ) in all modes with low EMI.

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21

Ballo, A., A. D. Grasso, and G. Palumbo. "A High-Performance Charge Pump Topology for Very-Low-Voltage Applications." IEEE Transactions on Circuits and Systems II: Express Briefs 67, no. 7 (July 2020): 1304–8. http://dx.doi.org/10.1109/tcsii.2019.2932471.

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22

LEE, D. H., D. KIM, H. J. SONG, and K. S. MIN. "A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage." IEICE Transactions on Electronics E91-C, no. 2 (February 1, 2008): 228–31. http://dx.doi.org/10.1093/ietele/e91-c.2.228.

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23

Abaravicius, Bartas, Sandy Cochran, and Srinjoy Mitra. "High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area." IEEE Access 9 (2021): 94386–97. http://dx.doi.org/10.1109/access.2021.3091808.

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24

Rahman, Labonnah Farzana, Mohammad Marufuzzaman, Lubna Alam, and Mazlin Bin Mokhtar. "Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications." Electronics 10, no. 6 (March 13, 2021): 676. http://dx.doi.org/10.3390/electronics10060676.

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Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

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25

D S, Rajeshwari, P. V Rao, and Ramesh Karmungi. "10Ghz Charge Pump PLL for Low Jitter Applica-tions." International Journal of Engineering & Technology 7, no. 2.12 (April 3, 2018): 348. http://dx.doi.org/10.14419/ijet.v7i2.12.11349.

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This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files

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26

Ker, Ming-Dou, and Shih-Lun Chen. "Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 1 (January 2007): 47–51. http://dx.doi.org/10.1109/tcsii.2006.882854.

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27

Baddipadiga, Bhanu Prashant, and Mehdi Ferdowsi. "A high-voltage-gain dc-dc converter based on modified dickson charge pump voltage multiplier." IEEE Transactions on Power Electronics 32, no. 10 (October 2017): 7707–15. http://dx.doi.org/10.1109/tpel.2016.2594016.

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28

Metange, P. N., and K. B. Khanchandani. "Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications." Indonesian Journal of Electrical Engineering and Computer Science 4, no. 2 (November 1, 2016): 397. http://dx.doi.org/10.11591/ijeecs.v4.i2.pp397-405.

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<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

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29

Chung, In-Young, and Jongshin Shin. "New charge pump circuits for high output voltage and large current drivability." IEICE Electronics Express 6, no. 12 (2009): 800–805. http://dx.doi.org/10.1587/elex.6.800.

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30

Xie, Yu, Shengming Huang, Yuming Xue, and Quanzhen Duan. "A low-voltage with high pumping efficiency charge pump for flash memory." Journal of Physics: Conference Series 1550 (May 2020): 052027. http://dx.doi.org/10.1088/1742-6596/1550/5/052027.

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31

Zhang, Liang, Xu Cheng, and Xianjin Deng. "A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency." Analog Integrated Circuits and Signal Processing 101, no. 3 (September 5, 2019): 601–9. http://dx.doi.org/10.1007/s10470-019-01531-w.

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32

Abdi, Alfian, Hyung Seok Kim, and Hyouk-Kyu Cha. "A High-Voltage Generation Charge-Pump IC Using Input Voltage Modulated Regulation for Neural Implant Devices." IEEE Transactions on Circuits and Systems II: Express Briefs 66, no. 3 (March 2019): 342–46. http://dx.doi.org/10.1109/tcsii.2018.2852360.

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33

Yu, Cao, Min Su Kim, Hyung Chul Kim, and Youn Goo Yang. "A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application." Advanced Materials Research 457-458 (January 2012): 1178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1178.

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A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

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34

Rakowski, R. F. "Charge movement by the Na/K pump in Xenopus oocytes." Journal of General Physiology 101, no. 1 (January 1, 1993): 117–44. http://dx.doi.org/10.1085/jgp.101.1.117.

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Pre-steady-state transient currents (1986. Nakao, M., and D. C. Gadsby. Nature [Lond.]. 323:628-630) mediated by the Na/K pump were measured under conditions for Na/Na exchange (K-free solution) in voltage-clamped Xenopus oocytes. Signal-averaged (eight times) current records obtained in response to voltage clamp steps over the range -160 to +60 mV after the addition of 100 microM dihydroouabain (DHO) or removal of external Na (control) were subtracted from test records obtained before the solution change. A slow component of DHO- or Na-sensitive difference current was consistently observed and its properties were analyzed. The quantity of charge moved was well described as a Boltzmann function of membrane potential with an apparent valence of 1.0. The relaxation rate of the current was fit by the sum of an exponentially voltage-dependent reverse rate coefficient plus a voltage-independent forward rate constant. The quantity of charge moved at the on and off of each voltage pulse was approximately equal except at extreme negative values of membrane potential where the on charge tended to be less than the off. The midpoint voltage of the charge distribution function (Vq) was shifted by -24.8 +/- 1.7 mV by changing the external [Na] in the test condition from 90 to 45 mM and by +14.7 +/- 1.7 mV by changing the test [Na] from 90 to 120 mM. A pseudo three-state model of charge translocation is discussed in which Na+ is bound and occluded at the internal face of the enzyme and is released into an external-facing high field access channel (ion well). The model predicts a shift of the charge distribution function to more hyperpolarized potentials as extracellular [Na] is lowered; however, several features of the data are not predicted by the model.

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35

Saiz-Vela, A., P. Miribel-Catala, J. Colomer, M. Puig-Vidal, and J. Samitier. "Charge pump design for high-voltage biasing applications in piezoelectric-based miniaturized robots." Analog Integrated Circuits and Signal Processing 59, no. 2 (December 9, 2008): 169–84. http://dx.doi.org/10.1007/s10470-008-9255-9.

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36

Abdi, Alfian, and Hyouk-Kyu Cha. "A regulated multiple-output high-voltage charge pump IC for implantable neural stimulators." Microelectronics Journal 92 (October 2019): 104617. http://dx.doi.org/10.1016/j.mejo.2019.104617.

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37

Tanguay, L. F., M. Sawan, and Y. Savaria. "A very-high output impedance charge pump for low-voltage low-power PLLs." Microelectronics Journal 40, no. 6 (June 2009): 1026–31. http://dx.doi.org/10.1016/j.mejo.2009.03.001.

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38

Koketsu, Kazuma, and Toru Tanzawa. "Design of a Charge Pump Circuit and System with Input Impedance Modulation for a Flexible-Type Thermoelectric Generator with High-Output Impedance." Electronics 10, no. 10 (May 19, 2021): 1212. http://dx.doi.org/10.3390/electronics10101212.

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This paper describes a charge pump system for a flexible thermoelectric generator (TEG). Even though the TEG has high-output impedance, the system controls the input voltage to keep it higher than the minimum operating voltage by modulating the input impedance of the charge pump using two-phase operation with low- and high-input impedance modes. The average input impedance can be matched with the output impedance of the TEG. How the system can be designed is also described in detail. A design demonstration was performed for the TEG with 400 Ω. The fabricated system was also measured with a flexible-type TEG based on carbon nanotubes. Even with an output impedance of 1.4 kΩ, the system converted thermal energy into electric power of 30 μW at 2.5 V to the following sensor ICs.

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39

Deng, Hai, and Guoqiang Li. "A High-Efficiency Low-Power Chip-Based CMOS Liquid Crystal Driver for Tunable Electro-Optic Eyewear." Electronics 8, no. 1 (December 22, 2018): 14. http://dx.doi.org/10.3390/electronics8010014.

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A high-efficiency low-power chip-based liquid crystal (LC) driver has been successfully designed and implemented for adaptive electro-optic eyewear including tunable vision correction devices (eyeglass, contact lens, intraocular lens, occluder, and prism), phoropter, iris, head-mounted display, and 3D imaging. The driver can generate a 1 kHz bipolar square wave with magnitude tunable from 0 V to 15 V to change the lens focus adaptively. The LC driver output magnitude is controlled by a reference DC voltage that is manually tunable between 0 and 3 V. A multi-mode 1×/2×/3×/4×/5× charge pump is developed for DC-DC conversion to expand the output range with a fast-sink function implemented to regulate the charge pump output. In addition, a new four-phase H-bridge driving scheme is employed to improve the DC/AC inverter efficiency. The LC driver has been successfully implemented and tested as an IC chip (8.6 mm × 8.6 mm) using AMS 0.18 μm High-Voltage CMOS technology.

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40

Ma, Yanzhao, Yinghui Zou, Shengbing Zhang, and Xiaoya Fan. "A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting." Journal of Circuits, Systems and Computers 26, no. 12 (August 2017): 1750196. http://dx.doi.org/10.1142/s0218126617501961.

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A fully-integrated self-startup circuit with ultra-low voltage for thermal energy harvesting is presented in this paper. The converter is composed of an enhanced swing LC oscillator and a charge pump with decreased equivalent input capacitance. The LC oscillator has ultra-low input voltage and high output voltage swing, and the charge pump has a fast charging speed and small equivalent input capacitance. This circuit is designed with 0.18[Formula: see text][Formula: see text]m standard CMOS process. The simulation results show that the output voltage is in the range of 0.14[Formula: see text]V and 2.97[Formula: see text]V when the input voltage is changed from 50[Formula: see text]mV to 150[Formula: see text]mV. The output voltage could reach 2.87[Formula: see text]V at the input voltage of 150[Formula: see text]mV and the load of 1[Formula: see text]M[Formula: see text]. The maximum efficiency is in the range of 10.0% and 14.8% when the input voltage is changed from 0.2[Formula: see text]V to 0.4[Formula: see text]V. The circuit is suitable for thermoelectric energy harvesting to start with ultra-low input voltage.

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41

Ueda, Tsuyoshi, Takahisa Ohji, Kenji Amei, and Masaaki Sakui. "A High-Power-Factor Single-Phase Voltage-Doubler Rectifier Circuit Using Parallel Charge-Pump." IEEJ Transactions on Industry Applications 128, no. 2 (2008): 151–52. http://dx.doi.org/10.1541/ieejias.128.151.

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42

Yamazoe, Takanori, Eiji Yamasaki, Nobuhiro Oodaira, and Musaaki Terasawa. "A charge pump without body effect that generates a positive or negative high voltage." Electronics and Communications in Japan (Part II: Electronics) 88, no. 3 (2005): 19–26. http://dx.doi.org/10.1002/ecjb.20097.

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43

Zhu, Tiezhu, Yuning Zhang, and Rendong Ji. "Design of a charge pump for high voltage driver applications based on 0.35 μm BCD technology." Modern Physics Letters B 31, no. 19-21 (July 27, 2017): 1740008. http://dx.doi.org/10.1142/s0217984917400085.

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Based on the switched capacitor system theory, a new charge pump is designed as the driver of the H-bridge power circuits. The proposed circuit is added with the output feedback control module to realize the steady output, lower the ripple and power noise, and improve the transforming efficiency. Simulation based on 0.35 [Formula: see text] BCD350GE process demonstrates that the circuit has a ripple voltage as low as 200 mV and reaches a high efficiency up to 70% with a load as much as 20 mA when the supply voltage changes from 8 V to 36 V.

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Prabhakar, Gyan, Abhishek Vikram, Rajendra Pratap, and R. K. Singh. "MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit." International Journal of Knowledge-based and Intelligent Engineering Systems 24, no. 4 (January 18, 2021): 311–21. http://dx.doi.org/10.3233/kes-190142.

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This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.

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Hu, Rong Bin, Kun Liu, and Jie Tang. "A Novel Charge Pumped Clock Generator for VLSI." Applied Mechanics and Materials 198-199 (September 2012): 1174–78. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1174.

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In this paper, a novel charge pumped clock generator is proposed, which can pump the reference cock to a level as high as double Vcc, while keeping the low level of the clock unchanged. The proposed circuit is very suitable for low voltage IC design to attain low on-resistance of MOS switch while keeping the parasitic capacitance small, which results in high speed of the circuit. The stimulated results show that the pumped clock has rising and falling time of 50ps and 67ps respectively.

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46

Luo, Zhicong, Li-Chin Yu, and Ming-Dou Ker. "An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 9 (September 2019): 3437–44. http://dx.doi.org/10.1109/tcsi.2019.2924581.

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47

Hwu, Kuo‐Ing, and Tso‐Jen Peng. "High‐voltage‐boosting converter with charge pump capacitor and coupling inductor combined with buck–boost converter." IET Power Electronics 7, no. 1 (January 2014): 177–88. http://dx.doi.org/10.1049/iet-pel.2013.0229.

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48

Shen, Chih-Lung, and Li-Zhong Chen. "Dual-Input Isolated Converter With Dual-Charge-Pump Cell for High Step-Up Voltage Ratio Achievement." IEEE Transactions on Industrial Electronics 67, no. 11 (November 2020): 9383–92. http://dx.doi.org/10.1109/tie.2019.2952793.

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49

Ma, Kezheng, Rene Van Leuken, Maja Vidojkovic, Jac Romme, Simonetta Rampu, Hans Pflug, Li Huang, and Guido Dolmans. "A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 225–32. http://dx.doi.org/10.2478/v10177-012-0031-5.

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Abstract The Phase Locked Loop (PLL) has become an important part of electrical systems. When designing a PLL, an efficient and reliable simulation platform for system evaluation is needed. However, the closed loop simulation of a PLL is time consuming. To address this problem, in this paper, a new PLL model containing both digital and analog parts based on SystemC/SystemC-AMS (BETA version) is presented. Many imperfections such as Voltage Control Oscillator (VCO) noise or reference jitter are included in this model. By comparing with the Matlab model, the SystemC/SystemC-AMS model can dramatically reduce simulation time. Also, by comparing with Analog Devices ADI SimPLL simulation results, Cadence simulation results and real measurement results, the accuracy of the SystemC/SystemC-AMS model is demonstrated. The paper shows the feasibility of a unified design environment for mixed-signal modelling based on SystemC/SystemC-AMS in order to reduce the cost and design time of electrical systems.

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50

WOO, YOUNGSHIN, YOUNG MIN JANG, and MAN YOUNG SUNG. "A NOVEL METHOD FOR HIGH-PERFORMANCE PHASE-LOCKED LOOP." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 53–63. http://dx.doi.org/10.1142/s0218126604001271.

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In this paper, we propose a phase-locked loop (PLL) with dual PFDs and a modified loop filter in which advantages of both PFDs can be combined and the trade-off between acquisition behavior and locked behavior can be achieved. By operating the appropriate PFD connected to the well-adjusted charge pump and regulating the loop bandwidth to input frequency ratio with an input divider and a modified loop filter, an unlimited error detection range, a high frequency operation, a reduced dead zone and a higher speed lock-up time can be achieved. The proposed PLL structure is designed using 1.5 μm CMOS technology with 5 V supply voltage.

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