Dissertations / Theses: 'High voltage/low voltage redundancy'

1

Zhou, Xunwei. "Low-voltage High-efficiency Fast-transient Voltage regulator Module." Diss., Virginia Tech, 1999. http://hdl.handle.net/10919/28832.

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In order to meet demands for faster and more efficient data processing, modern microprocessors are being designed with lower voltage implementations. The processor voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be packed on a single processor chip, and processors will operate at higher frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power management. Future generation processors will draw current up to 50 A ~ 100 A [2]. These demands, in turn, will require special power supplies and Voltage Regulator Modules (VRMs) to provide lower voltages with higher currents and fast transient capabilities for microprocessors. This work presents several low-voltage high-current VRM technologies for future generation data processing, communication, and portable applications. The developed advanced VRMs with these new technologies have advantages over conventional ones in power density, efficiency, transient response, reliability, and cost. The multi-module interleaved quasi-square-wave VRM topology achieves a very fast transient response and a very high power density. This topology significantly reduces the filter inductance and capacitance, while having small output and input ripples. The analysis, design, and experimental verification for this new topology are presented in this work. The current sensing and current sharing techniques are developed with simple and cost-effective implementations. With this technique, traditional current transformers and sensing resistors are not required, and the inductance value, MOSFET on resistance and other parasitics have no effect on current sharing results. The design principles are developed and experimentally verified. A generalized approach and an extension of the novel current sharing control are presented in this work. The techniques for improving VRM light load efficiency are developed in this work. By utilizing the duty cycle signal, VRMs can be implemented with advanced power management functions to reduce further the power consumption at light loads to extend the battery-operation time in portable systems or to facilitate the compliance with various "energy star" ("green" power) requirements in office systems. Four improved approaches are presented and verified with experimental results. The high-input-voltage VRM topology, push-pull forward converter, can be used in high-bus-voltage distributed power systems. This converter has a high efficiency, a high power density, a fast transient response, and can be easily packaged as a standard module. The circuit design and experimental evaluation are addressed to demonstrate the operation principles and advantages of this topology.
Ph. D.

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2

Ng, Wing Lun. "Low-voltage high-frequency CMOS transformer-feedback voltage-controlled oscillators /." View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20NG.

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Bergquist, Hampus. "A self restoring system on low voltage level." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-181804.

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Fortums electric grid in Norra Djurgårdsstaden is a test grid for smart equipment and they are investigating new techniques and ways to improve the quality of the grid. With the quality improvements that are researched, a "self-restoring system" is a part of the research with the intention to lower the amount of outages and shorten the time it takes to restore faults. This thesis can be seen as a part of the optimization process of the grid in Norra Djurgårdsstaden where the benefits with a basic self-restoring system have been investigated on low voltage level. In the thesis the self-restoring system has been classified into a "basic" and an "advanced" category. The basic self-restoring system cross-connect several feeding paths by cross-connecting different low voltage grids and use mechanical equipment to change between cables when a fault in a cable occurs. The advanced self-restoring system uses several feeders and smart grid technology with equipment and softwares which communicate and visualize the grid. The difference between the systems is that the advanced system can visualize the grid and is able to tell when and where faults have occurred to a more detailed level. The advanced system can also calculate the power available and does not need the same amount of cables for redundancy because it can command users to lower their consumption when an outage has occurred. A decision was made to only investigate the technique on low voltage level because a basic system already exists on medium voltage in Norra Djurgårdsstaden. Results show that investing in a basic self-restoring system in Norra Djurgårdsstaden would cost about 2 million SEK and lower the total amount of outages for the customers in the area from 45 minutes per customer and year down to about 41 minutes. The reason why the decrease is only four minutes per year and customer is because faults occurring on higher voltage level cannot be reduced with the system. It is totally about 10 % of the faults that occur on low voltage level. One conclusion from the thesis is that the reduction in quality costs which are because to the lowered outages will not be enough to pay back the investment. More outage-time per customer and year need to be prevented with the system or the customers need to value reduced outages significantly more.

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Zhang, Yan. "Cost reflective network pricing for high voltage and low voltage distribution networks." Thesis, University of Bath, 2012. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.558863.

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Li, Wei Ph D. Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science. "Very-high-frequency low-voltage power delivery." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/82352.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 217-223).
Power conversion for the myriad low-voltage electronic circuits in use today, including portable electronic devices, digital electronics, sensors and communication circuits, is becoming increasingly challenging due to the desire for lower voltages, higher conversion ratios and higher bandwidth. Future computation systems also pose a major challenge in energy delivery that is difficult to meet with existing devices and design strategies. To reduce interconnect bottlenecks and enable more flexible energy utilization, it is desired to deliver power across interconnects at high voltage and low current with on- or over-die transformation to low voltage and high current, while providing localized voltage regulation in numerous zones. This thesis introduces elements for hybrid GaN-Si dc-de power converters operating at very high frequencies (VHF, 30-300 MHz) for low-voltage applications. Contributions include development of a new VHF frequency multiplier inverter suitable for step-down power conversion, and a Si CMOS switched-capacitor step-down rectifier. These are applied to develop a prototype GaN-Si hybrid dc-dc converter operating at 50 MHz. Additionally, this thesis exploits these elements to propose an ac power delivery architecture for low-voltage electronics in which power is delivered across the interconnect to the load at VHF ac, with local on-die transformation and rectification to dc. With the proposed technologies and emerging passives, it is predicted that the ac power delivery system can achieve over 90 % efficiency with greater than 1 W/mm² power density and 5:1 voltage conversion ratio. A prototype system has been designed and fabricated using a TSMC 0.25 [mu]m CMOS process to validate the concept. It operates at 50 MHz with output power of 4 W. The prototype converter has 8:1 voltage conversion ratio with input voltage of 20 V and output voltage of 2.5 V. To the author's best knowledge, this is the first ac power delivery architecture for low-voltage electronics ever built and tested.
by Wei Li.
Ph.D.

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Lieu, Anthony D. "A New Architecture For Low-Voltage Low-Phase-Noise High-Frequency CMOS LC Voltage-Controlled Oscillator." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7109.

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Presented in this work is a novel design technique for a low-phase-noise high-frequency CMOS voltage-controlled oscillator. Phase noise is generated from electrical noise near DC, the oscillation frequency, and its harmonics. In CMOS technology, low-frequency flicker noise dominates the close-in phase noise of the VCO. The proposed technique minimizes the VCO phase noise by seeking to eliminate the effect of flicker noise on the phase noise. This is accomplished by canceling out the DC component of the impulse sensitivity function (ISF) corresponding to each flicker-noise source, thus preventing the up-conversion of low-frequency noise into phase noise. The proposed circuit topology is a modified version of the complementary cross-coupled transconductance VCO, where additional feedback paths are introduced such that a designer can choose the feedback ratios, transistor sizes, and bias voltages to achieve the previously mentioned design objectives. A step-by-step design algorithm is presented along with a MATLAB script to aid in the computation of the ISFs and the phase noise of the VCO. Using this algorithm, a 5-GHz VCO was designed and fabricated in a 0.18μm CMOS process, and then tested for comparison with simulated results.

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Zhao, Shishuo. "High Frequency Isolated Power Conversion from Medium Voltage AC to Low Voltage DC." Thesis, Virginia Tech, 2017. http://hdl.handle.net/10919/74969.

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Modern data center power architecture developing trend is analyzed, efficiency improvement method is also discussed. Literature survey of high frequency isolated power conversion system which is also called solid state transformer is given including application, topology, device and magnetic transformer. Then developing trend of this research area is clearly shown following by research target. State of art wide band gap device including silicon carbide (SiC) and gallium nitride (GaN) devices are characterized and compared, final selection is made based on comparison result. Mostly used high frequency high power DC/DC converter topology dual active bridge (DAB) is introduced and compared with novel CLLC resonant converter in terms of switching loss and conduction loss point of view. CLLC holds ZVS capability over all load range and smaller turn off current value. This is beneficial for high frequency operation and taken as our candidate. Device loss breakdown of CLLC converter is also given in the end. Medium voltage high frequency transformer is the key element in terms of insulation safety, power density and efficiency. Firstly, two mostly used transformer structures are compared. Then transformer insulation requirement is referred for 4160 V application according to IEEE standard. Solid insulation material are also compared and selected. Material thickness and insulation distance are also determined. Insulation capability is preliminary verified in FEA electric field simulation. Thirdly two transformer magnetic loss model are introduced including core loss model and litz wire winding loss model. Transformer turn number is determined based on core loss and winding loss trade-off. Different core loss density and working frequency impact is carefully analyzed. Different materials show their best performance among different frequency range. Transformer prototype is developed following designed parameter. We test the developed 15 kW 500 kHz transformer under 4160 V dry type transformer IEEE Std. C57.12.01 standard, including basic lightning test, applied voltage test, partial discharge test. 500 kHz 15 kW CLLC converter gate drive is our design challenge in terms of symmetry propagation delay, cross talk phenomenon elimination and shoot through protection. Gate drive IC is carefully selected to achieve symmetrical propagation delay and high common mode dv/dt immunity. Zero turn off resistor is achieved with minimized gate loop inductance to prevent cross talk phenomenon. Desaturation protection is also employed to provide shoot through protection. Finally 15 kW 500 kHz CLLC resonant converter is developed based on 4160V 500 kHz transformer and tested up to full power level with 98% peak efficiency.
Master of Science

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8

Aliahmad, Mehran. "High voltage circuits for short loop SLICs in a low voltage submicron BiCMOS technology." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0006/NQ41393.pdf.

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9

Larsson, Anders. "On high-frequency distortion in low-voltage power systems." Doctoral thesis, Luleå tekniska universitet, Energivetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-26658.

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Power quality is a subject that has received a lot of attention during the last 10 to 20 years, both in industry and in academia. Power quality concerns interaction between the power grid and its customers and between the power grid and equipment connected to it, reflected in voltages and currents. Research and other developments in this area have to a great extent concentrated on relatively slow and low-frequency phenomena, with the main emphasis being on voltage dips (reductions in voltage magnitude with duration between about 50 ms and several seconds) and low-frequency harmonics (waveform distortion by frequency components up to about 2 kHz). These phenomena are reasonably well understood and several standards cover the area. For higher-frequency phenomena, above 2 kHz, there is no such general understanding, nor is there anything close to a complete set of standards covering this area. Modern energy efficient equipment connected to the grid, like fluorescent lamps but also solar panels, often uses switching technology, with switching frequencies that can range from a couple of kHz up to several hundreds of kHz. The grid is also used for communication of e.g. meter readings, system controls etc. This so-called power-line communication is using the same frequency range. The main frequency range of interest for this thesis has been the range from 2 to 150 kHz. There are two completely different measurement methods covering this frequency range: time-domain based and frequency-domain based. Time domain based measurements are used throughout the thesis. This gives an opportunity to choose between different analysing tools where among others the joint time-frequency domain has shown to be a useful tool for describing waveform distortion in our frequency range of interest. The majority of the measurements presented in this thesis have been directed towards fluorescent light powered by high frequency ballasts. This type of load has been, due to stringent harmonic limits, one of the first to use a more advanced switching technology called active power factor correction. This technique is also getting more frequently used in other small-power equipment, like computers. Installations of lights in stores etc. normally contain a large number of ballast connected together and the interaction is of importance, for example for setting emission and immunity standards. The measurements on ballasts presented in this work have shown that distortion in the frequency rage 2-150 kHz comes in three types: narrowband distortion; wideband distortion; and recurrent oscillations. The recurrent oscillations are a new type of powerquality disturbance that had not been recognized as such before. The measurements further have shown that the three types of distortion spread in a completely different way from the individual devices to the grid. This knowledge is essential for the setting of emission requirements on energy-efficient equipment.
Godkänd; 2011; 20110216 (andlar); DISPUTATION Nedanstående person kommer att disputera för avläggande av teknologie doktorsexamen. Namn: Anders Larsson Ämnesområde: Energiteknik/Energy Engineering Avhandling: On High-Frequency Distortion in Low-Voltage Power Systems Opponent: Adj. professor Lars Gertmar, Institutionen för industriell elektroteknik och automation, Lunds universitet Ordförande: Professor Math Bollen, Institutionen för teknikvetenskap och matematik, Luleå tekniska universitet Tid: Onsdag den 23 mars 2011, kl 10.00 Plats: Hörsal A, Campus Skellefteå, Luleå tekniska universitet

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10

Çoban, Abdulkerim Levent. "A low-voltage high-resolution audio delta-sigma modulator." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/15514.

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Salazar, Nathaniel Jay Tobias. "High frequency AC power converter for low voltage circuits." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/77026.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 74-76).
This thesis presents a novel AC power delivery architecture that is suitable for VHF frequency (50-100MHz) polyphase AC/DC power conversion in low voltage integrated circuits. A complete AC power delivery architecture was evaluated demonstrating the benefits of delivering power across the interconnect at high voltage and lower current with on- or over-die transformation to low voltage and high current. Two approaches to polyphase matching networks in the transformation stage are compared: a 3-phase system with separate single-phase matching networks and individual full bridge rectifiers, and a 3-phase delta-to-wye matching network and a 3-phase rectifier bridge. In addition, a novel switch-capacitor rectifier capable of 3V, 1W output, was evaluated as an alternative circuit to the diode rectifiers. A 50MHz prototype of each version of the system was designed and built for a 12:1 conversion ratio with 24Vpp line-to-line AC input, 2V DC output and 0.7W output power. The measured overall system efficiency is about 63 % for the 3-phase delta system. Although the application is intended for an integrated CMOS implementation, this thesis primarily focuses on discrete PCB level realizations of the proposed architectures to validate the concept and provide insights for future designs.
by Nathaniel Jay Tobias Salazar.
M.Eng.

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12

Rogers, Michael. "High-speed low-voltage line driver for SerDes applications." Thesis, Oxford Brookes University, 2009. https://radar.brookes.ac.uk/radar/items/d7f9d856-ae6d-4eab-bb7d-aa54376560d6/1/.

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The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps.

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13

Chen, Wei. "Low Voltage High Current Power Conversion with Integrated Magnetics." Diss., Virginia Tech, 1998. http://hdl.handle.net/10919/30518.

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Very low voltage, high current output requirement have necessitated improvements in power supply's density and efficiency. Existing power conversion techniques cannot meet very stringent size and efficiency requirements. By applying the proposed magnetic integration procedure, new integrated magnetic circuits featuring low loss, simple structure, and ripple cancellation technique are then developed to overcome the limitations of prior art. Both cores and windings are integrated. Consequently, the power loss and the size of the integrated magnetic device are greatly reduced. Detailed analysis and design considerations of the proposed circuits are presented. As a result of applying the proposed technique, very high density, high efficiency, low voltage, high current power modules were developed. A typical example features an isolated 3.3V/30A power module with a power density of 130W/in3 and an efficiency of 90% at 500 KHz switching frequency.
Ph. D.

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14

Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.

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The increasingly stringent requirements of today's communication systems and portable devices are imposing two challenges on the design of Analog-to-Digital Converters (ADC) and delta-sigma modulators (DeltaSigmaM) architecture in particular.
The first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.

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15

Zeljkovic, Sandra [Verfasser]. "IGBT-based High Voltage to Low Voltage DC/DC Converter for Electric and Hybrid Vehicles / Sandra Zeljkovic." Aachen : Shaker, 2015. http://d-nb.info/1074087283/34.

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16

zhou, hua. "MAGNETICS DESIGN FOR HIGH CURRENT LOW VOLTAGE DC/DC CONVERTER." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3381.

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With the increasing demand for small and cost efficient DC/DC converters, the power converters are expected to operate with high efficiency. Magnetics components design is one of the biggest challenges in achieving the higher power density and higher efficiency due to the significant portion of magnetics components volume in the whole power system. At the same time, most of the experimental phenomena are related to the magnetics components. So, good magnetics components design is one of the key issues to implement low voltage high current DC/DC converter. Planar technology has many advantages. It has low profile construction, low leakage inductance and inter-winding capacitance, excellent repeatability of parasitic properties, cost efficiency, great reliability, and excellent thermal characteristics. On the other side, however, planar technology also has some disadvantages. Although it improves thermal performance, the planar format increases footprint area. The fact that windings can be placed closer in planar technology to reduce leakage inductance also often has an unwanted effect of increasing parasitic capacitances. In this dissertation, the planar magnetics designs for high current low voltage applications are thoroughly investigated and one CAD design methodology based on FEA numerical analysis is proposed. Because the frequency dependant parasitic parameters of magnetics components are included in the circuit model, the whole circuit analysis is more accurate. When it is implemented correctly, integrated magnetics technique can produce a significant reduction in the magnetic core content number and it can also result in cost efficient designs with less weight and smaller volume. These will increase the whole converter's power density and power efficiency. For high output current and low output voltage applications, half bridge in primary and current doublers in secondary are proved to be a very good solution. Based on this topology, four different integrated magnetics structures are analyzed and compared with each other. One unified model is introduced and implemented in the circuit analysis. A new integrated magnetics component core shape is proposed. All simulation and experimental results verify the integrated magnetics design. There are several new magnetics components applications shown in the dissertation. Active transient voltage compensator is a good solution to the challenging high slew rate load current transient requirement of VRM. The transformer works as an extra voltage source. During the transient periods, the transformer injects or absorbs the extra transient to or from the circuit. A peak current mode controlled integrated magnetics structure is proposed in the dissertation. Two transformers and two inductors are integrated in one core. It can force the two input capacitors of half bridge topology to have the same voltage potential and solve the voltage unbalance issue. The proposed integrated magnetics structure is simple compared with other methods implementing the current mode control to half bridge topology. Circuit analysis, simulation and experimental results verify the feasibility of these applications.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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17

Hu, Jingying Ph D. Massachusetts Institute of Technology. "Design of low-voltage, high-bandwidth radio frequency power converters." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75637.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 158-166).
The mass and volume required for power electronics circuitry is a dominant obstacle to the miniaturization and integration of many systems. Likewise, power electronics with greater bandwidth and efficiency are becoming vital in many applications. To realize smaller and highly responsive power electronics at low voltages, this thesis explores devices, circuits, and passives capable of operating efficiently at very high frequencies (VHF, 30-300 MHz). Operation at these frequencies enables reduction of the numerical values and physical size of the passive components that dominate power converters, and enables increased bandwidth and transient performance which is valuable in a multitude of low-voltage and low-power applications. This thesis explores the scaling of magnetic component size with frequency, and it is shown that substantial miniaturization is possible with increased frequencies even considering material and heat transfer limitations. Moreover, the impact of frequency scaling of power converters on magnetic components is investigated for different design criteria. Quantitative examples of magnetics scaling are provided that clearly demonstrate the benefits and opportunities in VHF magnetics design. It is shown to utilize the advantages of frequency scaling on passive component size that system losses and other limitations must be considered. One such area that is examined is semiconductor device requirements, where through a combination of device layout optimization for cascode structures and integrated gate drive designs on a 0.35-um CMOS process, converter performance (i.e., loss and bandwidth) can be significantly improved in the VHF regime. In this thesis a dc-dc converter topology is developed that is suitable for low-voltage power conversion and employs synchronous rectification to improve efficiency. The converter is also comprised of a high-bandwidth and high-switching-frequency inverter topology that can dynamically adjust the output power from one-quarter to full power, while maintaining good efficiency. Furthermore, with its inherent capability of gate-width switching, the inverter can further reduce gating loss by one-half resulting in substantial performance improvements at light load operation. A major contribution of this thesis is the development of a synchronous rectifier operating in the VHF regime. VHF power conversion is especially challenging at low voltages due to poor efficiency resulting from rectification loss. To overcome diode rectification loss, the benefits of synchronous rectification are discussed in the context of a 100MHz class-E resonant rectifier, which results in a 2.5 x overall converter efficiency improvement. The culmination of the developed design techniques in passives, semiconductor devices, and circuit topologies is an experimental prototype of a miniaturized 100MHz, 1W power converter utilizing synchronous rectification.
by Jingying Hu.
Ph.D.

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Yang, Boyi. "High Performance Low Voltage Power MOSFET for High-Frequency Synchronous Buck Converters." Doctoral diss., University of Central Florida, 2012. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5582.

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Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35[micro]m process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.
ID: 031001367; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Adviser: Weiwei Deng.; Title from PDF title page (viewed May 8, 2013).; Thesis (M.S.M.E.)--University of Central Florida, 2012.; Includes bibliographical references (p. 84-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering

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19

Poitzsch, Alec Julius. "A high voltage, high current, low error operational amplifier with novel features." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91698.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 173-174).
This project details the design and evaluation of an operational amplifier designed in XF40, a 40 Volt bipolar process. Initially the signal path circuitry of the amplifier is outlined. Design decisions are chiefly formed around high voltage and high current drive functionality. A novel topology is introduced which compensates base current errors introduced by the individual stages, resulting in a very low (first-order canceled) overall input-referred voltage offset. Novel features are introduced which expand the functionality of the amplifier. Input stage gm is configurable, allowing for the tuning of amplifier bandwidth for a given gain configuration. A robust current-limiting architecture is implemented which allows for a user-configurable output current limit. When this current limit is reached, the amplifier latches into an alternate mode of operation, protecting the amplifier and the load. We utilize disjoint voltage supply rails at the input and output of the amplifier, substantially minimizing overall power dissipation. The chosen topology permits this feature without the introduction of additional errors. We introduce a "boosting" circuit which extends the large signal bandwidth and slew rate of the amplifier. Amplifier performance is evaluated through simulation in Cadence and ADICE (SPICE). The amplifier is capable of driving 1 Ampere through capacitive and resistive loads. The result is a low distortion amplifier with microvolt-order input-referred offset (VOS), 65 MHz large signal bandwidth, and 3000 V/[mu]s slew rate, powered at 20 mA quiescent current.
by Alec Julius Poitzsch.
M. Eng.

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Maric, Bojan. "Cache designs for reliable hybrid high and ultra-low voltage operation." Doctoral thesis, Universitat Politècnica de Catalunya, 2014. http://hdl.handle.net/10803/144563.

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Increasing demand for implementing highly-miniaturized battery-powered ultra-low-cost systems (e.g., below 1 USD) in emerging applications such as body, urban life and environment monitoring, etc., has introduced many challenges in the chip design. Such applications require high performance occasionally, but very little energy consumption during most of the time in order to extend battery lifetime. In addition, they require real-time guarantees. The most suitable technological solution for those devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/sub-threshold (NST) voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and it is mandatory trading off different SRAM designs, especially in cache memories, which occupy most of the processor¿s area. In this Thesis, we analyze the performance/power tradeoffs involved in the design of SRAM L1 caches for reliable hybrid high and NST Vcc operation from a microarchitectural perspective. We develop new, simple, single-Vcc domain hybrid cache architectures and data management mechanisms that satisfy all stringent needs of our target market. Proposed solutions are shown to have high energy efficiency with negligible impact on average performance while maintaining strong performance guarantees as required for our target market.

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21

Gupta, Vishal. "An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC." Diss., Available online, Georgia Institute of Technology, 2007, 2007. http://etd.gatech.edu/theses/available/etd-07052007-073154/.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Chair ; Bhatti, Pamela, Committee Member ; Leach, W. Marshall, Committee Member ; Morley, Thomas, Committee Member.

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22

Mostafa, Ahmed. "The design of low-voltage high-frequency CMOS LC-based oscillators /." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=33982.

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With the rapidly accelerating world of communications, there has been an increased interest in monolithic integration. CMOS technology has become a natural candidate for system integration being the technology of choice for digital circuit implementation.
This thesis presents several LC-based CMOS voltage controlled oscillators, demonstrating the capability and benefits of the technology in high-frequency designs. Through optimization of a simple LC oscillator, a 4 GHz circuit operating at a supply voltage as low as 0.85 V was implemented and measured. Optimization of a symmetric LC oscillator realized frequencies of 10 and 12.5 GHz. A novel oscillator architecture combining both high-frequency and low-voltage operation is also proposed in this thesis. This new oscillator structure allows for two tuning mechanisms, thus increasing the tuning range of the oscillator. The optimization of these designs was made without sacrificing other essential requirements of the oscillators such as phase noise. This is demonstrated by achieving comparable results to those reported in state-of-the-art publications.

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23

Chen, Wei. "Fast switching low power loss devices for high voltage integrated circuits." Thesis, University of Cambridge, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.262863.

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24

Rainbird, Paul L. "Prediction of temperature rise in low voltage high current electrical switchboards." Thesis, Queensland University of Technology, 1990. https://eprints.qut.edu.au/36452/1/36452_Rainbird_1990.pdf.

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At present, the electrical switchboard designer us ually constructs a full-scale prototype and tests it at rated current to ascertain its temperature rise performance, under simulated normal operating conditions. Temperatures are then reduced by application of one or several techniques including modification of the switchboard design. Steady-state temperature rise within an electrical switchboard is attained when t he Joule heat generated by electrical losses is exactly balanced by the heat l ost by cooling. The basic factors affecting this heat balance in electrical switchboards are r eviewed in this thesis . Also, the available empirical and computer based techniques which have been used to predict the temperature rise of electrical components such as cables, busbars, and circuit breakers as well as electrical switchboards containing these components, are discussed in detail. In view of the time and expense of development testing using techniques such as the above, this thesis introduces the concept of representing · the electrical switchboard heat transfer processes of radiation, convection, conduction, and natural ventilation by thermal equivalent resistances which are analogous to resistances in electric field theory. It is shown how thermal equivalent resistance circuits of individual switchboard components enable evaluation of their temperature rise and power loss performance The temperature rise experiments and the deve l opment of thermal equivalent resistance circuits for a 400 A moulded case circuit breaker and a 1600 A medi um voltage air circuit breaker , for a wide range of unenclosed and enc losed opera t ing conditions, are descr ibed and analysed . This thesis also presents the results of tests performed on a number of typical switchboard ventilators to quantify in real terms t heir ability to remove internally generated Joule heat from within electrical switchboards by natural ventilation. This analysis required the construction of a ventilator experimental test rig which is used to accurately simulate the actual operating conditions of a ventilator in nn electrical switchboard. The visualisation of the air flow patterns through these ventilators is also investigated. In line with the above described experiments, tests are performed on a full-scale electrical switchboard to determine its temperature rise and power loss performance for various ventilation configurations . From the measurement of the small differential pressure drops across the switchboard ventilators and internal components , the major obstructions to natura l ventilation and convection air flow within the switchboard are identified . To conduct these experiments on the switchboard, an automatic testing system was developed. This system, using a HP85 personal computer, digital multifunction meter, process datal ogger, pneumatic scanning box, digital micromanometer, and a special IEEE 488 input/output device, enables the automatic measurement, logging , and processing of electrical switch board experimental test data. This thesis also describes a computer program d e veloped by Van Leersum (16, 17) which has been used in the prediction of temperature rise o f simple non-vented heated enclos ures containing electronic equipment. A joint collaborative pro j ect between the Queensland University of Technology and the CSIRO's Division of Energy Technology was established to examine t he possibility of adapting this computer program, b a s~d upon the results of the t emperature rise tests on switchboard components d e scribed herein, so as to predict the t ~mperature r ise performance of vent i l ated enclosures such as electrica l switchboards. Simulations using this computer program are performed on both an idealised switchboard enclosure and a full-scale electrical switchboard over a wide range of operating conditions . Comparisons with experimental results revealed that the computer program could predict temperature rises to an accuracy of ±6 percent. It is concluded that although computer programs of this type are new to the electrical switchboard manufacturing industry in Australia and indeed throughout the world, their application in commercial switchboard design is justified in terms of both accuracy of temperature rise prediction and economic benefit development testing i n of that costly and time low voltage high current switchboards is not requi red. consuming electrica

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25

Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.

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26

Lee, Choong Hoon. "Design of high speed low voltage data converters for UWB communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/3798.

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For A/D converters in ultra-wideband (UWB) communication systems, the flash A/D type is commonly used because of its fast speed and simple architecture. However, the number of comparators in a flash A/D converter exponentially increases with an increase in resolution; therefore, an interpolating technique is proposed in this thesis to mitigate the exponential increase of comparators in a flash converter. The proposed structure is designed to improve the system bandwidth degradation by replacing the buffers and resistors of a typical interpolating technique with a pair of transistors. This replacement mitigates the bandwidth degradation problem, which is the main drawback of a typical interpolating A/D converter. With the proposed 4-bit interpolating structure, 3.75 of effective number of bits (ENOB) and 31.52dB of spurious-free dynamic range (SFDR) are achieved at Nyquist frequency of 264MHz with 6.93mW of power consumption. In addition, a 4-bit D/A converter is also designed for the transmitter part of the UWB communication system. The proposed D/A converter is based on the charge division reference generator topology due to its full swing output range, which is attractive for low-voltage operation. To avoid the degradation of system bandwidth, resistors are replaced with capacitors in the charge division topology. With the proposed D/A converter, 0.26 LSB of DNL and 0.06 LSB of INL is obtained for the minimum input data stream width of 1.88ns. A 130 Âµm Ã286 Âµm chip area is required for the proposed D/A converter with 19.04mW of power consumption. The proposed A/D and D/A converter are realized in a TSMC 0.18 Âµm CMOS process with a 1.8 supply voltage for the 528MHz system frequency.

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27

袁綺珊 and Yee-shan Cherry Yuen. "High impedance fault detection and overvoltage protection in low voltage power systems." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1998. http://hub.hku.hk/bib/B31222146.

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28

Yao, Liangbin. "HIGH CURRENT DENSITY LOW VOLTAGE ISOLATED DC-DC CONVERTERSWITH FAST TRANSIENT RESPONSE." Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3205.

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With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.
Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD

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29

Ha, Miranda J. (Miranda Joy). "A low-power, high-bandwidth LDO voltage regulator with no external capacitor." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45647.

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This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 38).
A low-dropout (LDO) voltage regulator for low-power applications is designed without an external capacitor for compensation. The regulator has two stages, the first a folded cascode amplifier and the second a large pass transistor acting as a common-source amplifier. To better explore the tradeoff between bandwidth and power supply rejection, transistor dimensions are modified to support three different bias current levels for the same topology. Tradeoffs involving phase margin and load capacitance are also explored. In simulation, the regulator provided an output of 1.3 V from an unregulated 1.8 V supply, using a 0.75 V reference. By exploiting the tradeoffs between PSRR, bandwidth, and power consumption, a PSRR between 40-60 dB is achieved with a bandwidth between 10 kHz-350 kHz while burning no more than 150 pA of current. The output voltage is stable for load currents between 18-174 mA.
by Miranda J. Ha.
M.Eng.

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30

Yuen, Yee-shan Cherry. "High impedance fault detection and overvoltage protection in low voltage power systems /." Hong Kong : University of Hong Kong, 1998. http://sunzi.lib.hku.hk/hkuto/record.jsp?B20735297.

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31

Kazim, Muhammad Anser. "Designing Smart Electrical Panels for Existing Wastewater Treatment Plants to Achieve Optimised Biogas Production and Cogeneration with HV/LV and Communication Redundancy for Smart Grid." Thesis, 2018. https://vuir.vu.edu.au/37856/.

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Recognising the deep potential in wastewater treatment plant (WWTP) automation strategies, this research focuses on expanding the plant operations in order to optimally utilise the produced biogas during the wastewater treatment process to achieve electricity cogeneration and High Voltage/Low Voltage (HV/LV) redundancy. The research has resulted in a proposed design for a smart Remote Terminal Unit (RTU). The proposed design also enables a failsafe mechanism at different levels of the water treatment process and biogas production thus facilitating an automated WWTP electricity cogeneration. The proposed design also increases the life span of substations, reduces power demand load on the grids and enhances safety of WWTP equipment during various scenarios of electricity cogeneration, shut downs and maintenance operations. Monitoring, operating and controlling of WWTPs is a complex and challenging task. The power equipment in most of the existing or old WWTPs that generates electricity from the biogas produced in the water treatment process requires intensive supervision and control to enable failsafe and redundant electricity cogeneration process. This research focuses on setting up an effective communication system between power equipment at existing or older WWTP distribution substations and power company`s zone substations, without the need to upgrade expensive switchgear and power equipment in the network. The proposed philosophy achieves automated and failsafe communication network for SCADA link to enable WWTP electricity cogeneration, utilising exiting or old infrastructure. This critical multidirectional power and data flow requires proper compliant and semantic data models to guarantee smooth and safe operations. It also requires to be flexible and have the ability to develop and implement the telemetric mapping philosophy between the substations during various scenarios of electricity cogeneration and faults. This research has resulted in a proposal of smart Remote Terminal Units (RTUs) on existing or old infrastructure of WWTP to achieve electricity cogeneration with integrated renewable energy resource

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32

Chen, Shih-Lun, and 陳世倫. "High-Voltage Circuit Design in Low-Voltage CMOS Processes." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/70309962398742844556.

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博士
國立交通大學
電子工程系所
94
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown, hot-carrier degradation, leakage issues, and so on will occur. Therefore, designing the high-voltage circuits in low-voltage CMOS processes is an important topic in today and future VLSI (very large scale integration) design. In this dissertation, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented. There are seven chapters included in this dissertation. Two new mixed-voltage I/O buffers realized with low-voltage devices are presented in Chapter 2 to prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. These two new mixed-voltage I/O buffer have novel gate-tracking circuits and dynamic n-well bias circuits. Compared with the prior designs of mixed-voltage I/O buffers, these two new mixed-voltage I/O buffers occupy smaller silicon area. Besides, the new proposed mixed-voltage I/O buffer 2 can be applied for high-speed applications without the gate-oxide reliability problem and the circuit leakage issue. The new proposed mixed-voltage I/O buffers realized with 1×VDD devices can be easily applied in 1×VDD/2×VDD mixed-voltage interface. Due to the high-integration trend of SOC (system-on-a-chip), an electronic system may be integrated into a single chip. Hence, there are digital circuits and analog circuits integrated in a single chip. For example, the digital part of the SOC is designed with 1-V devices to decrease its power consumption, the analog part is designed with 2.5-V devices to improve the circuit performance, and the chip-to-chip interface is 3.3-V PCI-X in a 0.13-µm 1/2.5-V CMOS process. Thus, the traditional I/O circuits are not suitable for this application. An input buffer with the proposed Schmitt trigger circuit and an output buffer with the proposed level converter in a 0.13-µm 1/2.5-V CMOS process are presented in Chapter 3 for 3.3-V applications. An NMOS-blocking technique for mixed-voltage I/O buffer design is presented in Chapter 4. Unlike the traditional mixed-voltage I/O buffer design, the mixed-voltage I/O buffer realized with only 1×VDD devices by using the NMOS-blocking technique can receive 2×VDD, 3×VDD, and even 4×VDD input signals without the gate-oxide reliability issue. In this dissertation, the 2×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3×VDD input tolerant mixed-voltage I/O buffer by using the NMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The NMOS-blocking technique can be extended to design the 4×VDD, 5×VDD, and even 6×VDD input tolerant mixed-voltage I/O buffers. The limitation of the NMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process. A new charge pump circuit without the gate-oxide overstress is presented in Chapter 5. Because the charge transfer switches of the new proposed charge pump circuit can be fully turned on and turned off, as well as the output stage doesn’t have the threshold drop problem, its pumping efficiency is higher than that of the prior designs. The gate-drain and the gate-source voltages of all devices in the new charge pump circuit don’t exceed VDD, so the new charge pump circuit doesn’t suffer the gate-oxide reliability problem. Besides, the proposed charge pump circuit has two pumping branches pumping the output node alternately so the output voltage ripple is small. The proposed circuit is suitable in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices. In general, the output voltage of the charge pump circuit will be limited by the breakdown voltage of the parasitic pn-junction in the given CMOS process. Chapter 6 presents an on-chip ultra-high-voltage charge pump circuit designed with the polysilicon diodes in low-voltage standard CMOS processes. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of parasitic pn-junction. The polysilicon diodes can be implemented in the standard (bulk) CMOS processes without extra process steps. The proposed charge pump circuit designed with the polysilicon diodes has been fabricated and verified in a 2.5-V 0.25-µm bulk CMOS process. In summary, several circuits designed in low-voltage CMOS processes but operated in high-voltage environments are presented in this dissertation. The proposed circuits have been implemented and verified in silicon chips. The proposed circuits are very useful and cost-efficient for the advanced SOC applications.

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33

Lai, Fu-Shiang, and 賴富祥. "The Process Integration of High Voltage and Low Voltage Device." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/08055164919704217671.

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34

Wang, Chung-Chih, and 王寵智. "Design of A High Voltage Regulator Circuits for Low Supply Voltage." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/53557650385828017980.

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碩士
國立中興大學
電機工程學系
93
This thesis proposes a high voltage regulator circuit for low supply voltages, which includes ring oscillator circuit, four-phase generator circuit, high-amplitude generator circuit, charge pumping circuit, band-gap reference (BGR) circuit, voltage regulator circuit, voltage regulator controller circuit. The operations of these sub-circuits and the complete regulator are introduced. The thesis also analyzes the low voltage dual pumping circuit and compares, the results of measurement and simulations. In addition, the sub-1V CMOS band-gap reference circuit is analyzed. The theoretical derivation proves and explains why the output waveforms are different from those of the other band-gap reference circuits. Finally, the high voltage regulator circuit is used to generate the output voltages of 6V, 7V, and 8V. It has been taped out using 0.35m CMOS technology.

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35

Chang, Wei-Jen, and 張瑋仁. "High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/70232955293959803259.

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博士
國立交通大學
電子工程系所
96
The scaling trend of the CMOS technology is toward the nanometer region to increase the speed and density of the transistors in integrated circuits. Due to the reliability issue, the power supply voltage is also decreased with the advanced technologies. However, in an electronic system, some circuits could be still operated at high voltage levels. If the circuits realized with low-voltage devices are operated at high voltage levels, the gate-oxide breakdown and leakage issues will occur. Therefore, for the CMOS integrated circuits (ICs) with the mixed-voltage I/O interfaces, the on-chip electrostatic discharge (ESD) protection circuits will meet more design constraints and difficulties. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths during normal circuit operating operation. During ESD stress condition, the on-chip ESD protection circuit should provide effective ESD protection for the internal circuits. In high-voltage CMOS technology, high-voltage transistors have been widely used for display driver ICs, power supplies, power management, and automotive electronics. The high-voltage MOSFET was often used as the ESD protection device in the high-voltage CMOS ICs, because it can work as both of output driver and ESD protection device simultaneously. With an ultra-high operating voltage, the ESD robustness of high-voltage MOSFET is quite weaker than that of low-voltage MOSFET. Hence, how to improve the ESD robustness of HV NMOS with a reasonable silicon area is indeed an important reliability issue in HV CMOS technology. In this thesis, some new ESD protection structures are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology. To protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS), ESD protection design with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed. The LVTPNP is realized by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device. The LVTPNP devices with different structures have been investigated and compared in CMOS processes. The experimental results in a 0.35-um CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-um and 0.25-um CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-um salicided CMOS process. To increase the system-on-chip ESD immunity of micro-electronic products against system-level ESD stress, the chip-level ESD/EMC protection design should be enhanced. Considering gate-oxide reliability, a new ESD protection scheme with ESD_BUS and high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed in this chapter. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage NMOS/PMOS devices which can be safely operated under the 2.5 V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (PS, NS, PD, and ND) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13 um CMOS process have confirmed that the proposed new ESD protection scheme has high human-body-model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low-voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces. To greatly improve ESD robustness of the vacuum-fluorescent-display (VFD) driver IC for automotive electronics applications, a new electrostatic discharge protection structure of high-voltage P-type silicon controlled rectifier (HVPSCR) embedded into the high-voltage PMOS device is proposed. By only adding the additional N+ diffusion into the drain region of high-voltage PMOS, the TLP-measured secondary breakdown current (It2) of output driver has been greatly improved greater than 6A in a 0.5-µm high-voltage CMOS process. Such ESD-enhanced VFD driver IC, which can sustain HBM ESD stress of up to 8kV, has been in mass production for automotive applications in car without latchup problem. Moreover, with device widths of 500um, 600um, and 800um, the MM ESD levels of the HVPSCR are as high as 1100V, 1300V, and 1900V, respectively. The dependences of drift implant and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in silicon chips. From the experimental results, the HV MOSFETs without drift implant in the drain region have better TLP-measured It2 and ESD robustness than those with drift implant in the drain region. Furthermore, the It2 and ESD level of HV MOSFETs can be increased as the layout spacing from the drain diffusion to polygate is increased. It was also demonstrated that a specific test structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the excellent TLP-measured It2 and ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the dependences of the TLP-measured It2 and HBM ESD levels on the spacing from the drain diffusion to polygate are different. In this thesis, the novel ESD protection circuits have been developed for mixed-voltage I/O interfaces and high-voltage CMOS process with high ESD robustness. Each of the ESD protection circuits has been successfully verified in the testchips.

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Lu, JainHao, and 盧建豪. "Novel four-phase high-voltage charge pumps for low-voltage operation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/85812133682021408335.

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碩士
國立中興大學
電機工程學系
91
For rapidly increasing requirements of portable equipments, the high-density storages using low-supply voltage have been heavily developed in recent years. For low-voltage Flash memories, the charge pump is an important element in the peripheral circuits. In this thesis, a charge pump design is proposed. It uses special substrate connection with triple well process and negative feedback loop regulating structure for nonvolatile memory. The basic principles of the charge pumps and its related issues are illustrated in this thesis. The challenge to design a low-supply voltage pumping circuit is to overcome the influence of the body effect and the threshold voltage, which reaches —0.94V in PMOS, when the pumping circuits are cascaded in many stages. Besides, the feedback regulator generating a stable pumping voltage was also designed. A test chip of the circuit was fabricated using 1P3M 0.6mm process. The simulation and the measurement show the new ten-stage charge pump can efficiently pump lower than —10V at supply voltage of 1.2V with 500pF loading capacitor.

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37

Tang, Kai-Neng, and 湯凱能. "Stacks of Low-Voltage Devices for ESD Protection in High-Voltage Applications." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/09343673113740855581.

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碩士
國立交通大學
電子工程學系電子研究所
103
Nowadays, many integrated circuits (ICs) of electrical products are fabricated in a high-voltage process. For example, driver ICs for various display panels, power management ICs and automotive ICs are commonly fabricated in a HV process. In a high-voltage process, HV transistors are born with complicated structure for the increase of the operating range and breakdown voltage, and that makes electrostatic discharge (ESD) protection design more difficult and challenging. In ESD protection design for HV applications, it is common to use lateral diffused MOS (LDMOS) as an ESD protection device. LDMOS is a general HV MOS, and its ESD robustness is worse than a low-voltage device’s. It has to enlarge LDMOS, and be aware of uniformity for ESD protection. In ESD protection design for HV applications, holding voltage of a device is an important factor. When holding voltage of a device is lower than supply voltage, it is possible that latchup occurs in applications. In some noisy environment, this factor should be paid more attention. Low-voltage devices are proved for good ESD robustness per area, and the devices can be enhanced by many methods. Stacking makes the devices’ trigger voltage and holding voltage increase so that the devices meet the conditions for HV applications. For area and ESD robustness concerns, stacking can be one of the best ways. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed for the problems and improvement. Stacked configuration in different shapes is also examined. Increasing turn-on speed by replacing with other devices will be discussed.

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38

Yu, Li-Chin, and 游力瑾. "High-Voltage Generator with Multi-Stage Selection in Low-Voltage CMOS Process." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/ce3g86.

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39

Wang, Wei-Juo, and 王偉州. "High Precision and Low Cost Voltage Metrology." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/27472350038495679912.

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碩士
國立中央大學
電機工程研究所
89
In recent years, the demand of mixed signal testing and fast development of system on chip technology are high due to the size of the chip grows larger and larger. However, faster and more complex test equipments are needed to meet the much demanding test specifications. Thus, test the chip precisely and efficiently becomes a difficult and more complicated task. In this thesis, we propose a new methodology to measure voltage precisely. The method is able to utilize the comparators in Pin Electronic ICs to exercise the measurement task. The proposed technique simplifies the DAC or LCD Driver IC measurement significantly. Here, we use the probability and statistic methods to analyze the proposed methodology. Experimental results using a demo circuit and a vendor PE card have verify and confirm the feasibility of the proposed methodology.

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40

Yeha, Yu-Kwang, and 葉昱崑. "Low-Voltage and High-Speed BiCMOS Multiplier." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/08000955059537268110.

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碩士
淡江大學
資訊工程研究所
83
Low voltage low power high speed integrated circuits are critical elements for portable electronic systems. In order to exploit this trend, in this thesis,a high-speed BiCMOS 16*16-bit multiplier with a supply voltage of 2.5V is proposed and ana- lyzed. Multiplication is one of the basic operation in digital sig- nal processing system, the speed of multiplication is critical of whole system's performance. The proposed low-voltage high- speed multiplier can be adopted to the design of high perfor- mance digital processing systems. Multiplication contains two basic operations:(a) partial-product generation and ;(b)partial- product addition. In order to improve the performance of the multiplier, modified Booth's algorithm and Wallace tree structure are used. The modified Booth's algorithm scheme can reduce the number of partial-product half per each multiplication. The Wa- llace- tree adder array and CLA adder are used to minimize the critical-delay-path gate stages. For high-speed and low- voltage requirement, the BiCMOS and CMOS circuits are used in this multiplier. The modified Booth's encoder and CLA are implemeted by the BiCMOS circuits for large capacitance loading. The Wallace addition tree and the Booth's decoder are implemented by the CMOS circuits for high packing density. The implementation of this chip is based upon the 1.0um DPDM BiCMOS process,which is provided by the Chip Implementation Center (CIC) of National Science Council(NSC) of the Republic of China. The procedures of design, simulation, layout,verification and testing consideration are included.

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41

Lin, Yu-Hsiang, and 林于翔. "A High-PSRR Low-Dropout Voltage Regulator." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/76281057373921718594.

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碩士
國立交通大學
電機學院電信學程
104
In recent years, mobile electronic products have become very popular in human life. One more key feature of the mobile electronic product is its power circuit. If the electronic product can be designed with a good power system, the quality of the product can be enhanced. This paper presents a high PSRR LDO regulator which uses a two-stage NMOS differential amplifier combined with a NMOS differential circuit and also chooses a high PSRR bandgap circuit for reference voltage. The circuit can achieve the PSRR lower than ≤ -60dBm and -50dBm during pre-simulation and post-simulation, respectively, which are better than the typical of regular LDOs. The chip presented in this thesis was fabricated by Taiwan Semiconductor Manufacturing Company （TSMC）0.35μm 2P4M 3.3V mixed‐signal CMOS process. The chip area is 0.8mm×0.767mm.

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42

Mining, Cheng Chi, and 鄭啟明. "The Effects of High Voltage Side Flicker Source on Low Voltage ide Customers." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/28811664175850960593.

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碩士
國立臺灣科技大學
電機工程研究所
82
This is a research on the voltage flicker resulted from electric arc furnace in the Tongishia primary substation area. The purposes are to (a) analyze the operation characteristics of electric arc furnace for the cause of voltage flicker (b) investigate the propagation of voltage flicker among different voltage feeders in that area, (c) discuss the posibble reasons of voltage flicker propagation attenuation, and (d) propose some feasible methods to reduce the voltage flicker level in that area. The statistic results of the measurement data at electric arc furnace transformers show that repeatedly transient overloads is the major reasons of severe voltage flicker in that area. Itdeduced that the electric arc furnace plants do not operate the furnace according to the primary review conditions. According to the statistics of measurement data, the voltage flickerperties from the 69kV equivent source through 69kV transmission lines to 110V customers. The voltage flicker level at the 11.4kV side of secondary substations attenuates to 80% of it original value, and that at 110V customers sides attenuates to 75% of it oginal value. From the simulations by EMTP, while nonlinear loads will cause attenuation of voltage flicker, linear loads and networks will not cause attenuation.

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43

Huang, Wei-Lin, and 黃威霖. "A High Efficiency CMOS DC-DC Switching Voltage Regulator for Low Voltage Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/59522187804192606403.

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碩士
國立成功大學
電機工程學系碩博士班
92
Abstract The design and implementation of a DC-DC buck switching regulator for low supply voltage electronic system is presented in this thesis. This switching regulator has low output ripple in steady state and fast transient response when the load is suddenly changed. It also has high power conversion efficiency that is suitable for portable electronic applications that are powered by batteries such as mobile phone, digital camera, PDA, etc. The switching regulator IC is designed with high operation frequency for reducing the output voltage ripple and the transient response recovery time. In addition, the feedback loop bandwidth is designed as wide as possible to achieve fast transient response. For making power conversion more efficient, the regulator is enhanced with two operation modes, PWM and PFM, for heavy and light load conditions. Another technique for increasing the power conversion efficiency is to design the buffer for driving the power MOSFET with the characteristics of anti-shoot through current and adaptive dead time control. This technique can prevent the occurrences of the shoot through current and reduce the body diode conduction time during switching transitions. To eliminate the excess large current at the start up of the regulator that may damage the devices of the power stage, the soft start operation is designed. This regulator IC is fabricated with TSMC 0.35um 2P4M 3.3V/5V Mixed Signal CMOS technology through CIC. The chip size is about 1.5×1.5 mm2. Other detailed performances will be described in the following chapters.

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44

Liao, Seian-Feng, and 廖顯峰. "Optimization of Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Layout Consideration." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/27130130262768377247.

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碩士
國立交通大學
電子工程學系電子研究所
104
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. ESD may occur accidentally during the fabrication, package, and assembling processes of IC products, which often caused serious damages on ICs. During normal circuit operation, the noise might unpredictably trigger the parasitic BJT of the ESD devices. Furthermore, to avoid latchup issue, the holding voltage (Vh) should be larger than the supply voltage of the internal circuits in ESD protection design for HV applications. Lateral DMOS (LDMOS) was often used as ESD protection device in HV process, but the holding voltage (Vh) of LDMOS after snapback was smaller than the circuit operating voltage (VCC). Thus, the LDMOS was sensitive to latchup issue. Therefore, the stacked configuration of LV devices is a way to achieve a high holding voltage for ESD protection in HV circuits. By adjusting the stacking numbers of stacked PMOSs, it can provide effective ESD protection for various HV applications. In this thesis, stacks for ESD protection are implemented and verified, and it is discussed about different layout parameters to effectively improve ESD robustness of ESD devices. The guard-ring layout on the stacked LV devices was further investigated holding voltage in silicon chip. In addition, the pulse width of the transmission line pulsing (TLP) system was also investigated holding voltage in silicon chip. Decreasing the layout area to get high ESD robustness and latchup-free immunity for HV applications.

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45

Chan, Ming-Hsien, and 詹明憲. "Design,Manufacture,Installation,Test and Maintenance Technologies for High voltage and Low voltage panels." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/69147663517280511448.

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碩士
中原大學
電機工程研究所
95
The power panels contain various equipments devices and associated assemblies for power control, operation and supervision; their qualities have significant effect on the safety and reliability of power supply. Power panel quality and its function are critical affected by the technologies of design, manufacturing, installation and maintenance tests. These technologies are surveyed, discussed and introduced in this report. For the design technologies, the related codes and standards, basic rules and methods are introduced including the computer aid design software package of panel design. For the manufacturing of panels, the material specifications, structures, coating and outer finishing and their processes techologies are discussed in this report. For the panel installation, the installation processes including suspension transportation, trunk openning, mounting, fixing and other associated processes are introduced. As to the maintenance tests, the contents of each test item and their complied standards are illustrated, and the test methods and some important maintenance works are discussed. Finally, in addition to local national standard, some international standards such as the standards issued by American National Standard Institute (ANSI) and International Electrical Commission (IEC) of European Union about high and low voltage panel are presented and comparisons of the panel products between Taiwan and China are introduced also.

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46

Tzuhsuan, Peng, and 彭子軒. "A Low Jitter High Linearity Voltage Controlled Oscillator." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/86239292001038107094.

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碩士
國立中山大學
電機工程學系研究所
92
Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system. We propose a low jitter voltage controlled oscillator designed in TSMC 0.35μm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.

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47

Lan, Jian-Jia, and 藍健嘉. "Two Low Jitter, High Linearity Voltage-Controlled Oscillators." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/67545856798165733161.

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碩士
國立中山大學
電機工程學系研究所
93
Voltage-controlled oscillators are widely used circle blocks, particularly in phase- locked loops. As CMOS is the technology of choice for many applications, CMOS oscillators with low timing jitter are highly desired. In this thesis, two types of VCO based on differential ring oscillator and relaxation oscillator are proposed. We describes the effect of supply noise on the performance of differential ring and relaxation oscillators. Compared to the conventional VCO, the proposed VCOs have lower sensitivity to noise on the power supply and also provided a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability. Both of VCOs are designed in TSMC 0.35μm 2P4M Mixed-Signal process technology.

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48

Chiang, Chih-Chyuang, and 姜智荃. "Low Voltage and High Speed NAND-type ROM." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/97296562161036497079.

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碩士
國立清華大學
電機工程學系
98
Read-only memory(ROM) is a non-volatile memory which is commonly used in embedded system for large fix information storage and system program storage. ROM include NOR-type and NAND-type. NAND-type ROM is used for lower speed application due to high density but lower operation frequency. When process technology scaling to nanometer, low voltage and high speed deisgn become a main goal. Since NAND-type ROM has higher reliability in low voltage compare with NOR-type ROM, a low voltage and high speed NAND-type ROM is necessary. Code-dependent cell current, charge sharing between bitline(BL) and NAND string, crosstalk and BL leakage in NAND-type ROM limit the operation frequency and minimum operation voltage(VDDmin). Previous studies have proposed some methods to solve these issues. We proposed a code-inversion scheme to solve the problem of small read current in NAND-type ROM. Operation frequency and minimum operation voltage is improved due to increase the on-off current ratio. To achieve low voltage design and high operation range, dynamic split sourceline scheme [1] is used in our design to reduce charge sharing, crosstalk and bitline leakage. BL tracking scheme [2] is used in our design for timing control. A 256kb NAND-type ROM macros is implement in 90nmCMOS technology, which can operate from 1V to 0.26V, improving 25% operation frequency. The measurement result shows the propose scheme has 9MHz operation speed at 0.3V.

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49

FAN, YAU-JIA, and 樊曜嘉. "High Speed and Low Voltage CMOS PLA Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/76737299018366542320.

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碩士
國立中正大學
電機工程研究所
90
The tendency of SOC is to increase complication of logic control unit, and the requests of the design to speed and power are comparatively higher than before, too. Traditional PLA architecture isn’t desirable on speed and power dissipation. Despite the newest dynamic PLA architecture could enhance efficiently operation speed and reduce power consumption, our research is going to point out heavy loading still forces to make serious degradation of operation speed as applying to high-capacity PLA. This thesis firstly uses function division technology to post modified-second-order PLA architecture, applying to 32 bits CPU’s control unit with being implemented with 0.18um 1P6M technique. After post layout simulation, compare with standard cell design, the modified-second-order PLA architecture could promote 2 times operation speed, but reduce 70% chip area. On the other hand, with the spread of portable device, a lot of VLSI adopt low voltage to reach the demand of low power. Our research further focus on modified-second-order-high —capacity PLA architecture, and propose an novel circuit design suitable to low voltage (0.9V) with high efficient Standby Control scheme and to Data retention. In order to prove the reliability of proposed design technology, we similarly design 32bits CPU’s control unit with being implemented TSMC 0.25um 1P5M technique. The number of transistor is 98065. After post layout simulation, the power dissipation is going to be 9mW as the voltage is 0.9V and the operation frequency is 100MHz.

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50

Chen, Yung-Chih, and 陳勇志. "Low Voltage and High Speed Embedded SRAM Design." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66868532767171516589.

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Dissertations / Theses on the topic 'High voltage/low voltage redundancy'

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