Relevant bibliographies by topics / HW/SW partitioning

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'HW/SW partitioning'

Author: Grafiati
Published: 4 June 2021
Last updated: 19 February 2022

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Journal articles on the topic "HW/SW partitioning"

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Lin, Geng, Wenxing Zhu, and M. Montaz Ali. "A Tabu Search-Based Memetic Algorithm for Hardware/Software Partitioning." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/103059.

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Hardware/software (HW/SW) partitioning is to determine which components of a system are implemented on hardware and which ones on software. It is one of the most important steps in the design of embedded systems. The HW/SW partitioning problem is an NP-hard constrained binary optimization problem. In this paper, we propose a tabu search-based memetic algorithm to solve the HW/SW partitioning problem. First, we convert the constrained binary HW/SW problem into an unconstrained binary problem using an adaptive penalty function that has no parameters in it. A memetic algorithm is then suggested for solving this unconstrained problem. The algorithm uses a tabu search as its local search procedure. This tabu search has a special feature with respect to solution generation, and it uses a feedback mechanism for updating the tabu tenure. In addition, the algorithm integrates a path relinking procedure for exploitation of newly found solutions. Computational results are presented using a number of test instances from the literature. The algorithm proves its robustness when its results are compared with those of two other algorithms. The effectiveness of the proposed parameter-free adaptive penalty function is also shown.
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Yan, Xiaohu, Fazhi He, Neng Hou, and Haojun Ai. "An Efficient Particle Swarm Optimization for Large-Scale Hardware/Software Co-Design System." International Journal of Cooperative Information Systems 27, no. 01 (March 2018): 1741001. http://dx.doi.org/10.1142/s0218843017410015.

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In the co-design process of hardware/software (HW/SW) system, especially for large and complicated embedded systems, HW/SW partitioning is a challenging step. Among different heuristic approaches, particle swarm optimization (PSO) has the advantages of simple implementation and computational efficiency, which is suitable for solving large-scale problems. This paper presents a conformity particle swarm optimization with fireworks explosion operation (CPSO-FEO) to solve large-scale HW/SW partitioning. First, the proposed CPSO algorithm simulates the conformist mentality from biology research. The CPSO particles with psychological conformist always try to move toward a secure point and avoid being attacked by natural enemy. In this way, there is a greater possibility to increase population diversity and avoid local optimum in CPSO. Next, to enhance the search accuracy and solution quality, an improved FEO with new initialization strategy is presented and is combined with CPSO algorithm to search a better position for the global best position. This combination can keep both the diversified and intensified searching. At last, the experiments on benchmarks and large-scale HW/SW partitioning demonstrate the efficiency of the proposed algorithm.
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Soininen, Juha-Pekka, Matti Sipola, and Kari Tiensyrjä. "SW/HW-partitioning of real-time embedded systems." Microprocessing and Microprogramming 27, no. 1-5 (August 1989): 239–44. http://dx.doi.org/10.1016/0165-6074(89)90053-7.

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LU, Xiao-zhang, Wei LIU, and Yao-dong TAO. "Method of HW/SW partitioning based on NSGA-II." Journal of Computer Applications 29, no. 1 (June 25, 2009): 238–41. http://dx.doi.org/10.3724/sp.j.1087.2009.238.

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Iguider, Adil, Kaouthar Bousselam, Oussama Elissati, Mouhcine Chami, and Abdeslam En-Nouaary. "GO Game Inspired Algorithm for Hardware Software Partitioning in Multiprocessor Embedded Systems." Computer and Information Science 12, no. 4 (November 22, 2019): 111. http://dx.doi.org/10.5539/cis.v12n4p111.

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The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.
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Fuhr, Gereon, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, and Juan Fernando Eusse. "Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs." IEEE Embedded Systems Letters 11, no. 3 (September 2019): 93–96. http://dx.doi.org/10.1109/les.2019.2901224.

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Jia, Huizhu, Peng Zhang, Don Xie, and Wen Gao. "An AVS HDTV video decoder architecture employing efficient HW/SW partitioning." IEEE Transactions on Consumer Electronics 52, no. 4 (November 2006): 1447–53. http://dx.doi.org/10.1109/tce.2006.273169.

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Tmar, H., J. Ph Diguet, A. Azzedine, M. Abid, and J. L. Philippe. "RTDT: A static QoS manager, RT scheduling, HW/SW partitioning CAD tool." Microelectronics Journal 37, no. 11 (November 2006): 1208–19. http://dx.doi.org/10.1016/j.mejo.2006.07.028.

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Tang, Qi, Biao Guo, and Zhe Wang. "Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-Chip." Electronics 9, no. 9 (August 21, 2020): 1362. http://dx.doi.org/10.3390/electronics9091362.

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A heterogeneous system-on-chip (SoC) integrates multiple types of processors on the same chip. It has great advantages in many aspects, such as processing capacity, size, weight, cost, power, and energy consumption, which result in it being widely adopted in many fields. The SoC based on region-based dynamic partial reconfigurable (DPR) FPGA plays an important role in the SoC field. However, delivering its powerful capacity to the consumer depends on the efficient Sw/Hw partitioning and scheduling technology that determines the resource volume of the DPR region, the mapping of the application to the DPR region and other processors, and the schedule of the task and its reconfiguration. This paper first proposes an exact approach based on the mixed integer linear programming (MILP) for the Sw/Hw partitioning and scheduling problem. The proposed MILP is able to solve the problem optimally; however, its scalability is poor, despite that we carefully designed its formulation and tried to make it as concise as possible. Therefore, a multi-step hybrid method that combines graph partitioning and MILP is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. A set of experiments is carried out using a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.
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Shi, Wenjun, Jigang Wu, Guiyuan Jiang, and Siew-kei Lam. "Multiple-Choice Hardware/Software Partitioning for Tree Task-Graph on MPSoC." Computer Journal 63, no. 5 (February 23, 2019): 688–700. http://dx.doi.org/10.1093/comjnl/bxy140.

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Abstract Hardware/software (HW/SW) partitioning, that decides which components of an application are implemented in hardware and which ones in software, is a crucial step in embedded system design. On modern heterogeneous embedded system platform, each component of application can typically have multiple feasible configurations/implementations, trading off quality aspects (e.g. energy consumption, completion time) with usage for various types of resources. This provides new opportunities for further improving the overall system performance, but few works explore the potential opportunity by incorporating the multiple choices of hardware implementation in the partitioning process. This paper proposes three algorithms for multiple-choice HW/SW partitioning of tree-shape task graph on multiple processors system on chip (MPSoC) with the objective of minimizing execution time, while meeting area constraint. Firstly, an efficient heuristic algorithm is proposed to rapidly generate an approximate solution. The obtained solution produced by the first algorithm is then further refined by a customized Tabu search algorithm. We also propose a dynamic programming algorithm to calculate the exact solutions for relatively smaller scale instances. Simulation results show that the proposed heuristic algorithm is able to quickly generate good approximate solutions, and the solutions become very close to the exact solutions after refined by the proposed Tabu search algorithm, in comparison to the exact solutions produced by the dynamic programming algorithm.
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Dissertations / Theses on the topic "HW/SW partitioning"

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Bjärmark, Joakim, and Marco Strandberg. "Hardware Accelerator for Duo-binary CTC decoding : Algorithm Selection, HW/SW Partitioning and FPGA Implementation." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7902.

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Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device.

Duo-binary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVB-RSC. This report describes the development of a duo-binary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design.

An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a reference-model has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bit-true reference for the hardware verification.

The final result is a duo-binary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.

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Tiejun, Hu Di Wu. "Design of Single Scalar DSP based H.264/AVC Decoder." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2812.

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H.264/AVC is a new video compression standard designed for future broadband network. Compared with former video coding standards such as MPEG-2 and MPEG-4 part 2, it saves up to 40% in bit rate and provides important characteristics such as error resilience, stream switching etc. However, the improvement in performance also introduces increase in computational complexity, which requires more powerful hardware. At the same time, there are several image and video coding standards currently used such as JPEG and MPEG-4. Although ASIC design meets the performance requirement, it lacks flexibility for heterogeneous standards. Hence reconfigurable DSP processor is more suitable for media processing since it provides both real-time performance and flexibility.

Currently there are several single scalar DSP processors in the market. Compare to media processor, which is generally SIMD or VLIW, single scalar DSP is cheaper and has smaller area while its performance for video processing is limited. In this paper, a method to promote the performance of single scalar DSP by attaching hardware accelerators is proposed. And the bottleneck for performance promotion is investigated and the upper limit of acceleration of a certain single scalar DSP for H.264/AVC decoding is presented.

Behavioral model of H.264/AVC decoder is realized in pure software during the first step. Although real-time performance cannot be achieved with pure software implementation, computational complexity of different parts is investigated and the critical path in decoding was exposed by analyzing the first design of this software solution. Then both functional acceleration and addressing acceleration were investigated and designed to achieve the performance for real-time decoding using available clock frequency within 200MHz.

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Nilsson, Per. "Hardware / Software co-design for JPEG2000." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.

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For demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.

This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.

First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.

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Andersson, Mikael, and Per Karlström. "Parallel JPEG Processing with a Hardware Accelerated DSP Processor." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615.

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This thesis describes the design of fast JPEG processing accelerators for a DSP processor.

Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed.

First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog.

Extension of the accelerator instructions was given following a custom design flow.

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Kandasamy, Santheeban. "Dynamic HW/SW Partitioning: Configuration Scheduling and Design Space Exploration." Thesis, 2007. http://hdl.handle.net/10012/3042.

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Hardware/software partitioning is a process that occurs frequently in embedded system design. It is the procedure of determining whether a part of a system should be implemented in software or hardware. This dissertation is a study of hardware/software partitioning and the use of scheduling algorithms to improve the performance of dynamically reconfigurable computing devices. Reconfigurable computing devices are devices that are adaptable at the logic level to solve specific problems [Tes05]. One example of a reconfigurable computing device is the field programmable gate array (FPGA). The emergence of dynamically reconfigurable FPGAs made it possible to configure FPGAs at runtime. Most current approaches use a simple on demand configuration scheduling algorithm for the FPGA configurations. The on demand configuration scheduling algorithm reconfigures the FPGA at runtime, whenever a configuration is needed and is found not to be configured. The problem with this approach of dynamic reconfiguration is the reconfiguration time overhead, which is the time it takes to reconfigure the FPGA with a new configuration at runtime. Configuration caches and partial configuration have been proposed as possible solutions to this problem, but these techniques suffer from various limitations. The emergence of dynamically reconfigurable FPGAs also made it possible to perform dynamic hardware/software partitioning (DHSP), which is the procedure of determining at runtime whether a computation should be performed using its software or hardware implementation. The drawback of performing DHSP using configurations that are generated at runtime is that the profiling and the dynamic generation of configurations require profiling tool and synthesis tool access at runtime. This study proposes that configuration scheduling algorithms, which perform DHSP using statically generated configurations, can be developed to combine the advantages and reduce the major disadvantages of current approaches. A case study is used to compare and evaluate the tradeoffs between the currently existing approach for dynamic reconfiguration and the DHSP configuration scheduling algorithm based approach proposed in the study. A simulation model is developed to examine the performance of the various configuration scheduling algorithms. First, the difference in the execution time between the different approaches is analyzed. Afterwards, other important design criteria such as power consumption, energy consumption, area requirements and unit cost are analyzed and estimated. Also, business and marketing considerations such as time to market and development cost are considered. The study illustrates how different types of DHSP configuration scheduling algorithms can be implemented and how their performance can be evaluated using a variety of software applications. It is also shown how to evaluate when which of the approaches would be more advantageous by determining the tradeoffs that exist between them. Also the underlying factors that affect when which design alternative is more advantageous are determined and analyzed. The study shows that configuration scheduling algorithms, which perform DHSP using statically generated configurations, can be developed to combine the advantages and reduce some major disadvantages of current approaches. It is shown that there are situations where DHSP configuration scheduling algorithms can be more advantageous than the other approaches.
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Chen, Chin-Yang, and 陳金洋. "HW/SW Partitioning and Pipelined Scheduling Using Integer Linear Programming." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/13997876798330032318.

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碩士
國立中山大學
資訊工程學系研究所
93
The primary design goal of many embedded systems for multimedia applications is usually meeting the performance requirement at a minimum cost. In this thesis, we proposed two different ILP based approaches for hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. One ILP approach solves the HW/SW partitioning and pipelined scheduling problem simultaneously. Another ILP approach separates the HW/SW partitioning and pipelined scheduling problem into two phases. The first phase is focusing on the HW/SW partitioning and mapping problem. Second phase is used to solve the pipelined scheduling problem. The two ILP approaches not only partition and map each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. For the first ILP model, the objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint. In the second ILP approach, the objective of the first phase and second phase is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint, respectively. Finally, experiments on three real multimedia applications (JPEG Encoder, MP3 Decoder, Wavelet Video Encoder) are used to demonstrate the effectiveness of the proposed approaches.
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Lin, Lan-Hsin, and 林藍芯. "A Novel Approach of HW/SW Partitioning for Embedded Multiprocessor Systems." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/17996773602461302920.

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碩士
國立中正大學
資訊工程研究所
92
To speed the time-to-market cycle, the codesign of hardware and software has become one of the kernel technologies in modern embedded systems. To achieve this objective, we must develop the hardware and software concurrently and begin the software design targeting at the “virtual hardware platforms” before the hardware platform is available. This can lead to the better system design and reduce the risks that arise from the rapid changes of system specifications. An incorrect HW/SW-partitioning will result in time-consuming design and expensive optimizations of the whole system. Therefore, how to partition the system into hardware and software parts has become one of the critical issues in system level. This paper presents a novel HW/SW-partitioning approach, which targets at embedded systems consisting of multiprocessor for time, area, and power constraints. Our approach is two-fold: partitioning phase and scheduling phase. In the partitioning phase, for an embedded system with n processors, recursive spectral bisection (RSB) has been used to partition an application program into n blocks and then these blocks are mapped into software components. We try to move tasks from software components to hardware components in order to meet the deadline constraint. In the scheduling phase, we derive an approach to adapt the load in each processor by exchanging tasks between hardware and software components not only to meet the deadline constraint of the system but also to reduce the cost of the system. Finally, we conclude this paper and describe the work we will continue in the near future.
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Juliato, Marcio. "Fault Tolerant Cryptographic Primitives for Space Applications." Thesis, 2011. http://hdl.handle.net/10012/5876.

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Spacecrafts are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, there has been an increasing demand to utilize strong cryptographic primitives to assure their security. Moreover, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. The problem of recovering spacecrafts from failures or attacks, and bringing them back to an operational and safe state is crucial for reliability. Despite the recent interest in incorporating on-board security, there is limited research in this area. This research proposes a trusted hardware module approach for recovering the spacecrafts subsystems and their cryptographic capabilities after an attack or a major failure has happened. The proposed fault tolerant trusted modules are capable of performing platform restoration as well as recovering the cryptographic capabilities of the spacecraft. This research also proposes efficient fault tolerant architectures for the secure hash (SHA-2) and message authentication code (HMAC) algorithms. The proposed architectures are the first in the literature to detect and correct errors by using Hamming codes to protect the main registers. Furthermore, a quantitative analysis of the probability of failure of the proposed fault tolerance mechanisms is introduced. Based upon an extensive set of experimental results along with probability of failure analysis, it was possible to show that the proposed fault tolerant scheme based on information redundancy leads to a better implementation and provides better SEU resistance than the traditional Triple Modular Redundancy (TMR). The fault tolerant cryptographic primitives introduced in this research are of crucial importance for the implementation of on-board security in spacecrafts.
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Book chapters on the topic "HW/SW partitioning"

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Ray, Abhijit, Wu Jigang, and Srikanthan Thambipillai. "Knapsack Model and Algorithm for HW/SW Partitioning Problem." In Computational Science - ICCS 2004, 200–205. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-24685-5_25.

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Iguider, Adil, Mouhcine Chami, Oussama Elissati, and Abdeslam En-Nouaary. "Embedded Systems HW/SW Partitioning Based on Lagrangian Relaxation Method." In Innovations in Smart Cities and Applications, 149–60. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-74500-8_14.

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Pu, Geguang, Zhang Chong, Zongyan Qiu, Zuoquan Lin, and He Jifeng. "A Hybrid Heuristic Algorithm for HW-SW Partitioning Within Timed Automata." In Lecture Notes in Computer Science, 459–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11892960_56.

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Wu, Yue, Hao Zhang, and Hongbin Yang. "Research on Parallel HW/SW Partitioning Based on Hybrid PSO Algorithm." In Algorithms and Architectures for Parallel Processing, 449–59. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03095-6_43.

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Prevostini, Mauro, Francesco Balzarini, Atanas Nikolov Kostadinov, Srinivas Mankan, Aris Martinola, and Antonio Minosi. "UML-Based Specifications of an Embedded System Oriented to HW/SW Partitioning." In Languages for System Specification, 71–84. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/1-4020-7991-5_5.

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Kastrup, Bernardo, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, and Jef van Meerbergen. "Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis." In Lecture Notes in Computer Science, 695–706. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_74.

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"Fundamentals and HW/SW Partitioning." In Image Processing for Embedded Devices, edited by S. Battiato, G. Puglisi, A. Bruna, A. Capra, and M. Guarnera, 1–9. BENTHAM SCIENCE PUBLISHERS, 2012. http://dx.doi.org/10.2174/978160805170011001010001.

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B., M., and S. E. D. Habib. "Particle Swarm Optimization for HW/SW Partitioning." In Particle Swarm Optimization. InTech, 2009. http://dx.doi.org/10.5772/6740.

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Conference papers on the topic "HW/SW partitioning"

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Hardt, W. "An automated approach to HW/SW-codesign." In IEE Colloquium on Partitioning in Hardware-Software Codesigns. IEE, 1995. http://dx.doi.org/10.1049/ic:19950170.

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Farmahini-Farahani, Amin, Mehdi Kamal, Sied Mehdi Fakhraie, and Saeed Safari. "HW/SW partitioning using discrete particle swarm." In the 17th great lakes symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1228784.1228870.

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Halimic, Mirsad, and Aida Halimic. "Vendor supplied development environments based HW/SW partitioning." In Exhibition, "Innovative Engineering for Sustainable Environment". IEEE, 2009. http://dx.doi.org/10.1109/ieeegcc.2009.5734248.

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Chehida, K. Ben, and M. Auguin. "HW / SW partitioning approach for reconfigurable system design." In the international conference. New York, New York, USA: ACM Press, 2002. http://dx.doi.org/10.1145/581630.581670.

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Banerjee, Sudarshan, and Nikil Dutt. "Efficient search space exploration for HW-SW partitioning." In the 2nd IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1016720.1016752.

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Henkel, Jouml;rg, and Yanbing Li. "Energy-conscious HW/SW-partitioning of embedded systems." In the sixth international workshop. New York, New York, USA: ACM Press, 1998. http://dx.doi.org/10.1145/278241.278292.

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Wei Liu and Xuejie Wang. "An AVS VLD architecture based on HW/SW partitioning." In 2011 International Conference on Transportation and Mechanical & Electrical Engineering (TMEE). IEEE, 2011. http://dx.doi.org/10.1109/tmee.2011.6199481.

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Weiss, Shlomo, and Shay Beren. "HW/SW partitioning of an embedded instruction memory decompressor." In the ninth international symposium. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/371636.371668.

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Han, Honglei, Liu Wenju, Wu Jigang, and Li Hui. "Framework for HW/SW partitioning and scheduling on MPSoCs." In 2010 International Conference on Computer and Information Application (ICCIA). IEEE, 2010. http://dx.doi.org/10.1109/iccia.2010.6141566.

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Li, Letitia W., Florian Lugou, and Ludovic Apvrille. "Security-aware Modeling and Analysis for HW/SW Partitioning." In 5th International Conference on Model-Driven Engineering and Software Development. SCITEPRESS - Science and Technology Publications, 2017. http://dx.doi.org/10.5220/0006119603020311.

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