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Journal articles on the topic 'HW/SW partitioning'

Author: Grafiati

Published: 4 June 2021

Last updated: 19 February 2022

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1

Lin, Geng, Wenxing Zhu, and M. Montaz Ali. "A Tabu Search-Based Memetic Algorithm for Hardware/Software Partitioning." Mathematical Problems in Engineering 2014 (2014): 1–15. http://dx.doi.org/10.1155/2014/103059.

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Hardware/software (HW/SW) partitioning is to determine which components of a system are implemented on hardware and which ones on software. It is one of the most important steps in the design of embedded systems. The HW/SW partitioning problem is an NP-hard constrained binary optimization problem. In this paper, we propose a tabu search-based memetic algorithm to solve the HW/SW partitioning problem. First, we convert the constrained binary HW/SW problem into an unconstrained binary problem using an adaptive penalty function that has no parameters in it. A memetic algorithm is then suggested for solving this unconstrained problem. The algorithm uses a tabu search as its local search procedure. This tabu search has a special feature with respect to solution generation, and it uses a feedback mechanism for updating the tabu tenure. In addition, the algorithm integrates a path relinking procedure for exploitation of newly found solutions. Computational results are presented using a number of test instances from the literature. The algorithm proves its robustness when its results are compared with those of two other algorithms. The effectiveness of the proposed parameter-free adaptive penalty function is also shown.

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2

Yan, Xiaohu, Fazhi He, Neng Hou, and Haojun Ai. "An Efficient Particle Swarm Optimization for Large-Scale Hardware/Software Co-Design System." International Journal of Cooperative Information Systems 27, no. 01 (March 2018): 1741001. http://dx.doi.org/10.1142/s0218843017410015.

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In the co-design process of hardware/software (HW/SW) system, especially for large and complicated embedded systems, HW/SW partitioning is a challenging step. Among different heuristic approaches, particle swarm optimization (PSO) has the advantages of simple implementation and computational efficiency, which is suitable for solving large-scale problems. This paper presents a conformity particle swarm optimization with fireworks explosion operation (CPSO-FEO) to solve large-scale HW/SW partitioning. First, the proposed CPSO algorithm simulates the conformist mentality from biology research. The CPSO particles with psychological conformist always try to move toward a secure point and avoid being attacked by natural enemy. In this way, there is a greater possibility to increase population diversity and avoid local optimum in CPSO. Next, to enhance the search accuracy and solution quality, an improved FEO with new initialization strategy is presented and is combined with CPSO algorithm to search a better position for the global best position. This combination can keep both the diversified and intensified searching. At last, the experiments on benchmarks and large-scale HW/SW partitioning demonstrate the efficiency of the proposed algorithm.

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3

Soininen, Juha-Pekka, Matti Sipola, and Kari Tiensyrjä. "SW/HW-partitioning of real-time embedded systems." Microprocessing and Microprogramming 27, no. 1-5 (August 1989): 239–44. http://dx.doi.org/10.1016/0165-6074(89)90053-7.

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4

LU, Xiao-zhang, Wei LIU, and Yao-dong TAO. "Method of HW/SW partitioning based on NSGA-II." Journal of Computer Applications 29, no. 1 (June 25, 2009): 238–41. http://dx.doi.org/10.3724/sp.j.1087.2009.238.

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5

Iguider, Adil, Kaouthar Bousselam, Oussama Elissati, Mouhcine Chami, and Abdeslam En-Nouaary. "GO Game Inspired Algorithm for Hardware Software Partitioning in Multiprocessor Embedded Systems." Computer and Information Science 12, no. 4 (November 22, 2019): 111. http://dx.doi.org/10.5539/cis.v12n4p111.

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The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.

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6

Fuhr, Gereon, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, and Juan Fernando Eusse. "Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs." IEEE Embedded Systems Letters 11, no. 3 (September 2019): 93–96. http://dx.doi.org/10.1109/les.2019.2901224.

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7

Jia, Huizhu, Peng Zhang, Don Xie, and Wen Gao. "An AVS HDTV video decoder architecture employing efficient HW/SW partitioning." IEEE Transactions on Consumer Electronics 52, no. 4 (November 2006): 1447–53. http://dx.doi.org/10.1109/tce.2006.273169.

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8

Tmar, H., J. Ph Diguet, A. Azzedine, M. Abid, and J. L. Philippe. "RTDT: A static QoS manager, RT scheduling, HW/SW partitioning CAD tool." Microelectronics Journal 37, no. 11 (November 2006): 1208–19. http://dx.doi.org/10.1016/j.mejo.2006.07.028.

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9

Tang, Qi, Biao Guo, and Zhe Wang. "Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-Chip." Electronics 9, no. 9 (August 21, 2020): 1362. http://dx.doi.org/10.3390/electronics9091362.

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A heterogeneous system-on-chip (SoC) integrates multiple types of processors on the same chip. It has great advantages in many aspects, such as processing capacity, size, weight, cost, power, and energy consumption, which result in it being widely adopted in many fields. The SoC based on region-based dynamic partial reconfigurable (DPR) FPGA plays an important role in the SoC field. However, delivering its powerful capacity to the consumer depends on the efficient Sw/Hw partitioning and scheduling technology that determines the resource volume of the DPR region, the mapping of the application to the DPR region and other processors, and the schedule of the task and its reconfiguration. This paper first proposes an exact approach based on the mixed integer linear programming (MILP) for the Sw/Hw partitioning and scheduling problem. The proposed MILP is able to solve the problem optimally; however, its scalability is poor, despite that we carefully designed its formulation and tried to make it as concise as possible. Therefore, a multi-step hybrid method that combines graph partitioning and MILP is proposed, which is able to reduce the time complexity significantly with the solution quality being degraded marginally. A set of experiments is carried out using a set of real-life applications, and the result demonstrates the effectiveness of the proposed methods.

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10

Shi, Wenjun, Jigang Wu, Guiyuan Jiang, and Siew-kei Lam. "Multiple-Choice Hardware/Software Partitioning for Tree Task-Graph on MPSoC." Computer Journal 63, no. 5 (February 23, 2019): 688–700. http://dx.doi.org/10.1093/comjnl/bxy140.

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Abstract Hardware/software (HW/SW) partitioning, that decides which components of an application are implemented in hardware and which ones in software, is a crucial step in embedded system design. On modern heterogeneous embedded system platform, each component of application can typically have multiple feasible configurations/implementations, trading off quality aspects (e.g. energy consumption, completion time) with usage for various types of resources. This provides new opportunities for further improving the overall system performance, but few works explore the potential opportunity by incorporating the multiple choices of hardware implementation in the partitioning process. This paper proposes three algorithms for multiple-choice HW/SW partitioning of tree-shape task graph on multiple processors system on chip (MPSoC) with the objective of minimizing execution time, while meeting area constraint. Firstly, an efficient heuristic algorithm is proposed to rapidly generate an approximate solution. The obtained solution produced by the first algorithm is then further refined by a customized Tabu search algorithm. We also propose a dynamic programming algorithm to calculate the exact solutions for relatively smaller scale instances. Simulation results show that the proposed heuristic algorithm is able to quickly generate good approximate solutions, and the solutions become very close to the exact solutions after refined by the proposed Tabu search algorithm, in comparison to the exact solutions produced by the dynamic programming algorithm.

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11

Banerjee, Sudarshan, Elaheh Bozorgzadeh, and Nikil D. Dutt. "Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 11 (November 2006): 1189–202. http://dx.doi.org/10.1109/tvlsi.2006.886411.

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12

Quinn, Heather, Miriam Leeser, and Laurie Smith King. "Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems." Journal of Real-Time Image Processing 2, no. 4 (November 6, 2007): 179–90. http://dx.doi.org/10.1007/s11554-007-0050-0.

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13

Adeluyi, Olufemi, and Jeong-A. Lee. "CHARMS: A Mapping Heuristic to Explore an Optimal Partitioning in HW/SW Co-Design." Journal of the Korea Society of Computer and Information 15, no. 9 (September 30, 2010): 1–8. http://dx.doi.org/10.9708/jksci.2010.15.9.001.

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14

Ben Haj Hassine, Siwar, Mehdi Jemai, and Bouraoui Ouni. "Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System." Journal of Optimization 2017 (2017): 1–11. http://dx.doi.org/10.1155/2017/8624021.

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Shortening the marketing cycle of the product and accelerating its development efficiency have become a vital concern in the field of embedded system design. Therefore, hardware/software partitioning has become one of the mainstream technologies of embedded system development since it affects the overall system performance. Given today’s largest requirement for great efficiency necessarily accompanied by high speed, our new algorithm presents the best version that can meet such unpreceded levels. In fact, we describe in this paper an algorithm that is based on HW/SW partitioning which aims to find the best tradeoff between power and latency of a system taking into consideration the dark silicon problem. Moreover, it has been tested and has shown its efficiency compared to other existing heuristic well-known algorithms which are Simulated Annealing, Tabu search, and Genetic algorithms.

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15

Liu, LeiBo, YingJie Chen, ShouYi Yin, Li Zhou, Hang Yuan, and ShaoJun Wei. "Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system." Science China Information Sciences 57, no. 8 (July 16, 2014): 1–14. http://dx.doi.org/10.1007/s11432-013-4979-2.

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16

Guo, Zhongfu, Xingming Zhang, and Bo Zhao. "A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW/SW Partitioning on Reconfigurable MPSoCs." IEEE Access 7 (2019): 112448–58. http://dx.doi.org/10.1109/access.2019.2934390.

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17

Hou, Neng, Fazhi He, Yi Zhou, Yilin Chen, and Xiaohu Yan. "A Parallel Genetic Algorithm With Dispersion Correction for HW/SW Partitioning on Multi-Core CPU and Many-Core GPU." IEEE Access 6 (2018): 883–98. http://dx.doi.org/10.1109/access.2017.2776295.

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18

Boudour, R., and M. T. Laskri. "Outil de partitionnement hw/sw basé sur l’algorithme Kernighan/Lin amélioré." Revue Africaine de la Recherche en Informatique et Mathématiques Appliquées Volume 7, 2007 (November 26, 2007). http://dx.doi.org/10.46298/arima.1882.

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International audience Partitioning of system functionality for implementation among multiple system components, such as among hardware and software components in codesign, is becoming an increasingly important topic. Various heuristics are used in automatic partitioning. In this paper, we present our tool, called AutoDec, implemented in Visual C++ 6.0. We verified that hierarchical clustering algorithm, based on closeness metrics, can be used to merge pieces of functionality before applying Kernighan/Lin algorithm, resulting in reduced execution time with often improvements in quality. In addition, we show that our approach, when used in partitioning, fills the gap between fast algorithms and highly-optimizing ones. Le partitionnement fonctionnel d’un système, en composants matériels et logiciels, acquiert de plus en plus de l’importance en conception conjointe. Plusieurs heuristiques et algorithmes sont utilisés en partitionnement. Dans ce papier, nous présentons l'outil, appelé AutoDec, implémenté en Visual C++ 6.0. Nous vérifions que l’algorithme hierarchical clustering, basé sur des métriques de rapprochement, peut être utilisé pour fusionner des parties fonctionnelles avant l’application de l’algorithme Kernihgan/Lin, entraînant ainsi une réduction notable du temps d’exécution avec souvent une amélioration accrue en qualité. En somme, nous montrons que notre approche, utilisée en partitionnement, permet de réduire le fossé entre les algorithmes rapides et hautement optimaux

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19

Khadidja, Yahyaoui. "PARTITIONING AND SCHEDULING RESOLUTION PROBLEMS BY BEES MATING STRATEGY IN DRES’ SYSTEMS." International Journal of Computing, June 30, 2017, 97–105. http://dx.doi.org/10.47839/ijc.16.2.886.

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In last years, several approaches have been proposed for solving the Hardware/Software partitioning and scheduling problem in dynamically reconfigurable embedded systems (DRESs), directed by metaheuristic algorithms. Honey Bees Mating Optimization (HBMO) algorithm is one of these advanced methods. It is a nature inspired algorithm which simulates the process of real honey-bees mating. In this work, we propose a variant of the Honey-bee Mating Optimization Algorithm for solving Hardware/software (HW/SW) partitioning and scheduling problems in DRESs. The algorithm is used in a hybrid scheme with other metaheuristic algorithms for successfully solving these problems. More precisely, the proposed algorithm (HBMO_ DRESs) combines a Honey Bees Mating Optimization (HBMO) algorithm, the Tabu Search (TS) and Simulated Annealing (SA)). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, the adopted method performs HW/SW partitioning and scheduling such that the global application execution time is minimized. Comparing the proposed method with Genetic Algorithm and Evolutionary Strategies (ES), the simulation results show that the proposed algorithm has better convergence performance.

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20

"Performance Improvement of Force-directed Partitioning Algorithm for HW/SW Codesign." KIPS Transactions:PartA 9A, no. 4 (December 1, 2002): 491–96. http://dx.doi.org/10.3745/kipsta.2002.9a.4.491.

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21

Zhang, Man, Imen Bahri, Xavier Mininger, Cristina Vlad, Hongqin Xie, Eric Berthelot, and Weihao Hu. "Vibration Reduction Controller for a Switched Reluctance Machine based on HW/SW Partitioning." IEEE Transactions on Industrial Informatics, 2020, 1. http://dx.doi.org/10.1109/tii.2020.3010375.

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22

Khadidja, Yahyaoui, and Bouchoicha Mohammed. "Collective Behavior Bees for Solving HW/SW Partitioning and Scheduling Problems in RSoC." Transactions on Machine Learning and Artificial Intelligence 5, no. 4 (August 31, 2017). http://dx.doi.org/10.14738/tmlai.54.3205.

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23

Akeela, Rami, and Mitchell P. Krawiec-Thayer. "Efficient HW/SW partitioning of Halo: FPGA-accelerated recursive proof composition in blockchain." Microsystem Technologies, January 3, 2021. http://dx.doi.org/10.1007/s00542-020-05138-4.

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