Dissertations / Theses on the topic 'IDCT'
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Anders, Jörg. "Java MPEG1-Player." Universitätsbibliothek Chemnitz, 2003. http://nbn-resolving.de/urn:nbn:de:swb:ch1-200300738.
Full textAugust, Nathaniel J. "On the Low Power Design of DCT and IDCT for Low Bit Rate Video Codecs." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/32125.
Full textMaster of Science
Pai, Cheng-Yu. "Design and evaluation of a data-dependent low-power 8 x 8 DCT/IDCT." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ59308.pdf.
Full textRosengren, Kaj. "Modelling and implementation of an MPEG-2 video decoder using a GALS design path." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6911.
Full textAs integrated circuits get smaller, faster and can fit more functionality, more problems arise with wire delays and cross-talk. Especially when using global clock signals distributed over a large chip area. This thesis will briefly discuss a solution to this problem using the Globally Asynchronous Locally Synchronous (GALS) design path.
The goal of this thesis was to test the solution by modelling and partially implementing an MPEG-2 video decoder connected as a GALS system, using synchronous design tools. This includes design of the system in Simulink, implementing selected parts in VHDL and finally testing the connected parts on an FPGA. Presented in this thesis is the design and implementation of the system as well as theory on the MPEG-2 video decoding standard and a short analysis of the result.
Zilic, Edmin. "Implementering av 1D-DCT." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7785.
Full textIDCT (Inverse Discrete Cosine Transform) is a common algorithm being used with image and sound decompression. The algorithm is a Fourier related transform which can occur in many different types like, one-dimensional, two-dimensional, three-dimensional and many more.
The goal with this thesis is to create a fast and low effect version of two-dimensional IDCT algorithm, where techniques as multiple-constant multiplication and subexpression sharing plus bit-serial and bit-parallel arithmetic are used.
The result is a hardware implementation with power consumption at 19,56 mW.
Bhardwaj, Divya Anshu. "Inverse Discrete Cosine Transform by Bit Parallel Implementation and Power Comparision." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2447.
Full textThe goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.
Abyaneh, Hossein Askarian. "Assessment of IDMT and distance relay settings." Thesis, University of Manchester, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332331.
Full textNgimbwa, Peter Cosmas. "An Irrigation Decision Support Tool (IDST) for Smallholdings in Tanzania." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1461171005.
Full textDu, Guangli. "Implementation of the SuperPave IDT analysis procedure." Thesis, KTH, Väg- och banteknik (stängd 20110301), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-52983.
Full textHalvarsson, Evelin, and Amanda Karsson. "Evidensbaseradeomvårdnadsbehov som påverkar livskvaliteten hos patienter idet palliativa skedet : En systematisk litteraturstudie." Thesis, Högskolan Dalarna, Omvårdnad, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:du-4420.
Full textArabackyj, Marc [Verfasser]. "Steigerung der Qualität des Fertigungstests integrierter Schaltungen durch IDDT-Verfahren / Marc Arabackyj." München : Verlag Dr. Hut, 2012. http://d-nb.info/1025821475/34.
Full textSong, Kibong. "Development of an Information Base Tool for IDT Research." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/52590.
Full textPh. D.
Ye, Zhan. "Yersinia pestis VIRULENCE FACTOR YopM UNDERMINES THE FUNCTION OF DISTINCT CCR2+Gr1+ CELLS IN SPLEEN AND LIVER DURING SYSTEMIC PLAGUE." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_diss/63.
Full textEstêvão, Carlos Miguel da Silva Coelho Pinheiro. "O IDT, IP no contexto do NPM e do PRACE." Master's thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12316.
Full textO estudo reflete sobre o IDT,IP, organismo público que tinha como missão operacionalizar as políticas públicas de luta contra as drogas, lícitas e ilícitas, e as dependências. Neste sentido, o objetivo do trabalho visa avaliar os impactos que podem ser observados no IDT,IP resultantes das reformas administrativas influenciadas pelo NPM ocorridas na Administração Pública portuguesa, especificamente pelo PRACE, e pelas opções de Políticas Públicas de luta contra as drogas assumidas por Portugal ao longo da primeira década do século XXI. Tendo em conta o objetivo definido anteriormente optámos por realizar um estudo comparativo entre o IDT e o IDT,IP, investigando, para cada um deles, os impactos decorrentes das três dimensões mencionadas. Para isso foi necessário, previamente, contextualizar e fundamentar as três dimensões. No final da investigação concluímos que o IDT,IP é um organismo público onde os impactos decorrentes do paradigma do NPM, do PRACE e das opções de Política Pública das Drogas se evidenciam claramente.
The study reflects on the IDT,IP, a public structure whose mission was to operationalize public policies to combat drugs, licit and illicit, and dependencies. In this sense the purpose of the study is to evaluate the impacts that can be observed in the IDT,IP resulting from the administrative reforms influenced by NPM occurred in the Portuguese Administration, more specifically by the PRACE, and the Public Policy options assumed by Portugal throughout the first decade of the twenty-first century. Taking into account the obective of the investigation, we developed a comparative study between the IDT and the IDT,IP, analysing, for each of them, the impacts resulting from the three mentioned subjects. This required a previous contextualization and explanation of the three concepts. At the end of the investigation it is possible to understand that the IDT,IP is a public organisation where the impacts of the NPM paradigm, the PRACE and the Drugs Public Policy options is clearly evident.
Ohrn, Tania L. "Assisting IDC [Integrated Diagnostic Center] in performing more efficiently and effectively." [Denver, Colo.] : Regis University, 2006. http://165.236.235.140/lib/TOhrn2006.pdf.
Full textBOUSQUET, POUGET PASCALE. "Le calculateur de dose d'insuline (idc) : etude chez 10 diabetiques insulinodependants." Clermont-Ferrand 1, 1991. http://www.theses.fr/1991CLF13009.
Full textArabackyj, Marc [Verfasser], and Klaus [Akademischer Betreuer] Helmreich. "Steigerung der Qualität des Fertigungstests integrierter Schaltungen durch IDDT-Verfahren / Marc Arabackyj. Betreuer: Klaus Helmreich." Erlangen : Universitätsbibliothek der Universität Erlangen-Nürnberg, 2012. http://d-nb.info/1024198952/34.
Full textBernardo, Luiz Carlos. "Sistemas de comunicação utilizando transmissão OFDM baseado em wavelets com subportadoras com modulação caótica." Universidade Presbiteriana Mackenzie, 2013. http://tede.mackenzie.br/jspui/handle/tede/1434.
Full textA chaotic signal based communication system represents a new wideband transmission model. Nonetheless, chaotic based systems have not yet shown a distinguished performance in terms of bit error rate when transmitted in narrow band channels or in the presence of impairments in comparison to the traditional communications systems. The focus of this work relies on an experiment that overcomes this issue, through the conjugation of the characteristics of traditional communications based in orthogonal carriers and those originated from chaotic signals. More clearly, the chaotic modulation is employed in sub-carriers of traditional OFDM (Orthogonal Frequency Division Multiplexing). This novel modulation scheme is implemented through the generation of chaotic sequences in a one dimensional map controlled by a parameter p which defines the central region of the map as a guard interval, the slope of the delimiting lines and the chaotic behavior of the generated sequence. This parameter also determines directly the amplitude of each symbol, making it more irregular and less predictable, avoiding the detection by eavesdroppers and increasing the security level of the link to be transmitted. Besides the change in the traditional OFDM modulator from 4QAM to chaotic one, the Fast Fourier Transform (IFFT /FFT) will be replaced by Wavelets Transform IDWT/DWT), in order to overcome some conventional OFDM s disadvantages Additionally a quadrature chaotic OFDM system was conceived, where the chaotic modulation was performed in a constellation I and Q that was submitted to the same channel conditions as the previous one. Both systems were simulated in a MATLAB® environment using the built in functions at the Communications System Toolbox and its behavior analyzed using the BER-Bit error rate versus SNR-Signal noise ratio. The obtained results were reported and scrutinized.
Sistemas de comunicações baseados em sinais caóticos representam um novo campo de estudo de transmissão em banda larga. Entretanto, sistemas baseados em sinais caóticos não apresentaram ainda um desempenho distinto em termos de taxa de erro, quando transmitidos em canais sem fios ou na presença de interferências em comparação aos sistemas tradicionais. O foco deste trabalho está na proposta de um novo esquema obtido através da conjugação das características da comunicação tradicional baseada em subportadoras ortogonais e aquelas originadas por sinais caóticos. Mais precisamente, a modulação caótica é empregada nas subportadoras de um sistema OFDM (Multiplexação por Divisão de Frequência Ortogonal) tradicional. Este novo modelo de modulação é implementado através de geração de sequências caóticas em um mapa unidimensional controlado por um parâmetro p que define uma região central do mapa como um intervalo de guarda e, por conseguinte, o comportamento caótico da sequência gerada. Este parâmetro também determina diretamente a amplitude de cada símbolo, fazendo-o mais irregular e menos previsível, evitando a detecção por pessoal não autorizado, possibilitando o aumento do nível de segurança da transmissão. Além da mudança no modulador do OFDM convencional de 4QAM para caótico, ter-se-á a substituição da Transformada Rápida de Fourier (IFFT/FFT), largamente utilizada em sistemas OFDM pela Transformada Wavelet (IDWT/DWT), de maneira a aprimorar os pontos fracos do sistema OFDM convencional. Como contribuição adicional, tem se a concepção do sinal com modulação simbólica em quadratura, ou seja, uma parte do sinal foi gerada no eixo I e a outra parte no eixo Q, criando uma modulação caótica em quadratura que é submetida aos mesmos canais da modulação caótica anterior. Os sistemas propostos foram simulados em ambiente MATLAB® utilizando-se de funções pré-existentes no modulo de ferramentas de comunicações (Communications System Toolbox) e o seu comportamento analisado em termos de gráficos que representam a relação da taxa de erro do bit (BER) versus relação sinal ruído (SNR). Os resultados obtidos foram reportados e debatidos.
Johnson, Mark S. "Validation of an active multimedia courseware package for the Integrated Damage Control Training Technology (IDCTT) trainer." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA286207.
Full textAndrade, Rubstain Ferreira Ramos de. "Caminhos para o desenvolvimento territorial : uma trajetória da gestão social no Assentamento Nova Vitória, Brasília-DF." reponame:Repositório Institucional da UnB, 2015. http://dx.doi.org/10.26512/2015.03.D.19073.
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A Empresa de Assistência Técnica e Extensão Rural do Distrito Federal (EMATER-DF) diante do novo desafio da Política Nacional de Assistência Técnica e Extensão Rural (PNATER) para a promoção de uma ATER pública de qualidade, com agentes comprometidos com a agricultura familiar, com intervenção dialógica, construtiva, com uma práxis democrática e de orientação libertadora, com foco em uma extensão rural agroecológica, desenvolveu um instrumento para apoiar o processo de intervenção, chamado Índice de Desenvolvimento Comunitário Rural (IDCR) que tem como objetivo maior atender as demandas da gestão de políticas públicas mais específicas para cada comunidade. O objetivo do presente trabalho é estudar o processo de gestão social do Assentamento Nova Vitória - região administrativa de São Sebastião, Brasília-DF – para conhecer os caminhos para o desenvolvimento territorial, para verificar se esta ação de reconhecimento das necessidades locais viabilizará a dedicação das pessoas para a gestão social com foco na resistência para superar suas limitações, aproveitando o potencial local e a contribuição das políticas públicas construídas para uma melhor capacidade de negociação junto aos diversos setores institucionais.
The Enterprise Technical Assistance and Rural Extension of the Federal District (DF-EMATER) before the new challenge of the National Policy of Technical Assistance and Rural Extension - PNATER, for the promotion of quality public ATER, with committed staff and family agriculture, with dialogue, constructive intervention, with a democratic and liberating praxis orientation, focusing on an extension agroecology, has developed a tool to support the intervention process called Community Development Index rural-IDCR, to meet the demands of public policy management more specific to each community. The objective of this project is to identify the complexity in social relations in the social management process using the instrument IDCR in New Settlement Vitória - São Sebastião-DF, we will seek to determine whether that action to recognize local needs, will enable the dedication of the people for the management social focusing strength to overcome its limitations, using your local potential and contribution in public policies built by a good negotiation skills with the institutions of the various sectors.
Coughlin, Stephen J. "An assessment of the shipboard training effectiveness of the Integrated Damage Control Training Technology (IDCTT) version 3.0." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA345970.
Full textThesis Advisor(s): Bernard J. Ulozas, Alice Crawford. "March 1998." Includes bibliographical references (p. 147-150). Also available online.
Fuller, John V., Alice M. Crawford, and Frank C. Petho. "Measuring Damage Control Assistant's (DCA) decision-making proficiency in Integrated Damage Control Training Technology (IDCTT) training scenarios." Thesis, Monterey, California: Naval Postgraduate School, 1993. http://hdl.handle.net/10945/24190.
Full textPerleche, Quintanilla Kenneth Andersson, and Arangurí Jaime Eduardo Inga. "Roadmap de tendencias de TI." Bachelor's thesis, Universidad Peruana de Ciencias Aplicadas (UPC), 2018. http://hdl.handle.net/10757/626105.
Full textThis project aims to present in a structured, trends of information technology to the next five years. Also, identify key technologies that will be more relevant and, from this source, develop a portfolio of projects oriented knowledge are provided within the EISC are. Through this, it will contribute to the development of future projects in the Peruvian University of Applied Sciences. Reference sources IT trends will be providing Gartner, Forrester and IDC. Also, perform benchmarking on methodologies that provide each of these organizations. The project is developed in different stages, which will be reflected in the document through chapters, where the description of the project, study objective, problem and approach of the solution is defined. This will be reflected in the development of the research based on the technologies and deepening the context and its application to the future. Likewise, the development of the methodological process for the obtaining of results and the due management for these.
Tesis
Mahashe, Mawande Victor. "The effectiveness of IDC in financing the construction of low cost or RDP housing." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/97468.
Full textENGLISH ABSTRACT: The non-availability of funding for low-cost housing is a major stumbling block in the provision of housing for the poor in South Africa (Moss, 2001). Banks and other commercial institutions are generally reluctant to fund construction companies in this industry in view of the high level of risk involved. The Industrial Development Corporation of South Africa is a development finance institution that is involved in the financing of construction companies. This study looked at the effectiveness of IDC in financing construction companies that are involved in low cost housing development. The study also looked at whether the IDC's strategiC objectives of promoting job creation had been achieved by providing funding to the construction companies. Only those companies involved in low-cost housing as the only or part of their business activities have been chosen for the study. A qualitative method of research analysiS has been selected as the best way of analysing the research findings in this paper. The empirical analysis indicated that generally the respondents are satisfied with the funding provided by the Industrial Development Corporation, but have serious concerns regarding the turnaround times for credit approvals, completion of legal agreements, disbursement of funds and the fees charged.
Boulet, Jean-Claude. "Contribution des informations expérimentales et expertes à l'amélioration des modèles linéaires d'étalonnage multivarié en spectrométrie." Thesis, Montpellier, SupAgro, 2010. http://www.theses.fr/2010NSAM0027/document.
Full textSpectra contain informations about the composition of samples. This information is obtained using calibration. Harmful spectral information can be previoulsy withdrawn using pretraitments. Both calibration and pretraitment models are based on two types of informations: (1) experimental information based on measurements onto samples; (2) expert information based on a previous knowledge. The aim of this thesis is to study the links between those two types of information. After a biography review, a general model including both calibrations and pretraitments is proposed. The usefull or harmful spectral information is obtained after spectra have been orthogonaly projected (with a Sigma metrix ) onto a P matrix whose columns define a basis of the vectorial subspace described by the usefull or harmful information. Thus usefull information is kept whereas harmful information is withdrawn. Two new methods are proposed. First IDC-Improved Direct Calibra tion is a direct calibration method using both experimental and expert informations. Then VODKA-PLSR is a generalisation of PLSR. A vector r permits the use of expert information by the regression model. To conclude, this works allows a global view of existing tools, proposes two new models and offers new possibilities for building new models
Vemulapalli, Sreekanth. "Design Of Tunable Band Pass Filter Using Barium Strontium Titanate (BST) Thin Films." University of Dayton / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1304697174.
Full textPiquer, Gibert Mònica. "Fenotips d'immunodeficiència comuna variable (IDCV) en pacients pediàtrics. Correlació genotip-fenotip en l'evolució clínica i el tractament dels pacients." Doctoral thesis, Universitat de Barcelona, 2017. http://hdl.handle.net/10803/664273.
Full textCommon variable immunodeficiency (CVID) is an immune disorder characterized by a defect of antibody production in relation to recurrent sinopulmonary infections, autoimmune disorders, granulomatous disease and an increased risk of malignancy. CVID is a heterogeneous disease and pediatric patients have a great clinical variability and evolution attributable in part to the fact that it is a diagnosis of exclusion. The present study is focused on the clinical description, the immunological analysis and genetic study (whole exome sequencing) of a cohort of patients diagnosed of CVID with pediatric onset and diagnosis. We study 25 patients where the median age at the first symptom is 4 years old and 9 years old at diagnosis. Most of patients are male, Caucasian race and not inbred. Clinical and immunological characteristics are identified associated with certain phenotypes. Patient with mutations developed more clinical phenotypes and suffer CMV and/or EBV infections. More than half of patients with CVID presented autoimmune disease and 1/3 associated two or more autoimmune diseases. The female patients presented more complex phenotypes and worse prognosis, and patients with expansion of B lymphocytes CD21low presented greater chance of autoimmunity. Five malignancies (4 lymphomas) were diagnosed in four out of the 25 CVID pediatric patients. Since neither a particular immunological nor clinical phenotyping is clearly associated with an increased risk of developing malignancy, we recommend performing screening and prevention of modifiable factors for cancer in all CVID patients regardless of their age. Moreover, in pediatric patients with immunodeficiency and lymphoma, a screening for underlying genetic defects should be considered. This study allows diagnosing more accurately up to 20% of patients because of genetic studies (mutations in TACI, LRBA, PIK3R1 and CTLA4). In these patients has been possible genetic counselling and in 2 of them the fact of establishing a diagnosis of certainty has represented a change in the treatment and therefore in their prognosis.
Pavan, Renata Bigatti Bellizzotti 1982. "Validação do instrumento para mensuração do impacto da doença no cotidiano do valvopata - IDCV em pacientes com hipertensão arterial." [s.n.], 2012. http://repositorio.unicamp.br/jspui/handle/REPOSIP/310828.
Full textDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Ciências Médicas.
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Resumo: Este estudo teve como objetivo avaliar a praticabilidade, a aceitabilidade, os efeitos teto e chão, a confiabilidade e validade de constructo convergente, divergente e discriminante do instrumento para mensuração do Impacto da Doença no Cotidiano do Valvopata (IDCV), em pacientes hipertensos. Fizeram parte deste estudo 137 pacientes hipertensos em seguimento ambulatorial. A praticabilidade do IDCV foi avaliada por meio do tempo despendido na entrevista e a aceitabilidade pelo percentual de itens não respondidos e proporção de pacientes que responderam a todos os itens. Para análise do efeito teto e chão foi considerada a percentagem de pacientes que pontuou nos 10% melhores e piores resultados da escala, respectivamente. A confiabilidade foi avaliada por meio da estabilidade da medida e pela consistência interna, sendo utilizados os coeficientes de correlação intraclasse e o coeficiente alfa de Cronbach, respectivamente. A validade de constructo foi estimada por meio do coeficiente de correlação Spearman entre o IDCV e as medidas genérica (The Medical Study 36-item Short Form Health Survey - SF-36) e específica (Questionário de Qualidade de Vida em Hipertensão Arterial - Minichal Brasil) de qualidade de vida relacionada à saúde (QVRS), bem como com os instrumentos de medida da capacidade física (Veterans Specific Activity Questionnaire - VSAQ), Pictograma de Fadiga e Medida Geral de Impacto. A validade discriminante do IDCV foi testada com o emprego do teste de Mann Whitney para verificar se o IDCV é capaz de discriminar diferenças no impacto da doença de hipertensos com e sem controle da pressão arterial e utilizado o teste de Kruskall-Wallis e Anova com transformação por postos seguida do teste de Tukey para localização das diferenças, para testar a capacidade do IDCV em discriminar o impacto da doença entre grupos de pacientes classificados quanto a gravidade da hipertensão. O tempo médio de aplicação do IDCV foi de 8,0 (±3,0) minutos; 100% dos itens foram respondidos por todos os pacientes. Não foram detectados efeito teto e chão para o escore total do IDCV; no entanto, 31,4% dos sujeitos pontuaram "teto" no domínio Adaptação à Doença. A estabilidade da medida foi evidenciada para o escore total (ICC=0,99) e para todos os domínios. Foram constatadas evidências de consistência interna do IDCV total ('alfa'=0,83) e para os domínios Impacto Físico da Doença - Sintomas ('alfa'=0,78) e Impacto Social e Emocional da Doença ('alfa'=0,74). O IDCV total foi moderadamente correlacionado com todas as dimensões do SF-36, Minichal e Pictograma de Fadiga. Os domínios similares do IDCV, Minichal e SF-36 foram correlacionados. Correlações de moderada magnitude foram observadas entre: Impacto Social e Emocional do IDCV com a Capacidade Funcional, Dor, Estado Geral de Saúde e Vitalidade do SF-36. Além disso, indivíduos que apresentam pressão arterial não controlada tiveram escores significativamente maiores no IDCV do que aqueles com pressão controlada. O IDCV foi incapaz de discriminar os sujeitos classificados de acordo com a gravidade da hipertensão. Conclui-se que o IDCV é um instrumento de fácil aplicação e compreensão, com evidências de confiabilidade e validade de constructo convergente, divergente e discriminante em hipertensos
Abstract: This study aimed at evaluating the practicability, acceptability, ceiling and floor effects, reliability and convergent, divergent, discriminant validity of the Instrument for Measuring the Impact of Valve Heart Disease (IDCV), in hypertensive patients. One hundred thirty seven hypertensive outpatients were enrolled in the study. The practicability of IDCV was assessed by time spent in the interview and acceptance by the percentage of unanswered items and proportion of patients who answered to all items. To analyze the ceiling and floor effect it was considered the percentage of patients in the 10% best and worst results of the scale, respectively. The reliability was assessed according to the stability of the measure and internal consistency, using intraclass correlation coefficient (ICC) and Cronbach's alpha coefficient, respectively. The property of convergent/divergent validity was investigated by testing the correlation (Spearman coefficients) between the total and domains' scores of IDCV and of the Medical Outcomes Trust Short-form Health Survey (SF-36), Short Form of the Hypertension Quality of life Questionnaire (Minichal); Veterans Specific Activity Questionnaire (VSAQ), Fatigue Pictogram and General Measure of the Disease Impact. Discriminative validity of IDCV was evaluated according to the criteria of hypertension severity and control of blood pressure. The average application of IDCV was 8.0 (± 3.0) minutes; 100% of items were answered by all patients. It was not detected ceiling and floor effect for the total score of IDCV, however, 31.4% of subjects scored "ceiling" in the domain Adjustment to the Disease. The measurement stability was observed for the total score (ICC = 0.99) and for all domains. We found evidence of internal consistency IDCV total ('alpha' = 0.83) and for the domains Physical Impact of the Disease ('alpha' = 0.78) and Social and Emotional Impact of the Disease ('alpha' = 0.74). The total score of the IDCV were moderately correlated to all dimensions of the SF-36, the Minichal Questionnaire and Fatigue Pictogram total score. Similar domains on the IDCV, Minichal and SF-36 were correlated: Social and Emotional Impact of the IDCV with the Emotional domains and the Mental Health of the SF-36; and with Mental State of the Minichal; Physical Impact - Symptoms of the IDCV with Physical Functioning and Pain of the SF-36 and Somatic Manifestation of the Minichal. Correlations of moderate magnitude were also observed between: Social and Emotional Impact of the IDCV with Physical Functioning, Pain, General Health and Vitality of the SF-36. Additionally, individuals presenting uncontrolled blood pressure had statistically significantly higher IDCV scores than those with controlled levels blood pressure. The IDCV was unable to discriminate the subjects classified according to the severity of hypertension
Mestrado
Enfermagem e Trabalho
Mestra em Ciências da Saúde
Rieskamp, Kristina-Marija [Verfasser], and Bernd [Akademischer Betreuer] Wegener. "Experimentelle Evaluation des Risikos der extradiscalen thermischen Schädigung während der intradiscalen elektrothermalen Therapie (IDET) / Kristina-Marija Rieskamp. Betreuer: Bernd Wegener." München : Universitätsbibliothek der Ludwig-Maximilians-Universität, 2015. http://d-nb.info/1081899794/34.
Full text木村, 宏恒, and Hirotsune Kimura. "上からのマイクロクレジット : IDT(インドネシア貧困撲滅計画)の教訓." 名古屋大学大学院国際開発研究科, 1999. http://hdl.handle.net/2237/6666.
Full textAmparbeng, Kofi. "A cross sectional analysis of SME failure within the industrial sector: focus on IDC funded investments." Master's thesis, University of Cape Town, 2012. http://hdl.handle.net/11427/29006.
Full textAlemayehu, Andargachew Desta. "Microwave Frequency Thin BST Film Based Tunable Shunt and Series Interdigital Capacitor Device Design." University of Dayton / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1304558851.
Full textSadllah, Stapheen. "Produktutveckling av kyl/värmesystem för barnvagn." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-39222.
Full textShiu, Yi-Cheng, and 許益誠. "LOW-COST DESIGN OF IDCT FOR HDTV." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/77082446891281521292.
Full text大同大學
電機工程研究所
90
In this thesis, we design a low cost processor core of IDCT for HDTV. In the HDTV application, IDCT processor must operate in 80MHz at least. In order to achieve this goad, our design in Adder-based DA algorithm with novel adder reduction technique, another coefficient code and summation network asynchronous. Under the simulation of VIRTEX V100CS144 from Xilinx Foundation F3.1i, the result shows that it is appropriate for the requirements when working at 100MHz.
Tsai, Lei-Luo, and 蔡磊駱. "IMPLEMENTATION OF 2-D DCT/IDCT VLSI ARCHITECTURE." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/58937135731980105959.
Full text大同工學院
電機工程研究所
87
This thesis discusses the design of a combined DCT/IDCT CMOS integrated circuit for general video application. We know that the discrete cosine transform is widely used in several international standards, in this thesis, we use a low-complexity, and high-performance architecture to realize a DCT/IDCT chip. Beside, we also use some technique (tree structure) to improve the chip performance. Based on TSMC SPTM 0.6μm CMOS technology and COMPASS 0.6μm cell library, our DCT chip is implemented. It integrates about 120k transistors, and die size occupies a silicon area of 5415μm x 5495μm, and simulation results show that the clock rate can be up to above 85MHz that conforms our requirement.
Lin, Chun-Pin, and 林俊賓. "The Implementation of A Novel DCT/IDCT Chip." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/25856889946127942021.
Full text淡江大學
電機工程學系
88
The discrete cosine transform (DCT) is widely used in digital signal processing, particularly for digital image processing. Because of the complicated computational complexity, many efficient algorithms are proposed to improve the computing speed and hardware complexity. Discrete cosine transform (DCT) is used as core technique in the CODEC systems based on the compression standards of JPEG and MPEG. DCT can be implemented to integration circuits thanks to mature of semiconductor technology. The goal of this thesis is to design and implement a two-dimensional 8x8 discrete cosine transform chip for real-time applications. For real time application, this architecture of this DCT/IDCT chip contains the following features: (1) Modified butterfly architecture are applied to reduce a part of the adders, subtracters and multipliers. And make all coefficients of the modified butterfly architecture are positive to simplify the multiplier design. (2) Booth coding scheme and Wallace tree architecture are used to reduce the numbers of non-zero bit of coefficients and implementation the fast multiplier. (3) Pipelining architecture are applied to the parallel processing in order to reduce the total computing time efficiently.(4) Two transpose memory blocks are used to reduce the waiting state and to improve the latency. For 8x8 an information block, the latency only needs 37 clock cycles. The design is used Verilog HDL to implement the circuit modules and synthesis the modules with the cell library provided by CIC and synthesis tools provided by Synopsys. Then the Cadence CAD is used to do the auto-place-and-route (APR) and verification. Finally, transistor level simulation is analyzed with Timemill provided by EPIC.
Liu, Min-Chih, and 劉旻智. "VLSI IMPLEMENTATION OF 2-D DCT/IDCT ARCHITECTURE." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/58319845538696646120.
Full text大同大學
電機工程學系(所)
96
The digit compress technology is concerned by people extremely. The 2-D DCT and IDCT are widely used and the most effective compression technology in image compressing. There are also a lot of new algorithms being proposed all the time, but most structure application will spend too much cost. This paper takes the short time to market and low cost as the direction in design. We make the design to be an DCT/IDCT IP under the consideration of the area and speed of the chip. Though 2-D DCT/IDCT roughly are divided into row-column decomposition (RCD) and not row-column decomposition (NRCD). NRCD is more efficient than RCD, but it is relatively too complex for hardware to be implemented. So the design structure of this thesis also uses RCD as usual. And in order to get higher throughput, it uses two 1-D DCT/IDCT circuit units to do parallel operation. It also uses the improved shift-and-add multiplication logic to balance each multiplication path and save hardware resource. Combined with the concept of pipeline, the design can deal with input data continually. Finally, we can ensure the design reaching the requirements with the function and timing checking. Then we enforce placement and routing steps of back-end flow to finish the physical layout and make physical verifications to guarantee that the chip can be tape-outed.
Chen, Ting-Yu, and 陳亭諭. "Efficient BIST Techniques for Two-Dimensional DCT / IDCT Processor." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/97537645511103647119.
Full text輔仁大學
電子工程學系
91
In this paper, we propose a fully parallel systolic array architecture by using row-column decomposition method for 2D-DCT/IDCT applications. The architecture proposed possesses many advantages such as (1) the regularity of this architecture is higher than others. (2) control signals are greatly simplified. (3) it meets all MPEG-2 specifications. It is a high throughput architecture which performs one complete N × N—point transform per N clock cycles, and the latency of the architecture is only 2 N clock cycles. ,and (4) the architecture is very flexible. We use QuartusII software of Altera Corp. to simulate the circuit function and compare the results with the simulation results of the software implementation. The simulation results show that the architecture proposed can work correctly. For chip testing consideration, we modify the processing elements of array and make it bijective. We choose the cell fault model for multiplier and adder units. Then we combine the adder with the register file to perform accumulation and compression functions to evaluate the signatures of different test sessions. The signatures of each testing session are stored in each processing element and propagated to the primary outputs when the test session is done. We also propose a very efficiently BIST method. The TPGs can be implemented with several simple binary counters. Finally, the order of each BIST session is decided by the corresponding silicon area covered by that test session. This will efficiently shorten the test time.
CHIEH, TASI JEN, and 蔡仁傑. "Scalable DCT/IDCT Processor Design Using Prime-Factor Algorithm." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/99061536319178199211.
Full text國立交通大學
電機與控制工程系
89
DCT ( Discrete Cosine Transform ) has been widely used in digital signal processing , especially in image and audio processing. Although a large number of papers have been proposed to meet the real-time requirements, most of them can only deal with either 1-D or 2-D DCT/IDCT and the fixed-length DCT/IDCT. In order to increase the flexibility, this thesis proposes a scalable, parameterized DCT/IDCT processor using Prime-Factor Algorithm (PFA). The proposed architecture can perform both 1-D and 2-D variable length DCT/IDCT and features high degree of regularity and modularity. Finally, a prototype chip has been built using TSMC 0.35mm CMOS technology. The chip is packaged by 100 LD CQFP and can be operated at 45.5 MHz.
林郁翔. "Hardware architectures for the H.265-HEVC DCT/IDCT." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/4skwbh.
Full text國立彰化師範大學
資訊工程學系
105
It is that digital multimedia change the communication and life of human. It has the huge influence on human civilization. Data compression and video encoding are the important technology in the digital multimedia. Because H.264-AVC (Advanced Video Coding) has high efficiency data compression and video encoding, It has the huge influence in many kinds of Multimedia services. The International Telecommunication Union (ITU) has officially agreed on the release of the new video coding standard ITU-T H.265 (HEVC) January 25, 2013. H.265-HEVC is based on H.264-AVC, but it provides more flexible, more reliable and more stable than H.264-AVC. in the same quality, H.265-HEVC uses half of data volume than H.264-AVC, but H.265-HEVC provides methods and algorithm are more complex than H.264-AVC. This paper introduce the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) which applied to H.265-HEVC. Hardware and Software of DCT in this paper is implemented based on the DCT algorithm which is proposed by Grzegorz- Pastuszak and hardware and software of IDCT is implemented based on the modifying Row/Column DCT. Compared the results of data to the traditional software of two-dimensional DCT / IDCT and hardware of two-dimensional DCT / IDCT, performance of PSNR in hardware are not much difference from software, but the processing speed obtain improved dramatically
Tseng, Chung-Ching, and 曾仲卿. "Reduced Coefficient 2-D IDCT Architecture Design for MPEG Decoder." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/68788258094806577025.
Full text國立交通大學
電子研究所
83
In recent years, video compression techniques are widely applied and the 2-D DCT is recognized as the most effective technique. In MPEG, the DCT is postprocessed with quantization and most of the DCT coefficients are quantized to be zero. By using this characteristic; we developed a reduced coefficient 2-D IDCT algorithm. It is not only efficient for decoding but also its architecture is well suited for VLSI implementation. In this thesis, we proposed this two-dimensional inverse discrete cosine transform (2-D IDCT) algorithm based on base matrices and its symmetrical property, and then use the property of cosine product by sum-difference to reduce the number of multiplications. Thus the average number of multiplications with this algorithm is one-tenth comparing to the conventional row-column method. The average number of additions is also less than conventional row-column method. The IDCT chip totally uses 12500 gates; and thus is area efficient. The operation speed of IDCT chip is 80 MHz, and thus it computes one less than 2.5 us per 8x8 block that can satisfy the requirement of MPEG-2.
曾盟鈞. "A Design of High Performance 2-D DCT/IDCT Processor." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/35714584534535445296.
Full text中華大學
電機工程研究所
86
Discrete Cosine Transform (DCT) has been commonly adopted in many transformation application such as image, video, and facsimile. The discrete transform (DCT) has been recognized as one of the standard techniques in image compression. Therefore, a core processor that rapidly compputes DCT/IDCT has become a key comonent-in image compression in VLSI implementation. This paper describes ka 100-MHz two-dimensional DCT/IDCT core processor, whice is applicable to the real-time processigng of H.263 signals. Furthermore, mean values of errors generated in the core were minimezed to enhance the computational accuracy with the word-length constraints. Consequently,it features the fast operating speed under the low area with ist sufficient accuracy satisfying the specifications in CCITT recommendation H.263.
李俊凌. "A Fast and Scalable DCT/IDCT Processor Based on CORDIC Algorithm." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/14801633000485549844.
Full text國立臺灣科技大學
電機工程技術研究所
86
Progress in various fields of digital technology have made possible many applications of digital video such as hgh-definition television (HDTV),teleconferencing, and multimedia communications, These applications require high-speed transmission of vast amounts of video dato. Most video standards such as HDTV video conding, H. 261, JPEG, and MPEG use discrete cosine transform (DCT) as a standard transform coding scheme. The DCT is, however, very computationally intensive. To realize high-speed and cost-effective DCT for video coding, one needs efficient VLSI implementations so that the real time requirements can be matched. In our thesis, we propose a scalable and parallel architecture for DCT/IDCT.In the architecture, we employed an alternative arithmetic computing algorithm known as CORDIC (COordinate Rotation Digital Computer) to efficiently evaluate each of elementary functions in DCT/IDCT.By the properties of DCT/IDCT algorithm we adopt, we improve the hardware implementation and diminish the control circuit for computing cosine function.
Chih-Sheng, Huang, and 黃志聖. "The Design and Implementation of DCT/IDCT Chip with Novel Architecture." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/27326219756381096351.
Full text淡江大學
電機工程學系
87
Along with the progress of computer technology, the application of digital techniques such as HDTV and Videoconference include a large amount of pictures and image information. In order to store and transmit these data, it is an exigent issue how to compress them efficiently. JPEG and MPEG are the compression standards made for solving these problems. Discrete cosine transform (DCT) is used as core technique in the CODEC systems based on the compression standards of JPEG and MPEG because DCT is a very efficient technique among all approaches of image compression. DCT can be implemented to integration circuits thanks to mature of semiconductor technology. In the thesis, new architecture for VLSI implementation of real time DCT/IDCT chip is designed. For real time application, This architecture contains the following features: (1) Use modified butterfly architecture to reduce a part of the adders, substrators, and multipliers. And make all coefficients of the modified butterfly architecture are positive to simplify the multiplier design. (2) Use Booth coding scheme to reduce the numbers of non-zero bit of coefficients, and using Wallace tree architecture to implementation faster multipliers. (3) Use pipeline architecture for the parallel processing in order to reduce the total computing time efficiently. We use Verilog HDL to implement the circuit modules and synthesis the modules with the cell library provided by CIC and synthesis tools provided by Synopsys. Then the Cadence CAD is used to do the auto-place-and-route (APR) and verification. Finally, transistor level simulation is analyzed with TimeMill provided by EPIC.
朱瑞欽. "An efficient adder-based 2-D DCT/IDCT IP core design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/58577354836897901875.
Full textHung, Ming-Chi, and 洪明吉. "VLSI Implementation of An Area Efficient 2-D DCT/IDCT Architecture." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/36736917762404073846.
Full text逢甲大學
自動控制工程學系
89
There are many efficient VLSI architectures of 2-D DCT and 2-D IDCT for area and processing speed points of view. However, most of them spend much cost for using in a real-time digital video codec system. The aim of our research work was to develop an area efficient and low complexity VLSI architecture of 2-D DCT and 2-D IDCT for real-time digital low bit-rate video codec system. Hardware cost and performance of this architecture are main key point. It is based on the row-column decomposition technique. This architecture would be shown that a single 1-D DCT/IDCT could take role of 2-D DCT and 2-D IDCT. It can be achieved through precise timing scheduled. Intuitively, three 1-D DCT/IDCT and a matrix transposition could be saved as compared to the conventional architectures which usually use two one-dimensional transforms and transposition memory. To reduce its processing time, the proposed architecture used 3-bit serial distributed arithmetic, parallel and pipelined method. We simulated the finite wordlength of the proposed 2-D DCT/IDCT algorithm with C language. Then, based on TSMC 0.35um process technique, Galax! 0.35um cell library is used to implement the 2-D DCT/IDCT architecture. In proposed architecture, 11895 gates were consumed roughly for 45 MHz operating clock. As a result, this architecture can be characterized to maximize the utilization of the hardware resources. It also can be applied to the ASIC chips for real-time digital low bit-rate video codec system and multimedia services especially requiring low cost and low hardware complexity.
Pai, Cheng-Yu. "Design and evaluation of a data-dependent low-power 8x8 DCT/IDCT." Thesis, 2000. http://spectrum.library.concordia.ca/1299/1/MQ59308.pdf.
Full textLIN, HSIN-KUN, and 林信堃. "Reconfigurable DCT/IDCT Architecture Design for H.265HEVC Image and Video Compression." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/9bdrgf.
Full text國立雲林科技大學
電子工程系
104
In this paper, a reconfigurable Discrete Cosine Transform (DCT) architecture for H.265/HEVC video compression standard is presented. In order to reduce H.265/HEVC computation complexity, the basic elements by 0, ±0.5, ±1 are proposed to replace the traditional DCT coefficients. Next, we derive reconfigurable DCT coefficients for different transform block sizes based on DCT symmetry properties. From simulation results, we have gain higher 4dB for average peak signal-to-noise ratio (PSNR) values when comparing with general approximate DCT approaches. Since the proposed reconfigurable DCT coefficient is suitable for hardware design, a lower hardware cost and faster computation DCT architecture is designed and implemented on FPGA and chip. From the experimental results, the proposed architecture is available in H.265/HEVC standard compression. The reconfigurable DCT architecture successfully reduces approximately 40% hardware cost for multiple transform blocks.
Tsai, Shang-Ta, and 蔡尚達. "A Reconfigurable Architecture for Entropy Decoders and IDCT in H.264/AVC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/84783642624337145783.
Full text國立成功大學
電機工程學系碩博士班
96
Coarse-grain reconfigurable architectures can offer obvious advantages over the fine-grain counterparts for some specific applications. This thesis explores techniques to combine the two entropy decoding methods, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), provided in H.264/AVC using the coarse-grain reconfigurable architecture. By analyzing the similarities and differences between these two decoding processes, we show how to effectively merge the CAVLC into the CABAC decoder. Experimental results exhibit that about 1.5 K gates can be saved using our reconfigurable cell (RC) architecture, which corresponds to 25.4% area savings in implementing the CAVLC decoder. To use the idle time in RC arrays, the base cell can be further extended to carry out the inverse discrete cosine transform (IDCT) with very limited overhead. In this manner, our entropy decoder design, operated in 66 MHz, can decode video sequences at Main Profile Level 3.0 under the real-time constraint.
Wu, Chung-Lin, and 吳宗霖. "A DCT/IDCT IP Design and Its Implementation to MPEG-2 SoC Prototype." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/42918292769301775490.
Full text國立雲林科技大學
電子與資訊工程研究所
93
The progress of IC designing technique has brought up SoC. In a big system, the relation among operating system , driver , hardware circuit, influence whole efficiency of system. Among this page thesis, how be software , efficient communication of hardware? Regard MPEG-2 as the example , realize in the young system of ARM , and has proposed the hardware structure of one MSD-First DCT. Let FPGA deal with the operation of DCT, other parts are transfered to ARM processors to finish operation. Among them divide into the situation with operating system, do the situation in fact with have no situation of the operating system. The traditional addition device will have question of wave carry of ripples, unable to finish demand for the high-speed system. There are many kinds of to solve wave carry methods of the ripples. This thesis adopts addition device of number location to realize in DCT operation, and utilize the way in which the high position have priority to deal with the most, let whole DCT circuit under 0.35um make , can reach speed of 434MHz , is it have DCT circuit interface of AHB link up with ARM to make finally in Taiwan Semiconductor Manufacturing Co., finish the basic software and hardware and communicate and deal with realizing.