Journal articles: 'Ideal metal-semiconductor interface'

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Mönch, Winfried. "Electronic properties of ideal and interface-modified metal-semiconductor interfaces." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 14, no. 4 (July 1996): 2985. http://dx.doi.org/10.1116/1.588947.

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FLORES, F. "ALKALI-ATOM ADSORPTION ON SEMICONDUCTOR SURFACES: METALLIZATION AND SCHOTTKY-BARRIER FORMATION." Surface Review and Letters 02, no. 04 (August 1995): 513–37. http://dx.doi.org/10.1142/s0218625x95000480.

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Alkali metals deposited on weakly ionic semiconductors are neither reactive nor form large three-dimensional islands, offering an ideal system in which Schottky junctions can be analyzed. In this paper, the alkali-metal-semiconductor interface is reviewed with a special emphasis on the formation of the Schottky barrier. Two regimes are clearly differentiated for the deposition of AMs on a semiconductor: in the high-coverage limit the Schottky barrier is shown to depend, for not very defective interfaces, on the semiconductor charge neutrality level. For low coverages, different one- and two-dimensional structures appear on the semiconductor surface presenting an insulating behavior. For depositions around a metal monolayer, a Mott metal-insulator transition appears; then, the interface Fermi energy is pinned by the metallic density of states at the position determined by the semiconductor charge neutrality level. This situation defines the Schottky barrier height of a thick-metal overlayer.

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Murakami, Masanori, Yasuo Koide, and Takeo Oku. "Microstructural Analysis at Metal/Semiconductor Interface for Ideal Ohmic Contacts." Materia Japan 37, no. 12 (1998): 998. http://dx.doi.org/10.2320/materia.37.998.

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Gao, Xian, Ji Long Tang, Dan Fang, Fang Chen, Shuang Peng Wang, Hai Feng Zhao, Xuan Fang, et al. "The Electrical Characteristics of GaAs-MgO Interfaces of GaAs MIS Schottky Diodes." Advanced Materials Research 1118 (July 2015): 270–75. http://dx.doi.org/10.4028/www.scientific.net/amr.1118.270.

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Many researches pay attention to the metal-semiconductor interface barrier, due to its effect on device. Deliberate growing an interface layer to affect and improve the quality of device, especially metal-insulator-semiconductor (MIS) structures, arouses wide attention. In this paper, Be-doped GaAs was grown on substrate wafer by molecular beam epitaxy (MBE) on purpose before depositing insulator layer, and then MgO film as the dielectric interface layer of Au/GaAs were deposited using atomic layer deposition (ALD) method. The interface electrical characteristics of the metal-insulator-semiconductor (MIS) structures were investigated in detail. The barrier height and ideal factor of GaAs diode parameters were calculated by means of current-voltage (I-V) characteristics. Experimental result showed that along with the increasing of the doping content, the Schottky barrier height increasing, but the ideal factor decrease at first and then increase.

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Khanna, Shaweta, Arti Noor, Man Singh Tyagi, and Sonnathi Neeleshwar. "Interface States and Barrier Heights on Metal/4H-SiC Interfaces." Materials Science Forum 615-617 (March 2009): 427–30. http://dx.doi.org/10.4028/www.scientific.net/msf.615-617.427.

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Available data on Schottky barrier heights on silicon and carbon rich faces of 4H-SiC have been carefully analyzed to investigate the mechanism of barrier formation on these surfaces. As in case of 3C and 6H-SiC, the barrier heights depend strongly upon method of surface preparation with a considerable scatter in the barrier height for a given metal-semiconductor system. However, for each metal the barrier height depends on the metal work function and strong pinning of the Fermi level has not been observed. The slopes of the linear relation between the barrier heights and metal work functions varies over a wide range from 0.2 to about 0.75 indicating that the density of interface states depends strongly on the method of surface preparation. By a careful examination of the data on barrier heights we could identify a set of nearly ideal interfaces in which the barrier heights vary linearly with metal work function approaching almost to the Schottky limit. The density of interface states for these interfaces is estimated to lie between 4.671012 to 2.631012 states/ cm2 eV on the silicon rich surface and about three times higher on the carbon rich faces. We also observed that on these ideal interfaces the density of interface states was almost independent of metal indicating that the metal induced gap states (MIGS) play no role in determining the barrier heights in metal-4H-SiC Schottky barriers.

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Korošak, Dean, and Bruno Cvikl. "On the role of the interface charge in non-ideal metal–semiconductor contacts." Applied Surface Science 250, no. 1-4 (August 2005): 63–69. http://dx.doi.org/10.1016/j.apsusc.2004.12.024.

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Habersat, Daniel B., Aivars J. Lelis, G. Lopez, J. M. McGarrity, and F. Barry McLean. "On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices." Materials Science Forum 527-529 (October 2006): 1007–10. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1007.

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We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

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Ghazai, Alaa, and Marwaa Mohammed. "(Au, Ag)/Al0.08In0.08Ga0.84N/ (Au, Ag) Metal-semiconductor-metal (MSM) Photodetectors." Iraqi Journal of Nanotechnology, no. 1 (January 23, 2021): 72–79. http://dx.doi.org/10.47758/ijn.vi1.36.

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Metal-semiconductor-metal (MSM) photodetectors (PDs) based on gold and silver (Au, Ag)/Al0.08In0.08Ga0.84N (commercial sample)/ (Au, Ag) have been fabricated and characterized. The effect of annealing temperature of As deposit, 400, 500, and 600 0C for 30 min on the topography and electrical properties of Au contact on Al0.08In0.08Ga0.84N thin film have been characterized and optimized using Current-Voltage (I-V) characteristic. Schottky barrier height (SBH) and ideality factor (n) of Au/ Al0.08In0.08Ga0.84N interface were 1.223 eV and 1.773 at 50 0C annealing temperature for 30 min respectively, and it is found that contact has a high-quality surface. Also, with the same procedure, the effect of annealing time of 15, 30, 45 minutes, and 1 hour have been studied and optimized. The results revealed that the best annealing time is 30 min which has the highest SBH. Au contact compared with Ag contact used to first time as best our knowledge with the optimal condition to select the best metal for MSM photodetectors (PDs). The ideal characterization of Au, Ag/AlInGaN/Au, Ag MSMPDs on Si substrate depend on responsivities of 0.201 and 0.153 A W-1, quantum efficiencies of 71% and 57%, and NEPs of 3.55×10-4 and 1.45×10-3W-1, respectively have been also studied compared. The height SBH and QE for the samples grown on Si was at Au contact which proposed to use in such optoelectronic devices.

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Fraivillig, Jim, Richard Koba, and Kent Hutchings. "Semiconductor-to-metal attachment with silver-filled TPI bondlines." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, HiTEN (January 1, 2015): 000064–67. http://dx.doi.org/10.4071/hiten-session2-paper2_4.

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In the attachment of semiconductor chips and submounts to metal heat sinks, bondlines utilizing silver-filled thermoplastic polyimide adhesive (TPI) are very durable across a wide range of environmental conditions (thermal, physical, chemical, radiation). TPI bondlines can withstand an extreme CTE-mismatch between the laminated materials, and have excellent bonding with adhesive-layer thicknesses down to only a few microns. To provide electrical conductivity and enhance thermal conductivity, the TPI bondline can be compounded with a high concentration of silver particles, and retain durability and adhesion. There are two general constructions of silver-filled TPI bondlines:Bondfoil – thin layers of silver-filled B-staged TPI coatings on either side of a metal carrier/substrate. The thickness of the (cured) TPI coatings would be 2–10 μm/side. TPI-priming (B- or C-staged; partially or fully cured) of a semiconductor surface may be required.TPI coating only – thin layers of silver-filled TPI polymer (1–3 μm/surface; B- or C-staged) on the interface surfaces to be bonded. A minimal amount of A-staged TPI (liquid: polymer in solvent) may be added to the bondline construction to optimize surface wetting during lamination.The ultimate in robustness and thinness, silver-filled TPI bondlines can provide:Continuous operation at 350°C, as well as temporary exposure to 450°C. Thermogravimetric analysis (TGA) of the TPI polymer shows that degradation does not start until well above 500°C. [See opposite.]Thermal shock durability -- the CTE-mismatched TPI bondline between silicon and aluminum can survive repeated thermal shocks with a ΔT of 300–400°C.Thermal impedance as low as 0.06 °C-cm2/W (0.01°C-in2/W) when using a silver-filled TPI bondfoil, and about 0.01 °C-cm2/W (0.002°C-in2/W) when using just silver-filled TPI coatings on the interface surfaces (no metal foil). In both constructions, the thermal impedance includes all interface resistances.Shear strength of 10 MPa to an aluminum surface and 1–2 MPa to silicon. These features make TPI bondlines ideal for demanding, CTE-mismatched semiconductor packages. As opposed to cross-linked thermoset bondlines -- which are brittle, especially when highly filled -- thermoplastic polyimide bondlines remain ductile and resist cracking, even when highly stressed.

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Negrín-Montecelo, Yoel, Martín Testa-Anta, Laura Marín-Caba, Moisés Pérez-Lorenzo, Verónica Salgueiriño, Miguel A. Correa-Duarte, and Miguel Comesaña-Hermo. "Titanate Nanowires as One-Dimensional Hot Spot Generators for Broadband Au–TiO2 Photocatalysis." Nanomaterials 9, no. 7 (July 9, 2019): 990. http://dx.doi.org/10.3390/nano9070990.

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Metal–semiconductor nanocomposites have become interesting materials for the development of new photocatalytic hybrids. Along these lines, plasmonic nanoparticles have proven to be particularly efficient photosensitizers due to their ability to transfer plasmonic hot electrons onto large bandgap semiconductors such as TiO2, thus extending the activity of the latter into a broader range of the electromagnetic spectrum. The extent of this photosensitization process can be substantially enhanced in those geometries in which high electromagnetic fields are created at the metal–semiconductor interface. In this manner, the formation of plasmonic hot spots can be used as a versatile tool to engineer the photosensitization process in this family of hybrid materials. Herein, we introduce the use of titanate nanowires as ideal substrates for the assembly of Au nanorods and TiO2 nanoparticles, leading to the formation of robust hybrids with improved photocatalytic properties. Our approach shows that the correct choice of the individual units together with their rational assembly are of paramount importance in the development of complex nanostructures with advanced functionalities.

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Sands, T. "Heteroepitaxy of stable metallic phases on GaAs: identification of candidate phases by TEM." Proceedings, annual meeting, Electron Microscopy Society of America 45 (August 1987): 322–25. http://dx.doi.org/10.1017/s0424820100126421.

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The structural perfection and thermal stability of epitaxical silicide contacts provides silicon technology with the potential for three-dimensional device integration as well as novel discrete device structures. Furthermore, the detrimental effects of grain boundaries on film resistivity and interdiffusion are eliminated in these epitaxical contact structures. Similar benefits for GaAs technology may be expected if stable metallic phases that grow epitaxically on GaAs can be identified. Such structures would also represent the ideal configuration for understanding the relationship between interface structure and electronic transport properties of metal/compound semiconductor systems.The search for candidate metallic phases can be simplified by considering only those phases that are cubic with lattice parameters compatible with aо (GaAs) = 0.565 nm. Of the many cubic structure types, the CsCl structure is the most common among the transition metal MGa phases.

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Weng, Ming Hung, Rajat Mahapatra, Nicolas G. Wright, and Alton B. Horsfall. "Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide." Materials Science Forum 600-603 (September 2008): 771–74. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.771.

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The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.

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Birant, Gizem, Jorge Mafalda, Romain Scaffidi, Jessica de Wild, Dilara Gokcen Buldu, Thierry Kohl, Guy Brammertz, Marc Meuris, Jef Poortmans, and Bart Vermang. "Rear surface passivation of ultra-thin CIGS solar cells using atomic layer deposited HfOx." EPJ Photovoltaics 11 (2020): 10. http://dx.doi.org/10.1051/epjpv/2020007.

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In this work, hafnium oxide layer is investigated as rear surface passivation layer for ultra-thin (550 nm) CIGS solar cells. Point contact openings in the passivation layer are realized by spin-coating potassium fluoride prior to absorber layer growth. Contacts are formed during absorber layer growth and visualized with scanning electron microscopy (SEM). To assess the passivating qualities, HfOx was applied in a metal-insulator-semiconductor (MIS) structure, and it demonstrates a low interface trap density in combination with a negative density of charges. Since we used ultra-thin devices that are ideal to probe improvements at the rear, solar cell results indicated improvements in all cell parameters by the addition of 2 nm thick HfOx passivation layer with contact openings.

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Grieb, Michael, Dethard Peters, Anton J. Bauer, Peter Friedrichs, and Heiner Ryssel. "Influence of the Oxidation Temperature and Atmosphere on the Reliability of Thick Gate Oxides on the 4H-SiC C(000-1) Face." Materials Science Forum 600-603 (September 2008): 597–602. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.597.

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The reliability of thermal oxides grown on n-type 4H-SiC C(000-1) face wafer has been investigated. In order to examine the influence of different oxidation atmospheres and temperatures on the reliability, metal-oxide-semiconductor capacitors were manufactured and the different oxides were characterized by C-V measurements and constant-current-stress. The N2O-oxides show the smallest flat band voltage shift compared to the ideal C-V curve and so the lowest number of effective oxide charges. They reveal also the lowest density of interface states in comparison to the other oxides grown on the C(000-1) face, but it is still higher than the best oxides on the Si(000-1) face. Higher oxidation temperatures result in smaller flat band voltage shifts and lower interface state densities. Time to breakdown measurements show that the charge-to-breakdown value of 63% cumulative failure for the N2O-oxide on the C(000-1) face is more than one order of magnitude higher than the highest values measured on the Si(000-1) face. Therefore it can be concluded that a smaller density of interface states results in a higher reliability of the oxide.

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Xue, Shirui, Sicheng Cao, Zhaoling Huang, Daoguo Yang, and Guoqi Zhang. "Improving Gas-Sensing Performance Based on MOS Nanomaterials: A Review." Materials 14, no. 15 (July 30, 2021): 4263. http://dx.doi.org/10.3390/ma14154263.

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In order to solve issues of air pollution, to monitor human health, and to promote agricultural production, gas sensors have been used widely. Metal oxide semiconductor (MOS) gas sensors have become an important area of research in the field of gas sensing due to their high sensitivity, quick response time, and short recovery time for NO2, CO2, acetone, etc. In our article, we mainly focus on the gas-sensing properties of MOS gas sensors and summarize the methods that are based on the interface effect of MOS materials and micro–nanostructures to improve their performance. These methods include noble metal modification, doping, and core-shell (C-S) nanostructure. Moreover, we also describe the mechanism of these methods to analyze the advantages and disadvantages of energy barrier modulation and electron transfer for gas adsorption. Finally, we put forward a variety of research ideas based on the above methods to improve the gas-sensing properties. Some perspectives for the development of MOS gas sensors are also discussed.

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Shearer, Catherine. "Microstructure stability of TLPS interconnects in high operating temperature applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, HiTEN (July 1, 2017): 000226–33. http://dx.doi.org/10.4071/2380-4491.2017.hiten.226.

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Abstract Interconnect materials for high operating temperature applications are becoming a limiting factor within the chain of materials. While materials such as capacitor dielectrics, semiconductor platforms (e.g. SiC), and baseplate materials (e.g. SiN composites) have paved a pathway to deploying electronics in high operating temperature applications, interconnect materials are a clearly identified weak link. As is often the case in advancements in technology, the materials technologies that were the bottlenecks to advancement give way to new solutions that create new bottlenecks in the material supply chain. Rather than a fluid march towards advancements in new frontiers in electronics, the high operating temperature sphere, like much of advanced electronic, suffers from a ‘slip-fault’ mode of development where advances occur in one segment while others lag behind creating drag on implementation. For high operating temperature applications the available interconnect solutions are becoming the jarring stop to the smooth tectonic shift. Current solutions are diverse: high-lead, gold-based, and nano-sintering and its hybrids, but none are ideal. Even disregarding he toxicity of lead and the ongoing limbo of its regulatory status, the operating temperatures of the high-lead solders are on the low end of the requirements for future harsh environment electronics applications; whereas, the gold and nano-based alternatives have significant cost barriers - either at from the constituent materials perspective or the required investment in new processes. There is also the concern about the assessment of the action of nanomaterials in the waste stream due to their fundamentally different surface reactivity in a variety of situations. Reliance on conventional, solder-type interconnection structures, regardless of composition, introduces the perennial problem of the growth of the interfacial phases due to the essentially unlimited volume of the bulk solder material. The changes in the interfacial structure with additional thermal work - as is provided by high operating temperature applications - creates an environment that is ripe for growth of a variety of failure mechanisms. These failure mechanisms are often related to the uncontrolled laminar growth of intermetallic phases at the interfaces and the mechanical characteristics of these intermetallic phases in comparison with the materials joined and the bulk constituent material of the solder. An alternative class of interconnect materials, transient liquid phase sintering (TLPS) pastes, introduce a joint microstructure that is homogeneous throughout. The interfacial metallurgical reactions with the solderable surfaces are fundamentally similar to those that occur throughout the bulk of the joint. A reactant metal is included in the composition. This reactant metal, most often copper, reacts with and converts the bulk tin in the bulk of the solder interconnect to alloy structures with melting points well above the operating temperatures currently contemplated. At the conclusion of the joining process, which is generally a near drop-in for existing solder reflow processes, there is no large source of unreacted metal (e.g. Sn) that can continue to drive major microstructural changes with the continued thermal work provided by the application environment. For this reason the joints are homogeneous and do not have the free reactants necessary to drive substantial changes in joint morphology during cycling and use conditions. In this paper, we will explore the differences between TLPS joints and solder-type joints with the anticipated thermal work that would be introduced in a high operating temperature environment.

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Mönch, Winfried. "Electronic Properties of Ideal and Interface-Modified Metal-Semiconductor Contacts." MRS Proceedings 378 (1995). http://dx.doi.org/10.1557/proc-378-811.

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AbstractBarrier heights in metal-semiconductor contacts may be modified by interlayers. The effects of atomic interlayers are due to interface dipoles. With the restriction to nearest-neighbor interactions and monovalent interlayer atoms, they may be described as interface molecules which consist of an interlayer and a substrate atom. If the interlayers are thicker than a few atomic layers their two interfaces with the metal and with the semiconductor will be non-interacting. Both types of interfaces are described by the model that interface-induced gap states determine the alignment of the bands and the electronegativity difference describes the charge transfer across the interface. The present paper discusses and analyzes experimental data for H-modified diamond and silicon, Al/Si/GalnP, and metal/ Si3N4/Si Schottky contacts.

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Waddill, G. D., I. M. Vitomirov, C. M. Aldao, Steven G. Anderson, C. Capasso, and J. H. Weaver. "Metal-Semiconductor Interfaces with Novel Structural and Electrical Properties: Metal Cluster Deposition." MRS Proceedings 148 (1989). http://dx.doi.org/10.1557/proc-148-121.

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Studies of Schottky barrier formation at metal-semiconductor interfaces have been complicated by the difficulty of producing an abrupt, “ideal” interface. The commonly used methods of producing metal-semiconductor interfaces result in complex interfacial morphology and chemistry including substrate disruption, atomic interdiffusion, alloy or compound formation, and substrate surface structural changes. The complicated nature of such interfaces makes it difficult from a fundamental point of view to identify the mechanisms dominating Schottky barrier formation for the various stages of development.

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Levi, A. F. J., R. T. Tung, J. L. Batstone, J. M. Gibson, M. Anzlowar, and A. Chantre. "Electron Transport Through Epitaxial Metal/Semiconductor Heterostructures." MRS Proceedings 77 (1986). http://dx.doi.org/10.1557/proc-77-271.

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ABSTRACTAbrupt, epitaxial silicide/silicon heterostructures may be grown so that, for the first time, the physics of electron transport across near perfect, single crystal, metal/semiconductor interfaces may be probed experimentally. Transport measurements through type-A and -B oriented NiSi2 layers on Si(111) substrates have revealed Schottky barrier heights differing by 140 meV. In this paper we present results of experiments designed to explore the possible role of bulk and interface defects in determining the potential barrier at these near ideal epitaxial metal-semiconductor contacts. We have found little evidence for the presence of defects and the Schottky barrier is insensitive to details of the microscopic interfacial perfection. By contrast we find that both the electrical quality and magnitude of the barrier occurring at the NiSi2 /Si(100) heterojunction are dependent upon details of the microscopic interfacial perfection.

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Aldegunde, Manuel, Steven P. Hepplestone, Peter V. Sushko, and Karol Kalna. "Multi-Scale Simulation of Transport via a Mo/n+-GaAs Schottky Contact." MRS Proceedings 1553 (2013). http://dx.doi.org/10.1557/opl.2013.1057.

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ABSTRACTA multi-scale modeling of electron transport via a metal-semiconductor interface is carried out by coupling ab initio calculations with three-dimensional finite element ensemble Monte Carlo simulations. The results for the Mo/GaAs (001) interface show that variations of the electronic properties with the distance from the interface have a strong impact on the transport characteristics. In particular, the calculated tunneling barrier differs dramatically from that of the ideal Schottky model of an abrupt metal-semiconductor interface. The band gap narrowing near the interface lowers resistivity by more than one order of magnitude: from 2.1×10-8 Ωcm² to 4.7×10-10 Ωcm². The dependence of the electron effective mass from the distance to the interface also plays an important role bringing resistivity to 7.9×10-10 Ωcm².

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Rahman, Mosiur, T. S. Kalkur, Shunming Sun, Fred P. Gnadinger, David Dalton, Daesig Kim, Viorel Olariu, and David Klingensmith. "Characterization of MFMIS and MFIS Structures for Non-volatile Memory Applications." MRS Proceedings 830 (2004). http://dx.doi.org/10.1557/proc-830-d3.2.

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ABSTRACTTo eliminate the interface reaction problems between ferroelectric and semiconductor in MFS (metal-ferroelectric-semiconductor) as well as ferroelectric and insulator in MFIS (metal-ferroelectric-insulator-semiconductor) structures, a gate layer sandwich of the MFMIS (metal-ferroelectric-metal-insulator-semiconductor) is proposed. This structure consists of Pt-SBT-Pt-ZrO2-SiO2-Si stacks. In the MFMIS structure the MIS capacitor is separated from the ferroelectric MFM capacitor through a metal as a floating gate. Therefore, the MIS capacitor with SiO2 and ZrO2 as an insulator with excellent interface properties can be used and MFM acts as an ideal ferroelectric capacitor. As MFMIS is a series combination of MFM and MIS capacitors, it behaves as a voltage divider. The gate voltage is divided according to the capacitance ratio of the MIS and MFM structures. Since the fabricated devices have access to the floating gate, characteristics of the MFM and MIS capacitors can be determined independently to compare the characteristics of the MFMIS structure as a single capacitor. The ferroelectric can be programmed in one direction and the field effect due to that can be analyzed. The MFMIS structures showed significant memory window due to the polarization of ferroelectric thin films but the retention time was short. The short retention time was due to the depolarization field being larger than coercive field of the ferroelectric thin film.

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Sullivan, J. P., R. T. Tung, F. Schrey, and W. R. Graham. "The Fabrication of NiSi2/Si(100) Interfaces with Controlled Morphologies." MRS Proceedings 281 (1992). http://dx.doi.org/10.1557/proc-281-623.

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ABSTRACTThe morphology and defect structures associated with thin NiSi2 films prepared on Si(100) were investigated. Facets were found to be a common defect structure at the interface unless stoichiometric co-deposition of Ni and Si was performed. Annealing thin, uniform NiSi2 layers prepared by stoichiometric co-deposition to temperatures ≥ 700°C yielded epitaxial films of high crystalline perfection. Films in which the deposition was off-stoichiometric exhibited a variety of defect structures. In addition to facets at the interface, networks of meandering micro-twins or stacking faults were observed in highly Ni-rich films, while pinholes were observed in Si-rich films. Facets at the interface were found to be eliminated by annealing at temperatures ≥ - 750°C, indicating that the planar NiSi2/Si(100) interface is energetically stable with respect to the formation of NiSi2(111) facets. Through manipulation of the film growth kinetics, NiSi2/Si(100) interfaces with arbitrary facet densities were produced. Partially faceted NiSi2/Si(100) interfaces represent ideal experimental systems for revealing the effects of Schottky barrier inhomogeneity on the electrical measurements of metal/semiconductor contacts.

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Cova, P., A. Singh, R. A. Masut, and J. F. Currie. "A New Method for the Simultaneous Analysis of I-V/T and C-V/T Measurements of an Au/P-Inp Epitaxial Schottky Diode." MRS Proceedings 318 (1993). http://dx.doi.org/10.1557/proc-318-507.

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ABSTRACTWe have developed a new approach to analyze the current- voltage (I-V) characteristics of a tunnel metal-interface layer - semiconductor (MIS) diode which takes into account the voltage dependence of interface states distribution (Nss) and the barrier lowering due to image force. Our method of analysis uses simultaneously the I-V/T and C-V/T data to determine the characteristic parameters of an MIS diodes and is ideal for new epitaxial materials and devices where the carrier density is not known precisely before hand. The experimental verification of our approach to analyze the nonideal I-V/T and C-V/T characteristics of MIS diodes was done by comparing the values of Nss extracted from the room temperature forward I-V characteristics of a p-InP/Au MIS diodes with those obtained by the multi-frequency admittance method. Excellent agreement between the values of Nss determined by two different techniques strongly support the validity of our theoretical expression for the I-V/T characteristics and the method of analysis. Our results indicate that the interface layer thermionic emission was clearly the dominant mechanism of the forward current transport in epitaxial Au/p-InP MIS diodes over the temperature range 200–393 K. The transmission coefficient of the interface-layer obtained from the reverse I-V characteristics has a value of 1.43×10−3 (±7%).

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Dauplaise, H. M., A. Davis, K. Vaccaro, W. D. Waters, S. M. Spaziani, E. A. Martin, and J. P. Lorenzo. "Analysis of InP Passivated with Thiourea/Ammonia Solutions and Thin CdS Films." MRS Proceedings 448 (1996). http://dx.doi.org/10.1557/proc-448-69.

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AbstractThe use of thiourea/ammonia pre-treatments on (100) InP, followed by chemical bath deposition (CBD) of CdS thin films (∼ 30 Å), with low-temperature, low-pressure chemical vapor deposited SiO2 has been shown to produce metal-insulator-semiconductor (MIS) samples with near-ideal capacitance-voltage (C-V) response. Here, we report on x-ray photoelectron spectroscopy (XPS) analysis of the near-surface of InP following pre-treatment and CdS deposition. The pre-treatment was shown by XPS to form an indium sulfide layer and effectively remove native oxides from the InP surface. The subsequent deposition of CdS on a sulfur-passivated surface forms a stable layer which protects the substrate from oxidation during SiO2 chemical vapor deposition. MIS samples prepared using the pre-treatment without CdS deposition showed improved C- V response, while samples prepared with both the pre-treatment and CdS deposition showed a dramatic reduction in the density of interface states.

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Rahimi, Ronak, Srikanth Raghavan, N. P. Shelton, Dinesh Penigalapati, Andrew Balling, Andrew A. Woodworth, Tobias Denig, Charter D. Stinespring, and D. Korakakis. "Investigation of Nano-thin β-SiC Layers for Chemical Sensors." MRS Proceedings 1056 (2007). http://dx.doi.org/10.1557/proc-1056-hh08-05.

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ABSTRACTSilicon Carbide possesses a combination of properties that make it ideal for use in electronics. Its high values of electric breakdown field, melting point and saturated electron drift velocity have attracted the attention of the semiconductor community. Although the interest in β-SiC/Si devices has intensified in recent years [1-2], little focus has been given to the study of nano-thin film devices. Monocrystalline nano-thin β-SiC films have been reproducibly grown on Si (100) by Gas Source Molecular Beam Epitaxy (GSMBE). Auger Electron Spectroscopy and Reflection High Energy Electron Diffraction characterization have confirmed a growth consistent of β-SiC/Si. Scanning Electron Microscopy (SEM) and Atomic Force Microscopy (AFM) characterization has determined film thicknesses of 30nm. These nano-films have been used in the fabrication of Metal-Semiconductor-Metal (MSM) devices formed from aluminum Schottky contacts. Under electrical characterization, these MSM devices have exhibited unique properties in that the dominant conduction path does not occur at the β-SiC/Si interface [3] as previously reported, but within the entire β-SiC layer. It is proposed that the device is isolated from the Silicon substrate and due to the nano-thin β-SiC films used in this work the differentiation between surface and ‘bulk’ is not clear. Results obtained through chemical experimentation have indicated that conduction is largely dependent on the surface condition of the device. This suggests the possibility for nano-thin, surface-like, β-SiC films to be used in chemical agent sensors.

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Rubini, S., E. Pelucchi, M. Lazzarino, D. Kumar, A. Franciosi, C. Berthod, N. Binggeli, and A. Baldereschi. "Ideal unreactive metal/semiconductor interfaces: The case ofZn/ZnSe(001)." Physical Review B 63, no. 23 (May 18, 2001). http://dx.doi.org/10.1103/physrevb.63.235307.

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Zhang, Xiankun, Baishan Liu, Li Gao, Huihui Yu, Xiaozhi Liu, Junli Du, Jiankun Xiao, et al. "Near-ideal van der Waals rectifiers based on all-two-dimensional Schottky junctions." Nature Communications 12, no. 1 (March 9, 2021). http://dx.doi.org/10.1038/s41467-021-21861-6.

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AbstractThe applications of any two-dimensional (2D) semiconductor devices cannot bypass the control of metal-semiconductor interfaces, which can be severely affected by complex Fermi pinning effects and defect states. Here, we report a near-ideal rectifier in the all-2D Schottky junctions composed of the 2D metal 1 T′-MoTe2 and the semiconducting monolayer MoS2. We show that the van der Waals integration of the two 2D materials can efficiently address the severe Fermi pinning effect generated by conventional metals, leading to increased Schottky barrier height. Furthermore, by healing original atom-vacancies and reducing the intrinsic defect doping in MoS2, the Schottky barrier width can be effectively enlarged by 59%. The 1 T′-MoTe2/healed-MoS2 rectifier exhibits a near-unity ideality factor of ~1.6, a rectifying ratio of >5 × 105, and high external quantum efficiency exceeding 20%. Finally, we generalize the barrier optimization strategy to other Schottky junctions, defining an alternative solution to enhance the performance of 2D-material-based electronic devices.

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Journal articles on the topic 'Ideal metal-semiconductor interface'

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