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Relevant bibliographies by topics / IEEE 754 standard

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Academic literature on the topic 'IEEE 754 standard'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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Journal articles on the topic "IEEE 754 standard"

1

Hough, David G. "The IEEE Standard 754: One for the History Books." Computer 52, no. 12 (2019): 109–12. http://dx.doi.org/10.1109/mc.2019.2926614.

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Romera, M., G. Pastor, A. B. Orue, A. Martin, M. F. Danca, and F. Montoya. "A Method to Solve the Limitations in Drawing External Rays of the Mandelbrot Set." Mathematical Problems in Engineering 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/105283.

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The external rays of the Mandelbrot set are a valuable graphic tool in order to study this set. They are drawn using computer programs starting from the Böttcher coordinate. However, the drawing of an external ray cannot be completed because it reaches a point from which the drawing tool cannot continue drawing. This point is influenced by the resolution of the standard for floating-point computation used by the drawing program. The IEEE 754 Standard for Floating-Point Arithmetic is the most widely used standard for floating-point computation, and we analyze the possibilities of the quadruple

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Deokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics." International Journal for Research in Applied Science and Engineering Technology 9, no. VI (2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.

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The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of mul

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Ermilov, Sergey I. "Comparison of Universal Number with the IEEE 754 Standard with Respect to Validation Criterion." Vestnik MEI 3, no. 3 (2018): 109–15. http://dx.doi.org/10.24160/1993-6982-2018-3-109-115.

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Cawley, Gavin C. "On a Fast, Compact Approximation of the Exponential Function." Neural Computation 12, no. 9 (2000): 2009–12. http://dx.doi.org/10.1162/089976600300015033.

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Recently Schraudolph (1999) described an ingenious, fast, and compact approximation of the exponential function through manipulation of the components of a standard (IEEE-754 (IEEE, 1985)) floating-point representation. This brief note communicates a recoding of this procedure that overcomes some of the limitations of the original macro at little or no additional computational expense.

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Hiromoto, Masayuki, Hiroyuki Ochi, and Yukihiro Nakamura. "An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA." IPSJ Transactions on System LSI Design Methodology 2 (2009): 103–13. http://dx.doi.org/10.2197/ipsjtsldm.2.103.

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Xiao, Feibao, Feng Liang, Bin Wu, Junzhe Liang, Shuting Cheng, and Guohe Zhang. "Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and SquareRoot." Electronics 9, no. 10 (2020): 1622. http://dx.doi.org/10.3390/electronics9101622.

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As a substitute for the IEEE 754-2008 floating-point standard, Posit, a new kind of number system for floating-point numbers, was put forward recently. Hitherto, some studies have proven that Posit is a better floating-point style than IEEE 754-2008 in some fields. However, most of these studies presented the advantages of Posit from the arithmetical aspect, but none of them suggested it had a better hardware implementation than that of IEEE 754-2008. In this paper, we propose several hardware implementations that contain the Posit adder/subtractor, multiplier, divider, and square root. Our go

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Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floati

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Cheng, Harry H. "Scientific Computing in the CHProgramming Language." Scientific Programming 2, no. 3 (1993): 49–75. http://dx.doi.org/10.1155/1993/261875.

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We have developed a general-purpose block-structured interpretive programming Ianguage. The syntax and semantics of this language called CHare similar to C. CHretains most features of C from the scientific computing point of view. In this paper, the extension of C to CHfor numerical computation of real numbers will be described. Metanumbers of −0.0, 0.0, Inf, −Inf, and NaN are introduced in CH. Through these metanumbers, the power of the IEEE 754 arithmetic standard is easily available to the programmer. These metanumbers are extended to commonly used mathematical functions in the spirit of th

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Rukundo, Olivier. "Effects of Improved-Floor Function on the Accuracy of Bilinear Interpolation Algorithm." Computer and Information Science 8, no. 4 (2015): 1. http://dx.doi.org/10.5539/cis.v8n4p1.

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In this study, the standard IEEE 754–2008 and modulo-based floor functions for rounding non-integers have been presented. Their effects on the accuracy of the bilinear interpolation algorithm have been demonstrated. The improved-floor uses the modulo operator in an effort to make each non-integer addend an integer when the remainder between the multiplicative inverse of the fractional factor and the numerator is greater than zero. The experiments demonstrated relatively positive effects with the improved-floor function and the alternativeness to the standard round function.

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Dissertations / Theses on the topic "IEEE 754 standard"

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Nilsson, William, and Jakob Arvidsson. "An evaluation of a new standard for floating point precision : A quantitative comparison of Posit and IEEE 754 Float." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-302142.

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Posit is a new floating point precision representation that has been developed as an alternative to the existing IEEE 754 floating point standard. Prior studies have found several use-cases for posit, but also potential drawbacks. This thesis examines some of the potential drawbacks concerning the precision of posit’s floating point representation. The study is conducted through comparisons of 32-bit posit with 32-bit IEEE 754 for a limited set of operations and algorithms. The result shows that posit is the most accurate at values near one, progressively losing accuracy as the absolute value

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Panhaleux, Adrien. "Contributions à l'arithmétique flottante : codages et arrondi correct de fonctions algébriques." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2012. http://tel.archives-ouvertes.fr/tel-00744373.

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Une arithmétique sûre et efficace est un élément clé pour exécuter des calculs rapides et sûrs. Le choix du système numérique et des algorithmes arithmétiques est important. Nous présentons une nouvelle représentation des nombres, les "RN-codes", telle que tronquer un RN-code à une précision donnée est équivalent à l'arrondir au plus près. Nous donnons des algorithmes arithmétiques pour manipuler ces RN-codes et introduisons le concept de "RN-code en virgule flottante." Lors de l'implantation d'une fonction f en arithmétique flottante, si l'on veut toujours donner le nombre flottant le plus pr

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Martin-Dorel, Erik. "Contributions à la vérification formelle d'algorithmes arithmétiques." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2012. http://tel.archives-ouvertes.fr/tel-00745553.

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L'implantation en Virgule Flottante (VF) d'une fonction à valeurs réelles est réalisée avec arrondi correct si le résultat calculé est toujours égal à l'arrondi de la valeur exacte, ce qui présente de nombreux avantages. Mais pour implanter une fonction avec arrondi correct de manière fiable et efficace, il faut résoudre le "dilemme du fabricant de tables" (TMD en anglais). Deux algorithmes sophistiqués (L et SLZ) ont été conçus pour résoudre ce problème, via des calculs longs et complexes effectués par des implantations largement optimisées. D'où la motivation d'apporter des garanties fortes

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Yang, Chih-Pin, and 楊志斌. "Design and Analysis of an IEEE Standard 754 Reciprocal Square Root Arithmetic Unit." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/57237407302675219024.

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Books on the topic "IEEE 754 standard"

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Institute Of Electrical and Electronics Engineers. IEEE 754-2008: IEEE Standard for Floating-Point Arithmetic. IEEE, 2008.

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Rajanala, Arunkumar V. IEEE 754 single precision standard compatible floating point processor implemented using silicon compiler technology. 1988.

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Book chapters on the topic "IEEE 754 standard"

1

Prakash Rao, R., P. Hara Gopal Mani, K. Ashok Kumar, and B. Indira Priyadarshini. "Implementation of the Standard Floating Point DWT Using IEEE 754 Floating Point MAC." In Intelligent Communication Technologies and Virtual Mobile Networks. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-28364-3_13.

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Navabi, Zainalabedin. "Standard IEEE Test Access Methods." In Digital System Test and Testable Design. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-7548-5_8.

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3

"Machine Numbers and the IEEE 754 Floating-Point Standard." In Introduction to Scientific and Technical Computing. CRC Press, 2016. http://dx.doi.org/10.1201/9781315382395-10.

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"Machine Numbers and the IEEE 754 Floating-Point Standard." In Introduction to Scientific and Technical Computing. CRC Press, 2016. http://dx.doi.org/10.1201/9781315382395-3.

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Vestias, Mário Pereira. "Decimal Hardware Multiplier." In Encyclopedia of Information Science and Technology, Fourth Edition. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2255-3.ch400.

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IEEE-754 2008 has extended the standard with decimal floating point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal Multiplication is a fundamental operation utilized in many algorithms and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This article focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

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Vestias, Mário Pereira. "Decimal Hardware Multiplier." In Advanced Methodologies and Technologies in Artificial Intelligence, Computer Simulation, and Human-Computer Interaction. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7368-5.ch054.

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IEEE-754 2008 has extended the standard with decimal floating-point arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations without being subject to errors caused by decimal to binary conversions. Decimal multiplication is a fundamental operation utilized in many algorithms, and it is referred in the standard IEEE-754 2008. Decimal multiplication has an inherent difficulty associated with the representation of decimal numbers using a binary number system. Both bit and digit carries, as well as invalid results, must be considered in decimal multiplication in order to produce the correct result. This chapter focuses on algorithms for hardware implementation of decimal multiplication. Both decimal fixed-point and floating-point multiplication are described, including iterative and parallel solutions.

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Posadas, Hector, Juan Castillo, David Quijano, Victor Fernandez, Eugenio Villar, and Marcos Martinez. "SystemC Platform Modeling for Behavioral Simulation and Performance Estimation of Embedded Systems." In Behavioral Modeling for Embedded Systems and Technologies. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-750-8.ch009.

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Currently, embedded systems make use of large, multiprocessing systems on chip integrating complex application software running on the different processors in close interaction with the application-specific hardware. These systems demand new modeling, simulation, and performance estimation tools and methodologies for system architecture evaluation and design exploration. Recently approved as IEEE 1666 standard, SystemC has proven to be a powerful language for system modeling and simulation. In this chapter, SCoPE, a SystemC framework for platform modeling, SW source-code behavioral simulation and performance estimation of embedded systems is presented. Using SCoPE, the application SW running on the different processors of the platform can be simulated efficiently in close interaction with the rest of the platform components. In this way, fast and sufficiently accurate performance metrics are obtained for design-space exploration.

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Conference papers on the topic "IEEE 754 standard"

1

Chen, Xi, Fei Xiang, and Lili Zhang. "Optimal design of double-precision chaotic signal generators based on IEEE-754 standard." In 2012 IEEE International Conference on Automation and Logistics (ICAL). IEEE, 2012. http://dx.doi.org/10.1109/ical.2012.6308251.

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Rao, R. Prakash, N. Dhanunjaya Rao, K. Naveen, and P. Ramya. "IMPLEMENTATION OF THE STANDARD FLOATING POINT MAC USING IEEE 754 FLOATING POINT ADDER." In 2018 Second International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2018. http://dx.doi.org/10.1109/iccmc.2018.8487626.

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Rahman, Atul, Abdullah-Al-Kafi, Mr Khalid, A. T. M. Saiful Islam, and Mahmudur Rahman. "Optimized hardware architecture for implementing IEEE 754 standard double precision floating point adder/subtractor." In 2014 17th International Conference on Computer and Information Technology (ICCIT). IEEE, 2014. http://dx.doi.org/10.1109/iccitechn.2014.7073135.

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San, Aung Myo, and A. N. Yakunin. "Hardware Implementation of Floating-point Operating Devices by Using IEEE-754 Binary Arithmetic Standard." In 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2019. http://dx.doi.org/10.1109/eiconrus.2019.8656775.

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Ternovoy, E., Mikhail G. Popov, Dmitrii V. Kaleev, Yurii V. Savchenko, and Alexey L. Pereverzev. "Comparative Analysis of Floating-Point Accuracy of IEEE 754 and Posit Standards." In 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2020. http://dx.doi.org/10.1109/eiconrus49466.2020.9039521.

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