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Relevant bibliographies by topics / IEEE floating-point

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Academic literature on the topic 'IEEE floating-point'

Author: Grafiati

Published: 5 June 2025

Last updated: 24 June 2025

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Journal articles on the topic "IEEE floating-point"

1

Advanced Micro Devices. "IEEE floating-point format." Microprocessors and Microsystems 12, no. 1 (1988): 13–23. http://dx.doi.org/10.1016/0141-9331(88)90031-2.

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Boldo, Sylvie, Claude-Pierre Jeannerod, Guillaume Melquiond, and Jean-Michel Muller. "Floating-point arithmetic." Acta Numerica 32 (May 2023): 203–90. http://dx.doi.org/10.1017/s0962492922000101.

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Floating-point numbers have an intuitive meaning when it comes to physics-based numerical computations, and they have thus become the most common way of approximating real numbers in computers. The IEEE-754 Standard has played a large part in making floating-point arithmetic ubiquitous today, by specifying its semantics in a strict yet useful way as early as 1985. In particular, floating-point operations should be performed as if their results were first computed with an infinite precision and then rounded to the target format. A consequence is that floating-point arithmetic satisfies the ‘standard model’ that is often used for analysing the accuracy of floating-point algorithms. But that is only scraping the surface, and floating-point arithmetic offers much more.In this survey we recall the history of floating-point arithmetic as well as its specification mandated by the IEEE-754 Standard. We also recall what properties it entails and what every programmer should know when designing a floating-point algorithm. We provide various basic blocks that can be implemented with floating-point arithmetic. In particular, one can actually compute the rounding error caused by some floating-point operations, which paves the way to designing more accurate algorithms. More generally, properties of floating-point arithmetic make it possible to extend the accuracy of computations beyond working precision.

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Boldo, Sylvie, Claude-Pierre Jeannerod, Guillaume Melquiond, and Jean-Michel Muller. "Floating-point arithmetic." Acta Numerica 32 (May 1, 2023): 203–90. https://doi.org/10.1017/s0962492922000101.

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Floating-point numbers have an intuitive meaning when it comes to physics-based numerical computations, and they have thus become the most common way of approximating real numbers in computers. The IEEE-754 Standard has played a large part in making floating-point arithmetic ubiquitous today, by specifying its semantics in a strict yet useful way as early as 1985. In particular, floating-point operations should be performed as if their results were first computed with an infinite precision and then rounded to the target format. A consequence is that floating-point arithmetic satisfies the 'standard model' that is often used for analysing the accuracy of floating-point algorithms. But that is only scraping the surface, and floating-point arithmetic offers much more.In this survey we recall the history of floating-point arithmetic as well as its specification mandated by the IEEE-754 Standard. We also recall what properties it entails and what every programmer should know when designing a floating-point algorithm. We provide various basic blocks that can be implemented with floating-point arithmetic. In particular, one can actually compute the rounding error caused by some floating-point operations, which paves the way to designing more accurate algorithms. More generally, properties of floating-point arithmetic make it possible to extend the accuracy of computations beyond working precision.

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Vinotheni M S and Karthika K. "IMPLEMENTATION OF HIGH PERFORMANCE POSIT-MULTIPLIER." international journal of engineering technology and management sciences 7, no. 4 (2023): 166–76. http://dx.doi.org/10.46647/ijetms.2023.v07i04.026.

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To represent real numbers, practically all computer systems now employ IEEE-754 floating point. Posit has recently been offered as an alternative to IEEE-754 floating point because it provides higher accuracy and a wider dynamic range. The use of not-a-numbers (NaN's) is one of the most common , having too many of them wastes valuable bit patterns in floating point format. As an alternative to floating point, a system known as "Universal Numbers'' or UNUMs was developed. There are three variations of this system, but in terms of hardware compatibility, Type III(POSIT) is the best substitute for floating point. By employing only one bit pattern, this approach overcomes the NaN problem associated with floating point format. An IEEE float FPU requires 22.2% more circuitry than a posit processing unit. The proposed posit multiplier consumes 28.5% less power compared to corresponding IEEE Floating point format. The number of posit operations per second(POPS) handled by a device can be ubstantially larger than the number of FLOPS due to lower power consumption. In this paper, High performance Posit multiplier is implemented and compared with normal Floating point multiplier.

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Popova, Evgenija. "On a Formally Correct Implementation of IEEE Computer Arithmetic." JUCS - Journal of Universal Computer Science 1, no. (7) (1995): 560–69. https://doi.org/10.3217/jucs-001-07-0560.

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IEEE floating-point arithmetic standards 754 and 854 reflect the present state of the art in designing and implementing floating-point arithmetic units. A formalism applied to a standard non-trapping mode floating-point system shows incorrectness of some numeric and non-numeric results. A software emulation of decimal floating-point computer arithmetic supporting an enhanced set of exception symbols is reported. Some implementation details, discussion of some open questions about utility and consistency of the implemented arithmetic with the IEEE Standards are provided. The potential benefit for computations with infinite symbolic elements is outlined.

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Rajaraman, V. "IEEE standard for floating point numbers." Resonance 21, no. 1 (2016): 11–30. http://dx.doi.org/10.1007/s12045-016-0292-x.

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Liu, Hai Ke, Xin Gna Kang, and Shun Wang. "The FPGA Implementation of Single-Precision Floating-Point Adder." Advanced Materials Research 1008-1009 (August 2014): 668–71. http://dx.doi.org/10.4028/www.scientific.net/amr.1008-1009.668.

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A design of single precision floating point adder based on FPGA is presented,by analysing the form of real number formed on IEEE 754 and the storage format of IEEE 754 single-precision floating point,the addition arithmetic process which is easy to realized by using FPGA is put forward,the split of module based on the arithmetic process facilitates the realization of pipeline designing,so the single precision floating point adder introduce by this paper has powerful operation process ability.

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Singamsetti, Mrudula, Sadulla Shaik, and T. Pitchaiah. "Merged Floating Point Multipliers." International Journal of Engineering and Advanced Technology 9, no. 1s5 (2019): 178–82. http://dx.doi.org/10.35940/ijeat.a1042.1291s519.

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Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.

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Mishra, Raj Gaurav, and Amit Kumar Shrivastava. "Implementation of Custom Precision Floating Point Arithmetic on FPGAs." HCTL Open International Journal of Technology Innovations and Research (IJTIR) 1, January 2013 (2013): 10–26. https://doi.org/10.5281/zenodo.160887.

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Floating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in calculations and their hardware utilization for such calculations. In this paper, we have described and evaluated the performance of custom-precision, pipelined, floating point arithmetic core for the conversion to and from signed binary numbers. Then, we have assessed the practical implications of using these algorithms on the Xilinx Spartan 3E FPGA boards.

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Ms., Anuja A. Bhat* &. Prof. Mangesh N. Thakare. "DESIGN OF FLOATING POINT MULTIPLIER BASED ON BOOTH ALGORITHM USING VHDL." INTERNATIONAL JOURNAL OF RESEARCH SCIENCE & MANAGEMENT 4, no. 5 (2017): 55–62. https://doi.org/10.5281/zenodo.572573.

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In this paper, we have presented of High Speed, low power and less delay 32-bit IEEE 754 Floating Point Subtractor and Multiplier using Booth Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as Fast Fourier Transform (FFT). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this research is to reduce delay, power and to increase the speed. The coding is done in VHDL, synthesis and simulation has been done using Xilinx ISE simulator. The modules designed are 24-bit Booth Multiplier for mantissa multiplication in Floating Point Multiplier, 32-bit Floating Point Subtractor and 32-bit Floating Point Multiplier. The Computational delay obtained by Floating Point Subtractor, booth multiplier and floating point multiplier is 16.180nsec, 33.159nsec and 18.623nsec respectively

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Dissertations / Theses on the topic "IEEE floating-point"

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Jain, Sheetal A. 1980. "Low-power single-precision IEEE Floating-point unit." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87426.

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Kolumban, Gaspar. "Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath." Thesis, Linköpings universitet, Datorteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586.

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The ePUMA architecture is a novel master-multi-SIMD DSP platform aimed at low-power computing, like for embedded or hand-held devices for example. It is both a configurable and scalable platform, designed for multimedia and communications. Numbers with both integer and fractional parts are often used in computers because many important algorithms make use of them, like signal and image processing for example. A good way of representing these types of numbers is with a floating-point representation. The ePUMA platform currently supports a fixed-point representation, so the goal of this thesis will be to implement twelve basic floating-point arithmetic operations and two conversion operations onto an already existing datapath, conforming as much as possible to the IEEE 754-2008 standard for floating-point representation. The implementation should be done at a low hardware and power consumption cost. The target frequency will be 500MHz. The implementation will be compared with dedicated DesignWare components and the implementation will also be compared with floating-point done in software in ePUMA. This thesis presents a solution that on average increases the VPE datapath hardware cost by 15% and the power consumption increases by 15% on average. Highest clock frequency with the solution is 473MHz. The target clock frequency of 500MHz is thus not achieved but considering the lack of register retiming in the synthesis step, 500MHz can most likely be reached with this design.

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Tarnoff, David. "Episode 3.07 – Introduction to Floating Point Binary and IEEE 754 Notation." Digital Commons @ East Tennessee State University, 2020. https://dc.etsu.edu/computer-organization-design-oer/23.

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Regardless of the numeric base, scientific notation breaks numbers into three parts: sign, mantissa, and exponent. In this episode, we discuss how the computer stores those three parts to memory, and why IEEE 754 puts them together the way it does.

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Shafer, Lawrence E. "Data Driven Calculations Histories to Minimize IEEE-755 Floating-point Computational Error." NSUWorks, 2004. http://nsuworks.nova.edu/gscis_etd/830.

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The widely implemented and used IEEE-754 Floating-point specification defines a method by which floating-point values may be represented in fixed-width storage. This fixed-width storage does not allow the exact value of all rational values to be stored. While this is an accepted limitation of using the IEEE-754 specification, this problem is compounded when non-exact values are used to compute other values. Attempts to manage this problem have been limited to software implementations that require special programming at the source code level. While this approach works, the problem coder must be aware of the software and explicitly write high-level code specifically referencing it. The entirety of a calculation is not available to the special software so optimum results cannot always be obtained when the range of operand values is large. This dissertation proposes and implements an architecture that uses integer algorithms to minimize precision loss in complex floating-point calculations. This is done using runtime calculation operand values at a simulated hardware level. These calculations are coded in a high-level language such that the coder is not knowledgeable about the details of how the calculation is performed.

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Pathanjali, Nandini. "Pipelined IEEE-754 Double Precision Floating Point Arithmetic Operators on Virtex FPGA’s." University of Cincinnati / OhioLINK, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1017085297.

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Pathanjali, Nandini. "Pipelined IEEE-754 double precision floating point arithmetic operators on virtex FPGA's." Cincinnati, Ohio : University of Cincinnati, 2002. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1017085297.

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Liu, Qiong. "Design of an IEEE double precision floating-point adder/subtractor in GaAs technology /." Title page, table of contents and abstract only, 1995. http://web4.library.adelaide.edu.au/theses/09ENS/09ensl793.pdf.

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Abdel-Hamid, Amr Talaat. "A hierarchical verification of the IEEE-754 table-driven floating-point exponential function using HOL." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ64057.pdf.

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De, Blasio Simone, and Karpers Fredrik Ekstedt. "Comparing the precision in matrix multiplication between Posits and IEEE 754 floating-points : Assessing precision improvement with emerging floating-point formats." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280036.

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IEEE 754 floating-points are the current standard way to represent real values in computers, but there are alternative formats emerging. One of these emerging formats are Posits. The main characteristic of Posit is that the format allows for higher precision than IEEE 754 floats of the same bit size for numbers of magnitude close to 1, but lower precision for numbers of much smaller or bigger magnitude. This study compared the precision between IEEE 754 floating-point and Posit when it comes to matrix multiplication. Different sizes of matrices are compared, combined with different intervals which the values of the matrix elements were generated in. The results showed that Posits outperformed IEEE 754 floating-point numbers in terms of precision when the values are in an interval equal to or larger than [􀀀0:01; 0:01), or equal to or smaller than [􀀀100; 100). Matrix size did not affect this much, unless the intermediate format Quire was used to eliminate rounding error. For almost all other intervals, IEEE 754 floats performed better than Posits. Although most of our results favored IEEE 754 floats, Posits does have a precision benefit if one can be sure the data is within the ideal interval. Maybe Posits still have a role to play in the future of floating-point formats.<br>IEEE 754 flyttal är den nuvarande standarden för att representera reella tal i datorer, men det finns framväxande alternativa format. Ett av dessa nya format är Posit. Huvudkarakteristiken för Posit är att formatet möjliggör för högre precision än IEEE 754 flyttal med samma bitstorlek för värden av magnitud nära 1, men lägre precision för värden av mycket mindre eller större magnitud Denna studie jämförde precisionen mellan flyttal av formaten IEEE 754 och Posit när det gäller matrismultiplikation. Olika storlekar av matriser jämfördes, samt olika intervall av värden som matriselementen genererades i. Resultaten visade att Posits presterade bättre än IEEE 754 flyttal när det gäller precision när värdena är i ett intervall lika med eller större än [􀀀0:01; 0:01), eller lika med eller mindre än [􀀀100; 100). Matrisstorlek hade inte en anmärkningsvärd effekt på detta förutom när formatet Quire användes för att eliminera avrundningsfel. I nästan alla andra intervall presterade IEEE 754 flyttal bättre än Posits. Även om de flesta av våra resultat gynnade IEEE 754-flyttal, har Posits en precisions fördel om man kan vara säker på att värdena ligger inom det ideella intervallet. Posits kan alltså ha en roll att spela i framtiden för representation av flyttal.

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Jourdan, Jingyan. "Custom floating-point arithmetic for integer processors : algorithms, implementation, and selection." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2012. http://tel.archives-ouvertes.fr/tel-00779764.

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Media processing applications typically involve numerical blocks that exhibit regular floating-point computation patterns. For processors whose architecture supports only integer arithmetic, these patterns can be profitably turned into custom operators, coming in addition to the five basic ones (+, -, X, / and √), but achieving better performance by treating more operations. This thesis addresses the design of such custom operators as well as the techniques developed in the compiler to select them in application codes. We have designed optimized implementations for a set of custom operators which includes squaring, scaling, adding two nonnegative terms, fused multiply-add, fused square-add (x*x+z, with z>=0), two-dimensional dot products (DP2), sums of two squares, as well as simultaneous addition/subtraction and sine/cosine. With novel algorithms targeting high instruction-level parallelism and detailed here for squaring, scaling, DP2, and sin/cos, we achieve speedups of up to 4.2x for individual custom operators even when subnormal numbers are fully supported. Furthermore, we introduce the optimizations developed in the ST231 C/C++ compiler for selecting such operators. Most of the selections are achieved at high level, using syntactic criteria. However, for fused square-add, we also enhance the framework of integer range analysis to support floating-point variables in order to prove the required positivity condition z>= 0. Finally, we provide quantitative evidence of the benefits to support this selection of custom operations: on DSP kernels and benchmarks, our approach allows us to be up to 1.59x faster compared to the sole usage of basic ones.

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Books on the topic "IEEE floating-point"

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IEEE Computer Society. Standards Committee. Working group of the Microprocessor Standards Subcommittee. and American National Standards Institute, eds. IEEE standard for binary floating-point arithmetic. Institute of Electrical and Electronics Engineers, Inc, 1985.

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IEEE Computer Society Standards Committee. Working group of the Microprocessor Standards Subcommittee. and American National Standards Institute, eds. IEEE standard for binary floating-point arithmetic. Institute of Electrical and Electronics Engineers, 1985.

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IEEE Computer Society. Technical Committee on Microprocessors and Microcomputers. and IEEE Standards Board, eds. IEEE standard for radix-independent floating-point arithmetic. Institute of Electrical and Electronics Engineers, 1987.

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Center, Langley Research, ed. Defining the IEEE-854 floating-point standard in PVS. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Defining the IEEE-854 floating-point standard in PVS. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Defining the IEEE-854 floating-point standard in PVS. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Defining the IEEE-854 floating-point standard in PVS. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Interpretation of IEEE-854 floating-point standard and definition in the HOL system. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Center, Langley Research, ed. Interpretation of IEEE-854 floating-point standard and definition in the HOL system. National Aeronautics and Space Administration, Langley Research Center, 1995.

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Devices, Analog. 32/40-Bit IEEE floating-point DSP microprocessor ADSP-21020. Analog Devices, 1995.

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Book chapters on the topic "IEEE floating-point"

1

Russinoff, David M. "IEEE-Compliant Square Root." In Formal Verification of Floating-Point Hardware Design. Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-95513-1_7.

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Russinoff, David M. "IEEE-Compliant Square Root." In Formal Verification of Floating-Point Hardware Design. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-87181-9_7.

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Pillai, R. V. K., D. Al-Khalili, and A. J. Al-Khalili. "An IEEE Compliant Floating Point MAF." In VLSI: Systems on a Chip. Springer US, 2000. http://dx.doi.org/10.1007/978-0-387-35498-9_14.

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Torstensson, Olle, and Tjark Weber. "Hammering Floating-Point Arithmetic." In Frontiers of Combining Systems. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-43369-6_12.

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AbstractSledgehammer, a component of the interactive proof assistant Isabelle/HOL, aims to increase proof automation by automatically discharging proof goals with the help of external provers. Among these provers are a group of satisfiability modulo theories (SMT) solvers with support for the SMT-LIB input language. Despite existing formalizations of IEEE floating-point arithmetic in both Isabelle/HOL and SMT-LIB, Sledgehammer employs an abstract translation of floating-point types and constants, depriving the SMT solvers of the opportunity to make use of their dedicated decision procedures for floating-point arithmetic.We show that, by extending Sledgehammer’s translation from the language of Isabelle/HOL into SMT-LIB with an interpretation of floating-point types and constants, floating-point reasoning in SMT solvers can be made available to Isabelle/HOL. Our main contribution is a description and implementation of such an extension. An evaluation of the extended translation shows a significant increase of Sledgehammer’s success rate on proof goals involving floating-point arithmetic.

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Prakash Rao, R., P. Hara Gopal Mani, K. Ashok Kumar, and B. Indira Priyadarshini. "Implementation of the Standard Floating Point DWT Using IEEE 754 Floating Point MAC." In Intelligent Communication Technologies and Virtual Mobile Networks. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-28364-3_13.

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Mueller, Silvia Melitta, and Wolfgang J. Paul. "IEEE Floating Point Standard and Theory of Rounding." In Computer Architecture. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/978-3-662-04267-0_7.

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Titolo, Laura, Mariano Moscato, Marco A. Feliu, Paolo Masci, and César A. Muñoz. "Rigorous Floating-Point Round-Off Error Analysis in PRECiSA 4.0." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-71177-0_2.

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AbstractSmall round-off errors in safety-critical systems can lead to catastrophic consequences. In this context, determining if the result computed by a floating-point program is accurate enough with respect to its ideal real-number counterpart is essential. This paper presents PRECiSA 4.0, a tool that rigorously estimates the accumulated round-off error of a floating-point program. PRECiSA 4.0 combines static analysis, optimization techniques, and theorem proving to provide a modular approach for computing a provably correct round-off error estimation. PRECiSA 4.0 adds several features to previous versions of the tool that enhance its applicability and performance. These features include support for data collections such as lists, records, and tuples; support for recursion schemas; an updated floating-point formalization that closely characterizes the IEEE-754 standard; an efficient and modular analysis of function calls that improves the performances for large programs; and a new user interface integrated into Visual Studio Code.

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Constantinides, George, Fredrik Dahlqvist, Zvonimir Rakamarić, and Rocco Salvia. "Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations." In Computer Aided Verification. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_29.

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AbstractWe present a detailed study of roundoff errors in probabilistic floating-point computations. We derive closed-form expressions for the distribution of roundoff errors associated with a random variable, and we prove that roundoff errors are generally close to being uncorrelated with their generating distribution. Based on these theoretical advances, we propose a model of IEEE floating-point arithmetic for numerical expressions with probabilistic inputs and an algorithm for evaluating this model. Our algorithm provides rigorous bounds to the output and error distributions of arithmetic expressions over random variables, evaluated in the presence of roundoff errors. It keeps track of complex dependencies between random variables using an SMT solver, and is capable of providing sound but tight probabilistic bounds to roundoff errors using symbolic affine arithmetic. We implemented the algorithm in the PAF tool, and evaluated it on FPBench, a standard benchmark suite for the analysis of roundoff errors. Our evaluation shows that PAF computes tighter bounds than current state-of-the-art on almost all benchmarks.

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Shaikh, Shoaib Arif, B. B. Godbole, and Ulhas D. Shiurkar. "IEEE 754-Based Single- and Double-Precision Floating-Point Multiplier Analysis." In Advances in Intelligent Systems and Computing. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9515-5_8.

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Selvi, C. Thirumarai, J. Amudha, and R. S. Sankarasubramanian. "FPGA Based Efficient IEEE 754 Floating Point Multiplier for Filter Operations." In Communications in Computer and Information Science. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_30.

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Conference papers on the topic "IEEE floating-point"

1

Chabini, Noureddine, Marilyn C. Wolf, and Rachid Beguenane. "LUT-Based Multipliers for IEEE-754 Floating Point Arithmetic on FPGAs." In 2024 IEEE 15th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON). IEEE, 2024. http://dx.doi.org/10.1109/uemcon62879.2024.10754781.

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Dinda, Peter, and Conor Hetland. "Do Developers Understand IEEE Floating Point?" In 2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2018. http://dx.doi.org/10.1109/ipdps.2018.00068.

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Rao, R. Prakash, N. Dhanunjaya Rao, K. Naveen, and P. Ramya. "IMPLEMENTATION OF THE STANDARD FLOATING POINT MAC USING IEEE 754 FLOATING POINT ADDER." In 2018 Second International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2018. http://dx.doi.org/10.1109/iccmc.2018.8487626.

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Zaki, Ahmad M., Mohamed H. El-Shafey, Ayman M. Bahaa-Eldin, and Gamal M. Aly. "Accurate floating-point operation using controlled floating-point precision." In 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim). IEEE, 2011. http://dx.doi.org/10.1109/pacrim.2011.6032978.

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Thompson, Ross, and James E. Stine. "An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers." In 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2015. http://dx.doi.org/10.1109/asap.2015.7245706.

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Fandrianto, Jan, and B. Y. Woo. "VLSI floating-point processors." In 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH). IEEE, 1985. http://dx.doi.org/10.1109/arith.1985.6158947.

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Sasidharan, Anjana, and P. Nagarajan. "VHDL implementation of IEEE 754 floating point unit." In 2014 International Conference on Information Communication and Embedded Systems (ICICES). IEEE, 2014. http://dx.doi.org/10.1109/icices.2014.7033999.

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Hickmann, Brian, Andrew Krioukov, Michael Schulte, and Mark Erle. "A parallel IEEE P754 decimal floating-point multiplier." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601916.

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Havaldar, Soumya, and K. S. Gurumurthy. "Design of Vedic IEEE 754 floating point multiplier." In 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2016. http://dx.doi.org/10.1109/rteict.2016.7808008.

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Tenca, Alexandre F. "Multi-operand Floating-Point Addition." In 2009 IEEE 19th IEEE Symposium on Computer Arithmetic (ARITH). IEEE, 2009. http://dx.doi.org/10.1109/arith.2009.27.

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