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Relevant bibliographies by topics / Image processing FPGA / Dissertations / Theses

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Dissertations / Theses on the topic 'Image processing FPGA'

Author: Grafiati

Published: 5 June 2025

Last updated: 1 August 2025

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1

Zhao, Jin. "Video/Image Processing on FPGA." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/503.

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Video/Image processing is a fundamental issue in computer science. It is widely used for a broad range of applications, such as weather prediction, computerized tomography (CT), artificial intelligence (AI), and etc. Video-based advanced driver assistance system (ADAS) attracts great attention in recent years, which aims at helping drivers to become more concentrated when driving and giving proper warnings if any danger is insight. Typical ADAS includes lane departure warning, traffic sign detection, pedestrian detection, and etc. Both basic and advanced video/image processing technologies are

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2

Nnolim, Uche. "Fpga architectures for logarithmic colour image processing." Thesis, University of Kent, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.509634.

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3

Harris, Matthew Joshua. "Accelerating Reverse Engineering Image Processing Using FPGA." Wright State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright155535529307322.

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4

Xu, Haifeng. "Digital Image Processing Algorithms Research Based on FPGA." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-91039.

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As we can find through the development of TV systems in America, the digital TV related digital broadcasting is just the road we would walk into. Nowadays digital television is prevailing in China, and the government is promoting the popularity of digital television. However, because of the economic development, analog television will still take its place in the TV market during a long period. But the broadcasting system has not been reformed, as a result, we should not only take use of the traditional analog system we already have, but also improve the quality of the pictures of analog system

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Siddiqui, Fahad Manzoor. "FPGA-based programmable embedded platform for image processing applications." Thesis, Queen's University Belfast, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276.

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A vast majority of electronic systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce data bandwidth and memory requirements before sending information to the central system. Field Programmable Gate Arrays (FPGAs) represent a strong platform as they permit reconfigurability and pipelining for streaming applications. However, rapid advances and changes in these application use cases crave adaptable hardware architectures that can process dynamic data workloads and be easily programmed

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Ericsson, Kenneth, and Robert Grann. "Image optimization algorithms on an FPGA." Thesis, Mälardalen University, School of Innovation, Design and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-5727.

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<p> </p><p>In this thesis a method to compensate camera distortion is developed for an FPGA platform as part of a complete vision system. Several methods and models is presented and described to give a good introduction to the complexity of the problems that is overcome with the developed method. The solution to the core problem is shown to have a good precision on a sub-pixel level.</p><p> </p>

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7

Isaksson, Johan. "FPGA-Accelerated Image Processing Using High Level Synthesis with OpenCL." Thesis, Linköpings universitet, Datorteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143213.

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High Level Synthesis (HLS) is a new method for developing applications for use on FPGAs. Instead of the classic approach using a Hardware Descriptive Language (HDL), a high level programming language can be used. HLS has many perks, including high level debugging and simulation of the system being developed. This shortens the development time which in turn lowers the development cost. In this thesis an evaluation is made regarding the feasibility of using SDAccel as the HLS tool in the OpenCL environment. Two image processing algorithms are implemented using OpenCL C and then synthesized to ru

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Serguienko, Anton. "Evaluation of Image Warping Algorithms for Implementation in FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11849.

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<p>The target of this master thesis is to evaluate the Image Warping technique and propose a possible design for an implementation in FPGA. The Image Warping is widely used in the image processing for image correction and rectification. A DSP is a usual choice for implantation of the image processing algorithms, but to decrease a cost of the target system it was proposed to use an FPGA for implementation.</p><p>In this work a different Image Warping methods was evaluated in terms of performance, produced image quality, complexity and design size. Also, considering that it is not only Image War

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9

Laptik, Raimond. "Ant colony technologies for image processing." Doctoral thesis, Lithuanian Academic Libraries Network (LABT), 2010. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2009~D_20100303_133726-51617.

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In this work ant colony technologies for image processing are analyzed. Modifications of Max-Min ant system for automatic image pre-processing are proposed. Image segmentation by multiple ant colonies technique based on pheromone competition is proposed. Modified ant system is implemented in FPGA and MicroBlaze core units influence on performance is analyzed.<br>Darbe nagrinėjamos skruzdžių kolonijų technologijos vaizdams apdoroti. Pasiūlomos max-min skruzdžių sistemos modifikacijos tinkamos automatizuoti pirminį vaizdų apdorojimą. Pristatoma vaizdų segmentavimo metodika grįsta skruzdžių kolon

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Qureshi, Kamran. "Pedestrian Detection on FPGA." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-21509.

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Image processing emerges from the curiosity of human vision. To translate, what we see in everyday life and how we differentiate between objects, to robotic vision is a challenging and modern research topic. This thesis focuses on detecting a pedestrian within a standard format of an image. The efficiency of the algorithm is observed after its implementation in FPGA. The algorithm for pedestrian detection was developed using MATLAB as a base. To detect a pedestrian, a histogram of oriented gradient (HOG) of an image was computed. Study indicates that HOG is unique for different objects within

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11

Mudassar, Burhan Ahmad. "Design and implementation of a content aware image processing module on FPGA." Thesis, Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53618.

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In this thesis, we tackle the problem of designing and implementing a wireless video sensor network for a surveillance application. The goal was to design a low power content aware system that is able to take an image from an image sensor, determine blocks in the image that contain important information and encode those block for transmission thus reducing the overall transmission effort. At the same time, the encoder and the preprocessor must not consume so much computation power that the utility of this system is lost. We have implemented such a system which uses a combination of Edge Detect

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Mulligan, David John. "An FPGA Coprocessor for Real-Time Bathymetric Synthetic Aperture Sonar." Thesis, University of Canterbury. Electrical and Computer Engineering, 2007. http://hdl.handle.net/10092/1232.

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The following is a thesis for a Master's degree in Electrical Engineering. It presents the design of an FPGA coprocessor for real-time bathymetric synthetic aperture sonar. Bathymetry is the process of finding the height of the seafloor; a problem that requires the computation of a large number of short-length correlations and runs slowly on a conventional microprocessor architecture. It is desirable to generate the seafloor bathymetry in real time for use as a visual aid during data gathering, thus the development of a customised coprocessor is required. The design presented utilises the

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13

Alotaibi, Khalid F. D. "A high level hardware description environment for FPGA-based image processing applications." Thesis, Queen's University Belfast, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.287288.

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Uzun, Isa Servan. "Design and FPGA implementation of matrix transforms for image and video processing." Thesis, Queen's University Belfast, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.437819.

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Lucking, David Joseph. "FPGA Implementation of the JPEG2000 MQ Decoder." University of Dayton / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1272050082.

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Bournias, Ilias. "Design space exploration of image processing algorithms on FPGAs." Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS179.

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La mise en œuvre d'algorithmes de traitement d'image pour les systèmes embarqués est un sujet scientifique de grande importance et de nombreux chercheurs concentrent leurs travaux sur ce domaine. De nombreux compromis doivent être réalisés afin d'adapter ces algorithmes au système ciblé et obtenir en même temps un calcul en temps réel et une précision acceptable. Dans cette thèse, nous nous concentrons sur l'exploration de l'espace de conception d'un algorithme de flot optique appelé algorithme de Horn et Schunck multi-échelles dans un FPGA Arria 10. Bien que nous nous concentrions sur un algo

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Chandrasekaran, Shrutisagar. "Efficient FPGA implementation and power modelling of image and signal processing IP cores." Thesis, Brunel University, 2007. http://bura.brunel.ac.uk/handle/2438/7301.

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Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer electronics, instrumentation, medical data processing and avionics due to their reasonable energy consumption, high performance, security, low design-turnaround time and reconfigurability. Low power FPGA devices are also emerging as competitive solutions for mobile and thermally constrained platforms. Most computationally intensive image and signal processing algorithms also consume a lot of power leading to a number of issues including reduced mobili

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Zandi, Zand Sajjad. "FPGA implementation of ROI extraction for visual-IR smart cameras." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-26076.

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Video surveillance systems have been popular as a security tool for years, and the technological development helps monitoring accident-prone areas with the help of digital image processing.A thermal and a visual camera are being used in the surveillance project. The thermal camera is sensitive to the heat emitted by objects, and it is essential to employ the thermal camera as the visual camera is only useful in the presence of light. These cameras do not provide images of the same resolution. In order to extract the region of interest (ROI) of the visual camera, the images of these cameras nee

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Chen, Luna. "Fast generation of Gaussian and Laplacian image pyramids using an FPGA-based custom computing platform." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020239/.

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King, William E. "Using an FPGA-Based Processing Platform in an Industrial Machine Vision System." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/31799.

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This thesis describes the development of a commercial machine vision system as a case study for utilizing the Modular Reprogrammable Real-time Processing Hardware (MORRPH) board. The commercial system described in this thesis is based on a prototype system that was developed as a test-bed for developing the necessary concepts and algorithms. The prototype system utilized color linescan cameras, custom framegrabbers, and standard PCs to color-sort red oak parts (staves). When a furniture manufacturer is building a panel, very often they come from edge-glued paneled parts. These are panels f

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Antonik, Piotr. "Application of FPGA to real-time machine learning: hardware reservoir computers and software image processing." Doctoral thesis, Universite Libre de Bruxelles, 2017. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/257660.

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Reservoir computing est un ensemble de techniques permettant de simplifierl’utilisation des réseaux de neurones artificiels. Les réalisations expérimentales,notamment optiques, de ce concept ont montré des performances proches de l’étatde l’art ces dernières années. La vitesse élevée des expériences optiques ne permetpas d’y intervenir en temps réel avec un ordinateur standard. Dans ce travail, nousutilisons une carte de logique programmable (Field-Programmable Gate Array, ouFPGA) très rapide afin d’interagir avec l’expérience en temps réel, ce qui permetde développer de nouvelles fonctionnali

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Scalera, Jonathan E. "Image Chipping with a Common Architecture for Microsensors (CAuS)." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/34172.

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Recent interest has emerged in microsensor platforms that are capable of supporting reconnaissance, surveillance and target acquisition operations. These devices typically consist of one or more sensors, signal conditioning and processing subsystems, a radio link and a power source. Sensors employed can range from acoustic, to seismic, to magnetic, to visible/infrared imagers. <P> A notable shortcoming of these systems is the fact that they are battery powered. The use of a finite power source places an upper limit on the lifespan of such a system. Thus, a major thrust in the development and u

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Maturana, Patrícia Salles. "Algoritmos de detecção de bordas implementados em FPGA /." Ilha Solteira : [s.n.], 2010. http://hdl.handle.net/11449/87059.

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Orientador: Alexandre César Rodrigues da Silva<br>Banca: Aledir Silveira Pereira<br>Banca: Almir Rogério Camolesi<br>Resumo: O processamento de imagens é uma área promissora na automação, por poder ser aplicado nas mais variadas atividades da tecnologia como, por exemplo, na medicina, na agricultura de precisão, dentre muitas outras. Este trabalho consiste na aplicação da área de processamento de imagens, voltada a área de segmentação, com os operadores de bordas Roberts, Prewitt e Sobel. Tendo também muita contribuição na área de processamento de imagens e sistemas embarcados, implementando o

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Abdali, El Mehdi. "Exploring the performances of partial reconfiguration in the context of image processing acceleration on FPGA-based smart cameras." Thesis, Université Clermont Auvergne‎ (2017-2020), 2020. http://www.theses.fr/2020CLFAC009.

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Les FPGAs sont des circuits d’accélération qui contiennent des ressources de calcul pouvant être librement interconnectées selon l’algorithme désiré. Cette flexibilité a rendu les FPGAs plus adaptés à implémenter efficacement des structures de calcul en flot de données où chaque noeud de calcul reçoit directement ses données à partir des noeuds qui les produisent. Ces structures sont plus efficaces quand la production et la consommation de données s’effectuent sans retard en ayant les noeuds simultanément exécutés. Toutefois, le nombre limité de ressources dans un FPGA ne permet pas une implém

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Hrbáček, Radek. "Koevoluční algoritmus v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236407.

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This thesis deals with the design of a hardware acceleration unit for digital image filter design using coevolutionary algorithms. The first part introduces reconfigurable logic device technology that the acceleration unit is based on. The theoretical part also briefly characterizes evolutionary and coevolutionary algorithms, their principles and applications. Traditional image filter designs are compared with the biologically inspired design methods. The hardware unit presented in this thesis exploits dual MicroBlaze system extended by custom peripherals to accelerate cartesian genetic progra

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Wahlstedt, Martin. "Image interpolation in firmware for 3D display." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10326.

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<p>This thesis investigates possibilities to perform image interpolation on an FPGA instead of on a graphics card. The images will be used for 3D display on Setred AB’s screen and an implementation in firmware will hopefully give two major advantages over the existing rendering methods. First, an FPGA can handle big amounts of data and perform a lot of calculations in parallel. Secondly, the amount of data to transfer is drastically increased after the interpolation and with this, a higher bandwith is required to transfer the data at a high speed. By moving the interpolation as close to the pr

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Freitas, Jovander da Silva. "Implementação de uma arquitetura para binarização de imagens em FPGA." Universidade de São Paulo, 2012. http://www.teses.usp.br/teses/disponiveis/18/18152/tde-15102012-164024/.

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Em muitas aplicações de processamento de imagens é desejável converter imagens que estão em escala de cinza para imagens binarias, ou seja, em apenas dois níveis de intensidade. Para realizar essa tarefa de separação entre dois níveis é necessário que se calcule um valor de limiar, pois a partir dele determinamos quais pixels irão pertencer a um nível, normalmente o objeto de interesse, e quais pertencerão ao outro nível, ou ao fundo da imagem. Algumas aplicações exigem que se calcule esse valor de limiar em um tempo muito curto em relação à aquisição de imagem, principalmente quando ocorre um

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Cappetta, Carmine. "Project and development of hardware accelerators for fast computing in multimedia processing." Doctoral thesis, Universita degli studi di Salerno, 2019. http://elea.unisa.it:8080/xmlui/handle/10556/4300.

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2017 - 2018<br>The main aim of the present research work is to project and develop very large scale electronic integrated circuits, with particular attention to the ones devoted to image processing applications and the related topics. In particular, the candidate has mainly investigated four topics, detailed in the following. First, the candidate has developed a novel multiplier circuit capable of obtaining floating point (FP32) results, given as inputs an integer value from a fixed integer range and a set of fixed point (FI) values. The result has been accomplished exploiting a series of the

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Pakalapati, Himani Raj. "Programming of Microcontroller and/or FPGA for Wafer-Level Applications - Display Control, Simple Stereo Processing, Simple Image Recognition." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89795.

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In this work the usage of a WLC (Wafer Level Camera) for ensuring road safety has been presented. A prototype of a WLC along with the Aptina MT9M114 stereoboard has been used for this project. The basic idea is to observe the movements of the driver. By doing so an understanding of whether the driver is concentrating on the road can be achieved. For this project the display of the required scene is captured with a wafer-level camera pair. Using the image pairs stereo processing is performed to obtain the real depth of the objects in the scene. Image recognition is used to separate the object f

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Hameed, Tariq, Ahsan Ashfaq, and Rabid Mehmood. "Intelligent Sensor." Thesis, Högskolan i Halmstad, Sektionen för Informationsvetenskap, Data– och Elektroteknik (IDE), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-17310.

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The task is to build an intelligent sensor that can instruct a Lego robot to perform certain tasks. The sensor is mounted on the Lego robot and it contains a digital camera which takes continuous images of the front view of the robot. These images are received by an FPGA which simultaneously saves them in an external storage device (SDRAM). At one time only one image is saved and during the time it is being saved, FPGA processes the image to extract some meaningful information. In front of digital camera there are different objects. The sensor is made to classify various objects on the basis o

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De, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.

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The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, wit

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Pacheco, Márcio Alexandre. "Nova metodologia de localização de regiões candidatas em imagens digitais utilizando arquiteturas reconfiguráveis." Universidade Federal de Santa Maria, 2007. http://repositorio.ufsm.br/handle/1/8590.

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This work involves the study and the implementation of different techniques of image processing in software and hardware , aiming the implementation of a new methodology of digital images location of candidate regions . Both implementations will be compared with the objective of verifying the obtained performance during the execution of the algorithms in PC and FPGA XILINX Spartan3 model3s400ft256.®. This task will be performed by applying some morphological operators, like erosion, dilatation and gradient to obtain only the borders of the processed image. After the conclusion of this stage lo

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Rotava, Lucas. "Algoritmos de tempo real para melhoramento de imagens capturadas no espectro do infravermelho projetados para síntese em FPGA." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/18/18152/tde-21012016-143940/.

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Este trabalho apresenta o desenvolvimento de algoritmos de processamento de imagens para câmeras térmicas, com o objetivo de sintetizá-los em FPGA. Existem diversas aplicações para imagens térmicas nas áreas médica, de segurança e industrial, por isso o conhecimento e o desenvolvimento de câmeras térmicas são de interesse para a academia e para a indústria. Por consequência, o desenvolvimento de algoritmos que tratem as imagens também representa importante papel. Os algoritmos implementados neste trabalho são: correção de não uniformidade (NUC); substituição de pixels defeituosos, ou bad pixel

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Maturana, Patrícia Salles [UNESP]. "Algoritmos de detecção de bordas implementados em FPGA." Universidade Estadual Paulista (UNESP), 2010. http://hdl.handle.net/11449/87059.

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Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-11-26Bitstream added on 2014-06-13T20:47:51Z : No. of bitstreams: 1 maturana_ps_me_ilha.pdf: 1032347 bytes, checksum: dec94f0e6e09e287ba22966d66ac4e83 (MD5)<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)<br>O processamento de imagens é uma área promissora na automação, por poder ser aplicado nas mais variadas atividades da tecnologia como, por exemplo, na medicina, na agricultura de precisão, dentre muitas outras. Este trabalho consiste na aplicação da área de proces

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TROTTA, PASCAL. "Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2641174.

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Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge

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Wikström, Rebecca. "Real-time Traffic Sign Detection and Classification : Evaluation of Image Processing performed on an FPGA-based platform." Thesis, KTH, Mekatronik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-244397.

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As a part of the development of autonomous vehicles and advanced driver-assistance systems (ADAS), vision systems are used as a method for collection of extensive data about the surrounding world [1]. This data can thereafter be processed and information can be extracted. Due to the safety-critical nature of automotive applications, the image processing of the camera stream must be performed in real-time [2]. This thesis investigates how a system with real-time performance potential - an FPGA-based system - can be utilised to perform image processing applications. Specifically the thesis looks

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Gullapalli, Sai Krishna. "Wave-Digital FPGA Architectures of 4-D Depth Enhancement Filters for Real-Time Light Field Image Processing." University of Akron / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=akron1574443263497981.

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Tarmaster, Adit. "Median and morphological filtering of images in real time using an FPGA-based custom computing platform." Thesis, Virginia Tech, 1994. http://hdl.handle.net/10919/42204.

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This thesis describes the design and implementation of real-time image-processing tasks on a custom computing platform called Splash-2. The tasks that have been implemented are image histogram generation, median filtering using 3X3 neighborhoods, and morphological dilation and erosion. These problems are computationally intensive, involving large amounts of data. The problems are especially difficult when the images need to be processed at real-time rates, typically 30 frames per second. Splash-2 is a reconfigurable FFPGA-based attached processor featuring several programmable processing eleme

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Benderli, Oguz. "A Real-time, Low-latency, Fpga Implementation Of The Two Dimensional Discrete Wavelet Transform." Master's thesis, METU, 2003. http://etd.lib.metu.edu.tr/upload/1056282/index.pdf.

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This thesis presents an architecture and an FPGA implementation of the two dimensional discrete wavelet transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the iii DWT module and the amount of lo

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Drayer, Thomas Hudson. "A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware." Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30619.

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A new design methodology that produces hardware solutions for performing real-time image processing is presented here. This design methodology provides significant advantages over traditional hardware design approaches by translating real-time image processing tasks into the gate-level resources of programmable logic-based hardware architectures. The use of programmable logic allows high-performance solutions to be realized with very efficient utilization of available logic and interconnection resources. These implementations pr

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Tepvorachai, Gorn. "An Evolutionary Platform for Retargetable Image and Signal Processing Applications." Case Western Reserve University School of Graduate Studies / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=case1209504058.

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Tallawi, Reham. "FPGA-based Speed Limit Sign Detection." Master's thesis, Universitätsbibliothek Chemnitz, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-229018.

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This thesis presents a new hardware accelerated approach using image processing and detection algorithms for implementing fast and robust traffic sign detection system with focus on speed limit sign detection. The proposed system targets reconfigurable integrated circuits particularly Field Programmable Gate Array (FPGA) devices. This work propose a fully parallelized and pipelined parallel system architecture to exploit the high performance and flexibility capabilities of FPGA devices. This thesis is divided into two phases, the first phase, is a software prototype implementation of the propo

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Ramsay, Robert. "A Hardware Based 3D Room Scanner." Thesis, University of Canterbury. Electrical and Computer Engineering, 2008. http://hdl.handle.net/10092/1240.

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This thesis describes a project to create a hardware based 3D interior scanner. This was based on a previous project that created a scanner optimised for interior conditions, using structured light triangulation. The original project referred to as the Mark-I scanner, performed its control and processing on a PC and the primary goal of this project was to re-implement this system using hardware, making the scanner more portable and simpler to use. The Mark-I system required a specialised camera which had an unusually high noise associated with it, so a secondary goal was to investigate whether

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Joginipelly, Arjun. "Implementation of Separable & Steerable Gaussian Smoothers on an FPGA." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/98.

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Smoothing filters have been extensively used for noise removal and image restoration. Directional filters are widely used in computer vision and image processing tasks such as motion analysis, edge detection, line parameter estimation and texture analysis. It is practically impossible to tune the filters to all possible positions and orientations in real time due to huge computation requirement. The efficient way is to design a few basis filters, and express the output of a directional filter as a weighted sum of the basis filter outputs. Directional filters having these properties are called

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Cedernaes, Erasmus. "Runway detection in LWIR video : Real time image processing and presentation of sensor data." Thesis, Uppsala universitet, Avdelningen för visuell information och interaktion, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-300690.

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Runway detection in long wavelength infrared (LWIR) video could potentially increase the number of successful landings by increasing the situational awareness of pilots and verifying a correct approach. A method for detecting runways in LWIR video was therefore proposed and evaluated for robustness, speed and FPGA acceleration. The proposed algorithm improves the detection probability by making assumptions of the runway appearance during approach, as well as by using a modified Hough line transform and a symmetric search of peaks in the accumulator that is returned by the Hough line transform.

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Gogol, František. "Inteligentní kamera." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217458.

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An intelligent camera includes a processor, which can extract information from images without the need for an external processing unit, and interface devices used to make the results available to other devices. This paper describes the intelligent camera design and implementation into the Field Programmable Gate Array (FPGA). The implemented architecture contains a camera controller, a memory controller, an IIC controller, a VGA controller, and an execution unit. The camera controller communicates with a CMOS chip. The memory controller communicates with a DDR SDRAM memory. The IIC controller

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Almeida, Carlos Caetano de 1976. "Arquitetura do módulo de convolução para visão computacional baseada em FPGA." [s.n.], 2015. http://repositorio.unicamp.br/jspui/handle/REPOSIP/265780.

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Orientador: Eurípedes Guilherme de Oliveira Nóbrega<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica<br>Made available in DSpace on 2018-08-27T23:49:29Z (GMT). No. of bitstreams: 1 Almeida_CarlosCaetanode_M.pdf: 5316196 bytes, checksum: 8c3ec7a0c5709f2507df4dbc54c137b0 (MD5) Previous issue date: 2015<br>Resumo: Esta dissertação apresenta o estudo de uma arquitetura para o processamento digital de imagens, desenvolvido através de dispositivos de hardware programável, no caso FPGA, para a implementação eficiente no domínio do tempo do algoritmo da

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Ram, Prakash Rohith Raj. "FPGA Based Lane Tracking system for Autonomous Vehicles." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-273269.

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The application of Image Processing to Autonomous driving has drawn significant attention in recently. However, the demanding nature of the image processing algorithms conveys a considerable burden to any conventional realtime implementation. On the other hand, the emergence of FPGAs has brought numerous facilities toward fast prototyping and implementation of ASICs so that an image processing algorithm can be designed, tested and synthesized in a relatively short period in comparison to traditional approaches. This thesis investigates the best combination of current algorithms to reach an opt

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ROLFO, DANIELE. "High-performance hardware accelerators for image processing in space applications." Doctoral thesis, Politecnico di Torino, 2015. http://hdl.handle.net/11583/2616951.

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Mars is a hard place to reach. While there have been many notable success stories in getting probes to the Red Planet, the historical record is full of bad news. The success rate for actually landing on the Martian surface is even worse, roughly 30%. This low success rate must be mainly credited to the Mars environment characteristics. In the Mars atmosphere strong winds frequently breath. This phenomena usually modifies the lander descending trajectory diverging it from the target one. Moreover, the Mars surface is not the best place where performing a safe land. It is pitched by many and clo

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McNichols, John M. "Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding." University of Dayton / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1343737032.

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