Log in

Relevant bibliographies by topics / Image processing FPGA / Journal articles

To see the other types of publications on this topic, follow the link: Image processing FPGA.

Journal articles on the topic 'Image processing FPGA'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'Image processing FPGA.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Ai, Duong Huu, Van Loi Nguyen, Khanh Ty Luong, and Viet Truong Le. "Design of mean filter using field programmable gate arrays for digital images." Indonesian Journal of Electrical Engineering and Computer Science 36, no. 3 (2024): 1430. http://dx.doi.org/10.11591/ijeecs.v36.i3.pp1430-1436.

Full text

Abstract:

In this paper, we design and analysis of mean filter using field programmable gate arrays (FPGAs) for digital images, FPGAs are integrated circuits consisting of interconnections that connect programmable internal hardware blocks allows users to customize operations for a specific application. FPGA is an ideal choice for real-time image processing, these FPGA devices are controlled in Verilog or VHDL languages, allowing to design at different levels and adapt to design changes or even support new applications throughout the life of the component. Digital image filtering is the most important t

APA, Harvard, Vancouver, ISO, and other styles

2

Bundschuh, Sina, Jan Kunze, and Klaus-Dieter Kuhnert. "Implementation of an FPGA-Based System to Process Images and Match Keypoints on High-Resolution Pictures." Electronics 13, no. 23 (2024): 4774. https://doi.org/10.3390/electronics13234774.

Full text

Abstract:

Processing scenery and finding points of interest is crucial for applications in robotics and aerospace missions. Those areas require efficient and reliable visual input processing. Here, field programmable gate arrays (FPGAs) offer essential advantages, like low power consumption compared to CPUs, performing a large number of calculations simultaneously, and having compact hardware. This paper presents an FPGA system that processes incoming camera data, finds points of interest, and matches them across different images on high-resolution images (2048 × 1088). It is a novel approach to impleme

APA, Harvard, Vancouver, ISO, and other styles

3

B, Devanathan, Selvaraju P, Thulasimani T, and Vishal Ratansing Patil. "FPGA-BASED HARDWARE ACCELERATION OF MACHINE LEARNING ALGORITHM FOR REAL-TIME IMAGE PROCESSING." ICTACT Journal on Microelectronics 9, no. 3 (2023): 1613–19. https://doi.org/10.21917/ijme.2023.0280.

Full text

Abstract:

In real-time image processing, the demand for efficient solutions has surged with the proliferation of applications spanning from autonomous vehicles to medical diagnostics. This study addresses the imperative need for accelerated machine learning algorithms to enhance the processing speed of image-related tasks. The research focuses on leveraging Field-Programmable Gate Arrays (FPGAs) to implement hardware acceleration, exploiting their parallel computing capabilities. The advent of machine learning in image processing has revolutionized various industries, yet real-time applications encounte

APA, Harvard, Vancouver, ISO, and other styles

4

Bailey, Donald G. "Image Processing Using FPGAs." Journal of Imaging 5, no. 5 (2019): 53. http://dx.doi.org/10.3390/jimaging5050053.

Full text

Abstract:

Nine articles have been published in this Special Issue on image processing using field programmable gate arrays (FPGAs). The papers address a diverse range of topics relating to the application of FPGA technology to accelerate image processing tasks. The range includes: Custom processor design to reduce the programming burden; memory management for full frames, line buffers, and image border management; image segmentation through background modelling, online K-means clustering, and generalised Laplacian of Gaussian filtering; connected components analysis; and visually lossless image compress

APA, Harvard, Vancouver, ISO, and other styles

5

Vesely, Jaroslav. "FPGA and GPU Utilization in Industrial Image Processing: Comparative Study and Application." International Journal Software Engineering and Computer Science (IJSECS) 5, no. 1 (2025): 88–101. https://doi.org/10.35870/ijsecs.v5i1.3273.

Full text

Abstract:

This work aims to investigate the FPGA (Field-Programmable Gate Array) and GPU (Graphical Processing Unit) technology in image optimization research for an industrial frontier study. Using an experimental method, the research compared the efficiency of two technologies as implemented in some many image processing algorithms. NI CompactRIO platform for FPGA implementation and NVIDIA GeForce GTX 970 in GPU processing performed differently. As is well known, low-lag applications (camera synchronization, real-time data processing etc.) were very well suited for FPGAs. GPUs with architecture CUDA,

APA, Harvard, Vancouver, ISO, and other styles

6

Janmane, Akshay S., Apeksha S. Patil, and Madhuri V. Huilgol. "FPGA Based Real Time Medical Image Processing." Bonfring International Journal of Research in Communication Engineering 6, Special Issue (2016): 113–16. http://dx.doi.org/10.9756/bijrce.8214.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Duong, Huu Ai, Dat Vuong Cong, Ty Luong Khanh, and Truong Le Viet. "Field programmable gate array implementation of edge detection system based on an improved sobel edge detector." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 3 (2023): 1378–83. https://doi.org/10.11591/ijeecs.v32.i3.pp1378-1383.

Full text

Abstract:

Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an important tool.

APA, Harvard, Vancouver, ISO, and other styles

8

Huu Ai, Duong, Cong Dat Vuong, Khanh Ty Luong, and Viet Truong Le. "Field programmable gate array implementation of edge detection system based on an improved sobel edge detector." Indonesian Journal of Electrical Engineering and Computer Science 32, no. 3 (2023): 1378. http://dx.doi.org/10.11591/ijeecs.v32.i3.pp1378-1383.

Full text

Abstract:

<p>Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an import

APA, Harvard, Vancouver, ISO, and other styles

9

Fu, Qing Qing, and Zheng Bin Liang. "The Design of Textile Image Processing System." Applied Mechanics and Materials 148-149 (December 2011): 250–53. http://dx.doi.org/10.4028/www.scientific.net/amm.148-149.250.

Full text

Abstract:

According to the drawback of high cost and complicated circuit and inadequate use of resources in DSP and FPGA structure of textile image processing, an image processing system based on Nios II in FPGA is designed. FPGA is the core of the system.Nios II processor is created in FPGA.Video image is acquired by CCD and processed in FPGA. The result shows that the system has some characteristics of small size, low cost, high integration, high stability and flexibility.

APA, Harvard, Vancouver, ISO, and other styles

10

Zhou, Guangshao, Shuai Guo, and Zhibo Chen. "FPGA-Based Improved Sobel Operator Edge Detection." Frontiers in Computing and Intelligent Systems 5, no. 2 (2023): 6–11. http://dx.doi.org/10.54097/fcis.v5i2.12122.

Full text

Abstract:

Image edge detection is an important field in image processing, with its primary goal being to identify edge information of various objects in images. Traditional edge detection programs are mostly executed serially, resulting in low detection efficiency. This paper proposes an FPGA-based improved Sobel operator edge detection method, harnessing the parallel processing capability of FPGA to enhance detection efficiency. Building upon the Sobel operator in edge detection algorithms, this method increases the convolution calculation dimensions of the Sobel operator, expanding it from 2 direction

APA, Harvard, Vancouver, ISO, and other styles

11

Deng, Huajian, Hao Wang, and Zhonghe Jin. "High-performance subpixel edge location based on FPGA for horizon sensors." Journal of Physics: Conference Series 2746, no. 1 (2024): 012038. http://dx.doi.org/10.1088/1742-6596/2746/1/012038.

Full text

Abstract:

Abstract Horizon edge localization accuracy and speed are key factors in the performance of horizon sensors. This paper proposes a high-performance sub-pixel edge localization algorithm base on Field Programmable Gate Array (FPGA) for horizon sensors. The algorithm is carefully designed and simplified according to the computational capabilities and limitations of FPGAs. By making full use of the parallel computing capability of FPGA and carrying out multi-stage pipeline design, the algorithm can complete image acquisition, rough edge localization, sub-pixel edge localization, and projections f

APA, Harvard, Vancouver, ISO, and other styles

12

Aranda, Luis, Pedro Reviriego, and Juan Maestro. "Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs." Electronics 7, no. 11 (2018): 322. http://dx.doi.org/10.3390/electronics7110322.

Full text

Abstract:

Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some pa

APA, Harvard, Vancouver, ISO, and other styles

13

Agnihotri, Aditiya. "Investigation on Efficient FPGA Architectures for Image Coding Algorithm." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 9, no. 3 (2018): 1090–99. http://dx.doi.org/10.17762/turcomat.v9i3.13898.

Full text

Abstract:

In this research, we provide an effective hardware architecture for various image processing, enhancement, and filtering algorithms that is based on FPGAs. The inherent spatial and temporal parallelism in FPGA architecture makes them a popular choice as implementation platforms for real-time image processing applications. The filters are applied by iteratively cycling over an image's pixels using a windowing operator method. Software becomes less effective and real-time hardware solutions are required as picture sizes and bit depths increase. While the findings shown here are for a picture wit

APA, Harvard, Vancouver, ISO, and other styles

14

Kumar K, Kavin, Amirthavarshini S A, and Dhivya Dharshini T. "Optimization Of Memory Usage in High-Speed Cameras Using FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 03 (2025): 1–9. https://doi.org/10.55041/ijsrem42409.

Full text

Abstract:

High-speed cameras generate large amounts of data, making memory optimization difficult for real-time processing. This project minimizes data size by converting RGBA (Red, Green, Blue, Alpha) images to RGB, eliminating the Alpha channel to reduce memory usage. The captured images are provided as input to Verilog code in hexadecimal format, with the conversion done by MATLAB. Bilinear Interpolation is applied to reduce the potential quantization errors during the conversion, using the values of four surrounding pixels to smooth the image and maintain quality. After processing, the image is reco

APA, Harvard, Vancouver, ISO, and other styles

15

Dandekar, Omkar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekhar. "Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration." International Journal of Reconfigurable Computing 2008 (2008): 1–17. http://dx.doi.org/10.1155/2008/738174.

Full text

Abstract:

In real-time signal processing, a single application often has multiple computationally intensive kernels that can benefit from acceleration using custom or reconfigurable hardware platforms, such as field-programmable gate arrays (FPGAs). For adaptive utilization of resources at run time, FPGAs with capabilities for dynamic reconfiguration are emerging. In this context, it is useful for designers to derive sets of efficient configurations that trade off application performance with fabric resources. Such sets can be maintained at run time so that the best available design tradeoff is used. Fi

APA, Harvard, Vancouver, ISO, and other styles

16

Fan, Yong Jie, and Hua Chen. "General Digital Image Processing Circuit and its Applications." Advanced Materials Research 981 (July 2014): 299–303. http://dx.doi.org/10.4028/www.scientific.net/amr.981.299.

Full text

Abstract:

In this paper, the design and architecture of general digital image processing circuit (GFDIPC) based on a Xilinx Virtex-5 FPGA processor is presented. The GFDIPC applications on thermal imaging, image fusion, real-time video stabilization and time-delay test for image processing system are described. The design of FPGA in each application follows the principle of functional modularity, pipeline processing and parallel computing, which brings FPGA high efficiency and high real-time performance.

APA, Harvard, Vancouver, ISO, and other styles

17

Tymchenko, L. "FPGA USAGE FOR PROCESSING IMAGE OF LASER BEAM." Collection of scientific works of the State University of Infrastructure and Technologies series "Transport Systems and Technologies" 1, no. 37 (2021): 144–55. http://dx.doi.org/10.32703/2617-9040-2021-37-14.

Full text

Abstract:

Considered modern problems of laser image processing. An analysis of existing solutions and recent research in the field of image processing of laser beam. Determined that the latter solutions have a number of disadvantages in terms of increasing the speed and density of information flow. There are also problems with excessive power consumption during image processing due to excess power. Also presented method of processing image of laser beam with the use of FPGA and parallelhierarchical transformation. Performing simulation modeling of methods for processing the coordinates of laser beam spo

APA, Harvard, Vancouver, ISO, and other styles

18

Xu, Guo Sheng. "Design of Image Processing System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1281–84. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1281.

Full text

Abstract:

To speed up the image acquisition and make full use of effective information, a design method of CCD partial image scanning system is presented. The system achieves to functions of the high -speed data collection, the high -speed video data compression the real time video data Network Transmission and the real time compression picture data storage. the data processed was transferred to PC through USB2.0 real-time to reconstruct defects microscopic images. Experiments show that the system has stable performance, real-time data transmission and high quality images, feasible by adopting the algor

APA, Harvard, Vancouver, ISO, and other styles

19

Yu, Jiaye. "The progress of image denoising based on FPGA." Highlights in Science, Engineering and Technology 131 (March 25, 2025): 29–34. https://doi.org/10.54097/2bpam373.

Full text

Abstract:

With the increasing demand for high-quality images in applications such as intelligent driving and medical imaging, the removal of noise like Gaussian and salt-and-pepper noise has become a significant challenge. Traditional software-based denoising methods, while flexible, often fail to meet real-time performance and high throughput requirements, especially with the growing scale of image data. FPGA (Field-Programmable Gate Array) provides a promising alternative with its high parallelism and low power consumption, enabling efficient hardware-level image processing. This paper aims to FPGA-ba

APA, Harvard, Vancouver, ISO, and other styles

20

Barkovska, Olesia, Inna Filippenko, Ivan Semenenko, Valentyn Korniienko, and Peter Sedlaček. "Adaptation of FPGA architecture for accelerated image preprocessing." Radioelectronic and Computer Systems, no. 2 (May 25, 2023): 94–106. http://dx.doi.org/10.32620/reks.2023.2.08.

Full text

Abstract:

The work is devoted to the topical problem at the intersection of communications theory, digital electronics and numerical analysis, namely the study of image processing methods implementation time on different architectures of computational devices, which are used for software and hardware acceleration. The subject of this article is the investigation of reconfigurable FPGA processing systems in the image processing area. The goal of this work is to create a reconfigurable FPGA-based image processing system and compare it with existing processing architectures. Task. To fulfill the requiremen

APA, Harvard, Vancouver, ISO, and other styles

21

Bachanna, Dr Prashant. "Design and Implementation of Image and Video Handling on a Platform with Reconfiguravle FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 01 (2025): 1–9. https://doi.org/10.55041/ijsrem40481.

Full text

Abstract:

This research explores the design and implementa- tion of an image and video processing platform using recon- figurable FPGA technology. With the increasing demand for real- time, high-performance multimedia processing in modern applications, a flexible and efficient solution is essential. The project utilizes an FPGA-based platform to handle image and video data processing through edge detection, image scaling, and real-time motion detection techniques. By integrating custom- built hardware components, this study aims to provide a low- power, high-throughput solution that meets the requiremen

APA, Harvard, Vancouver, ISO, and other styles

22

Suhaili, Shamsiah, Joyce Shing Yii Huong, Asrani Lit, et al. "Development of Digital Image Processing Algorithms via FPGA Implementation." Semarak International Journal of Electronic System Engineering 3, no. 1 (2024): 28–45. http://dx.doi.org/10.37934/sijese.3.1.2845.

Full text

Abstract:

Real-time image processing is one of the fundamental elements in achieving IR 4.0. The rapid development of digital image processing techniques has enabled various applications in fields such as healthcare, transportation, and manufacturing. People are seeking higher-performance image processing as traditional image processing is no longer fulfilling the demands. FPGA-based digital image processing has become one of the choices for the public due to its parallel pipelining, which enables shorter processing time and better performance. Several digital image processing algorithms have been devel

APA, Harvard, Vancouver, ISO, and other styles

23

Suhaili, Shamsiah, Joyce Shing Yii Huong, Asrani Lit, et al. "Development of Digital Image Processing Algorithms via FPGA Implementation." Semarak International Journal of Electronic System Engineering 3, no. 1 (2024): 28–45. https://doi.org/10.37934/sijese.3.1.2845a.

Full text

Abstract:

Real-time image processing is one of the fundamental elements in achieving IR 4.0. The rapid development of digital image processing techniques has enabled various applications in fields such as healthcare, transportation, and manufacturing. People are seeking higher-performance image processing as traditional image processing is no longer fulfilling the demands. FPGA-based digital image processing has become one of the choices for the public due to its parallel pipelining, which enables shorter processing time and better performance. Several digital image processing algorithms have been devel

APA, Harvard, Vancouver, ISO, and other styles

24

Luo, Yawen, and Yuhua Chen. "FPGA-Based Acceleration on Additive Manufacturing Defects Inspection." Sensors 21, no. 6 (2021): 2123. http://dx.doi.org/10.3390/s21062123.

Full text

Abstract:

Additive manufacturing (AM) has gained increasing attention over the past years due to its fast prototype, easier modification, and possibility for complex internal texture devices when compared to traditional manufacture processing. However, potential internal defects are occurring during AM processes, and it requires real-time inspections to minimize the costs by either aborting the processing or repairing the defect. In order to perform the defects inspection, first the defects database NEU-DET is used for training. Then, a convolution neural network (CNN) is applied to perform defects clas

APA, Harvard, Vancouver, ISO, and other styles

25

UZUN, ISA SERVAN, and ABBES AMIRA. "A FPGA-BASED PARAMETRIZABLE SYSTEM FOR HIGH-RESOLUTION FREQUENCY-DOMAIN IMAGE FILTERING." Journal of Circuits, Systems and Computers 14, no. 05 (2005): 895–921. http://dx.doi.org/10.1142/s0218126605002775.

Full text

Abstract:

Signal and image processing applications require high computational power with the ability to experiment different algorithms involving matrix transforms. Reconfigurable hardware devices in the form of Field Programmable Gate Arrays (FPGAs) have been proposed to obtain high performance at an economical price. However, the users must program FPGAs at a very low level and must have a detailed knowledge of the architecture of the device being used. In trying to reconcile the dual requirements of high performance and the ease of development, this paper reports the design and realization of the Fas

APA, Harvard, Vancouver, ISO, and other styles

26

Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

Full text

Abstract:

A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acqu

APA, Harvard, Vancouver, ISO, and other styles

27

Yang, Chun Yan, Chang Qing Cui, and Qian Wang. "The Design of Digital Image Display System Based on FPGA." Applied Mechanics and Materials 631-632 (September 2014): 482–85. http://dx.doi.org/10.4028/www.scientific.net/amm.631-632.482.

Full text

Abstract:

With the development of computer, multimedia and integrated circuit technology, more and more information are digital, so that the storage and processing including images, sounds and words, etc. After processing the information, of course, it eventually to be represented in the form of people can accept. FPGA has the characteristics of the device, occupies an important position in the information processing system, this paper expounds how to complete image acquisition processing system functions in the FPGA.

APA, Harvard, Vancouver, ISO, and other styles

28

Narayanan, M. Rajaram, and S. Gowri. "Intelligent Vision Based Technique Using ANN for Surface Finish Assessment of Machined Components." Key Engineering Materials 364-366 (December 2007): 1251–56. http://dx.doi.org/10.4028/www.scientific.net/kem.364-366.1251.

Full text

Abstract:

In this work, an FPGA hardware based image processing algorithm for preprocessing the images and enhance the image quality has been developed. The captured images were processed using a FPGA chip to remove the noise and then using a neural network, the surface roughness of machined parts produced by the grinding process was estimated. To ensure the effectiveness of this approach the roughness values quantified using these image vision techniques were then compared with widely accepted standard mechanical stylus instrument values. Quantification of digital images for surface roughness was perfo

APA, Harvard, Vancouver, ISO, and other styles

29

Nishikant Sadafale, Minal Deshmukh, Prasad Khandekar,. "AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS." INFORMATION TECHNOLOGY IN INDUSTRY 9, no. 1 (2021): 280–87. http://dx.doi.org/10.17762/itii.v9i1.130.

Full text

Abstract:

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic

APA, Harvard, Vancouver, ISO, and other styles

30

Zhang, Bao Feng, Yi Yang, Jun Chao Zhu, and Cui Li. "Embedded Real-Time Image Processing System Based on DM6446+FPGA Architecture." Advanced Engineering Forum 6-7 (September 2012): 542–46. http://dx.doi.org/10.4028/www.scientific.net/aef.6-7.542.

Full text

Abstract:

To solve the traditional image processing system problem such as large in size, high power consumption and poor real-time, an embedded real-time image processing system is designed based on TMS320DM6446+FPGA architecture. DM6446 as the core of the system is responsible for the scheduling, image processing algorithms, image output; field programmable gate array (FPGA) is responsible for capturing real-time image data, image preprocessing. The paper describes the principle of the real-time image processing system. The experiment proved that the system can achieve real-time acquisition, processin

APA, Harvard, Vancouver, ISO, and other styles

31

Kong, Su Ran. "FPGA + DSP-Based Real-Time Image Acquisition System Research and Design." Advanced Materials Research 433-440 (January 2012): 5482–88. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5482.

Full text

Abstract:

Image processing system to calculate the volume, real-time high and the requirements of small size, using the DSP-based processor, FPGA approach, supplemented by the processor design of a high-performance real-time image processing system, and the system In the process of image acquisition and transmission of noise, using the PCB's anti-jamming design. Practice shows that two chips using FPGA + DSP, the algorithm is divided into two parts by the FPGA and DSP processing; effectively improve the efficiency of the algorithm. System real-time high, adaptability, real-time image acquisition system

APA, Harvard, Vancouver, ISO, and other styles

32

Mo, Handong, Xinhong Zhou, and Chenglang L. "Design of a real-time image processing system based on FPGA." Advances in Engineering Innovation 9, no. 1 (2024): 63–67. http://dx.doi.org/10.54254/2977-3903/9/2024094.

Full text

Abstract:

To enhance the real-time performance of image processing, effectively reduce video transmission bandwidth and storage space, and improve transmission efficiency, a real-time image processing system was designed using a Field Programmable Gate Array (FPGA). The system is mainly divided into image acquisition, image processing, and image display subsystems. Images are captured using a camera module and transmitted to the image processing module for processing, and finally displayed via an HDMI monitor. Measurements indicate that the system has strong real-time performance, low power consumption,

APA, Harvard, Vancouver, ISO, and other styles

33

Hudomalj, Uroš, Christopher Mandla, and Markus Plattner. "FPGA Implementations of Algorithms for Preprocessing of High Frame Rate and High Resolution Image Streams in Real Time." Annals of Emerging Technologies in Computing 5, no. 2 (2021): 50–61. http://dx.doi.org/10.33166/aetic.2021.02.005.

Full text

Abstract:

This paper presents FPGA implementations of image filtering and image averaging – two widely applied image preprocessing algorithms. The implementations are targeted for real time processing of high frame rate and high resolution image streams. The developed implementations are evaluated in terms of resource usage, power consumption, and achievable frame rates. For the evaluation, Microsemi’s Smartfusion2 Advanced Development Kit is used. It includes a SmartFusion2 M2S150 SoC FPGA. The performance of the developed implementation of image filtering algorithm is compared to a solution provided b

APA, Harvard, Vancouver, ISO, and other styles

34

Hrytsko, T. L., D. Lenskiy, and V. S. Hlukhov. "REVIEW OF THE CAPABILITIES OF THE JPEG-LS ALGORITHM FOR ITS USE WITH EARTH SURFACE SCANNERS." Computer systems and network 6, no. 2 (2024): 14–24. https://doi.org/10.23939/csn2024.02.014.

Full text

Abstract:

The article explores the possibilities of implementing the JPEG-LS image compression algorithm on Field Programmable Gate Arrays (FPGA) for processing monochrome video streams from Earth surface scanners. A comparison of software implementations of the algorithms, their compression ratio, and execution time is conducted. Methods for improving FPGA performance are considered, using parallel data processing and optimized data structures to accelerate compression and decompression processes. Test results of the software implementation of the algorithm show an average processing speed of 179.2 Mbi

APA, Harvard, Vancouver, ISO, and other styles

35

Hrytsko, T. L., D. Lenskiy, and V. S. Hlukhov. "REVIEW OF THE CAPABILITIES OF THE JPEG-LS ALGORITHM FOR ITS USE WITH EARTH SURFACE SCANNERS." Computer systems and network 6, no. 2 (2024): 15–25. https://doi.org/10.23939/csn2024.02.015.

Full text

Abstract:

The article explores the possibilities of implementing the JPEG-LS image compression algorithm on Field Programmable Gate Arrays (FPGA) for processing monochrome video streams from Earth surface scanners. A comparison of software implementations of the algorithms, their compression ratio, and execution time is conducted. Methods for improving FPGA performance are considered, using parallel data processing and optimized data structures to accelerate compression and decompression processes. Test results of the software implementation of the algorithm show an average processing speed of 179.2 Mbi

APA, Harvard, Vancouver, ISO, and other styles

36

Azhari, Zul Imran, Samsul Setumin, Anis Diyana Rosli, and Siti Juliana Abu Bakar. "A systematic literature review on hardware implementation of image processing." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 19. http://dx.doi.org/10.11591/ijres.v12.i1.pp19-28.

Full text

Abstract:

Image processing has become under the spotlight recently and leads to a significant shift in various fields such as biomedical, satellite images, and graphical applications. Nevertheless, the poor quality of an image is one of the noticeable limitations of image processing as it restricts efficient data extraction to be conducted. Conventionally, the image was processed via software applications such as MATLAB. In spite of the software's ability to cater to the data extraction of low-quality image issues, it still suffers from the time-consuming issue. As the ability to obtain a rapid outcome

APA, Harvard, Vancouver, ISO, and other styles

37

Zul, Imran Azhari, Setumin Samsul, Diyana Rosli Anis, and Juliana Abu Bakar Siti. "A systematic literature review on hardware implementation of image processing." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 1 (2023): 19–28. https://doi.org/10.11591/ijres.v12.i1.pp19-28.

Full text

Abstract:

Image processing has become under the spotlight recently and leads to a significant shift in various fields such as biomedical, satellite images, and graphical applications. Nevertheless, the poor quality of an image is one of the noticeable limitations of image processing as it restricts efficient data extraction to be conducted. Conventionally, the image was processed via software applications such as MATLAB. In spite of the software's ability to cater to the data extraction of low-quality image issues, it still suffers from the time-consuming issue. As the ability to obtain a rapid outc

APA, Harvard, Vancouver, ISO, and other styles

38

Alhomoud, Ahmed, Refka Ghodhbani, Taoufik Saidani, et al. "Model-based Design of a High-Throughput Canny Edge Detection Accelerator on Zynq-7000 FPGA." Engineering, Technology & Applied Science Research 14, no. 2 (2024): 13547–53. http://dx.doi.org/10.48084/etasr.7081.

Full text

Abstract:

This paper presents a novel approach for fast FPGA prototyping of the Canny edge detection algorithm using High-Level Synthesis (HLS) based on the HDL Coder. Traditional RTL-based design methodologies for implementing image processing algorithms on FPGAs can be time-consuming and error-prone. HLS offers a higher level of abstraction, enabling designers to focus on algorithmic functionality while the tool automatically generates efficient hardware descriptions. This advantage was exploited by implementing the Canny edge detection algorithm in MATLAB/Simulink and utilizing the HDL Coder to autom

APA, Harvard, Vancouver, ISO, and other styles

39

Kang, En Shun, and Yu Xi Zhao. "The Realization of Rapid Median Filter Algorithm on FPGA." Advanced Engineering Forum 6-7 (September 2012): 659–64. http://dx.doi.org/10.4028/www.scientific.net/aef.6-7.659.

Full text

Abstract:

Traditional median filter algorithm has the long processing time, which goes against the real-time image processing. According to its shortcomings, this paper puts forward the rapid median filter algorithm, and uses DE2 board of the company called Altera to do the realization on FPGA (CycloneII 2C35). The experimental results show that the image pre-processing system is able to complete a variety of high-level image algorithms in milliseconds, and FPGA's parallel processing capability and pipeline operations can dramatically improve the speed of image processing, so the FPGA-based image proces

APA, Harvard, Vancouver, ISO, and other styles

40

Zhou, Yu Bin. "Panoramic Vision System for Autonomous Driving Vehicle." Applied Mechanics and Materials 644-650 (September 2014): 497–501. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.497.

Full text

Abstract:

High effective vision system is important for autonomous driving vehicles. A panoramic vision system based on FPGA+DSP with 6-camera for intelligent vehicles is presented in this paper. The system includes digital image acquisition module and high image processing module which work independently to each other. The including two C6416 DSP chips and one high-performance Virtex-4 FPGA to achieve the complex real-time image processing during autonomous driving, such as cylindrical panoramic image rebuilding, lane detection and tracking. The proposed algorithm was also optimized according to the sp

APA, Harvard, Vancouver, ISO, and other styles

41

Yang, Fu, Wen Ming Zhang, and Wan Cai Jiao. "The Application and Prospects of SOPC Technology in Image-Processing." Applied Mechanics and Materials 644-650 (September 2014): 4048–51. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.4048.

Full text

Abstract:

The real-time image-processing by SOPC technology on the hardware is the new direction of the image-processing technology. FPGA is the core component of the image-processing based on SOPC technology. The principles and characteristics of SOPC technology and the commonly image-processing algorithm are introduced in the first part. Then the traditional DSP image-processing technology is compared with the image-processing technology using FPGA chip embedding with the Nios II soft-core processor. As a result, a conclusion that the usage of the SOPC technology can increase the speed and working fre

APA, Harvard, Vancouver, ISO, and other styles

42

Ngo, Dat, Jeonghyeon Son, and Bongsoon Kang. "VBI-Accelerated FPGA Implementation of Autonomous Image Dehazing: Leveraging the Vertical Blanking Interval for Haze-Aware Local Image Blending." Remote Sensing 17, no. 5 (2025): 919. https://doi.org/10.3390/rs17050919.

Full text

Abstract:

Real-time image dehazing is crucial for remote sensing systems, particularly in applications requiring immediate and reliable visual data. By restoring contrast and fidelity as images are captured, real-time dehazing enhances image quality on the fly. Existing dehazing algorithms often prioritize visual quality and color restoration but rely on computationally intensive methods, making them unsuitable for real-time processing. Moreover, these methods typically perform well under moderate to dense haze conditions but lack adaptability to varying haze levels, limiting their general applicability

APA, Harvard, Vancouver, ISO, and other styles

43

ZHAO Fan, 赵凡, and 张葆 ZHANG Bao. "Aerial image enhancement processing based on FPGA." Chinese Journal of Liquid Crystals and Displays 29, no. 5 (2014): 793–99. http://dx.doi.org/10.3788/yjyxs20142905.0793.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

SHI, Haobin, and Hangyu HU. "Acceleration method of infrared image detail enhancement on FPGA." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 40, no. 3 (2022): 524–29. http://dx.doi.org/10.1051/jnwpu/20224030524.

Full text

Abstract:

Among the many cockpit human-computer interaction systems of airborne, vehicle-mounted, and ship-borne platforms, the image detail enhancement technology can improve the ability of personnel to interpret infrared images, which has very important application requirements. The enhanced algorithm running on the embedded computing platform needs to have a higher processing speed and smaller time delay in meeting the needs of real-time interaction. The current infrared video sensor usually has a lower resolution, and the image detail enhancement algorithm still can achieve real-time processing perf

APA, Harvard, Vancouver, ISO, and other styles

45

Liu, Dingwei. "The efficient application analysis of FPGA in automotive intelligent control." Applied and Computational Engineering 54, no. 1 (2024): 57–63. http://dx.doi.org/10.54254/2755-2721/54/20241261.

Full text

Abstract:

In recent times, the automotive industry has witnessed a remarkable transformation with the rapid development of automotive intelligent control systems. This evolution has shifted consumer expectations from cars being mere modes of transportation to multifunctional lifestyle assistants. A pivotal player in this transformative journey is Field-Programmable Gate Arrays (FPGAs), which have made significant contributions by delivering high-performance and efficiency enhancements across various facets of automotive intelligent control. This article delves into the diverse applications of FPGA techn

APA, Harvard, Vancouver, ISO, and other styles

46

Mishra, Raj Gaurav, and Amit Kumar Shrivastava. "Implementation of Custom Precision Floating Point Arithmetic on FPGAs." HCTL Open International Journal of Technology Innovations and Research (IJTIR) 1, January 2013 (2013): 10–26. https://doi.org/10.5281/zenodo.160887.

Full text

Abstract:

Floating point arithmetic is a common requirement in signal processing, image processing and real time data acquisition & processing algorithms. Implementation of such algorithms on FPGA requires an efficient implementation of floating point arithmetic core as an initial process. We have presented an empirical result of the implementation of custom-precision floating point numbers on an FPGA processor using the rules of IEEE standards defined for single and double precision floating point numbers. Floating point operations are difficult to implement on FPGAs because of their complexity in

APA, Harvard, Vancouver, ISO, and other styles

47

Yang, Zhuoyue. "Saturation Adjustment of Image Enhancement Based on FPGA." Applied and Computational Engineering 120, no. 1 (2025): 187–92. https://doi.org/10.54254/2755-2721/2025.19486.

Full text

Abstract:

FPGA can allow designers to produce hardware functions quickly in accordance with requirements. Because of its flexibility and parallel processing ability. It has been widely used in image, signal processing and other fields. Image saturation is an important standard to describe image quality, which affects the color brightness and visual perception of the image. At the same time, image enhancement, it is an important part of enhancing image visual effects and improving image quality. Combined with the above two points, the high-speed parallel capability of FPGA can be used to carry out comple

APA, Harvard, Vancouver, ISO, and other styles

48

Li, Jun, Qiong Hou, and Yingjie Zhou. "Image Acquisition and Processing System based on ZYNQ." Scientific Journal of Technology 4, no. 7 (2022): 65–70. http://dx.doi.org/10.54691/sjt.v4i7.1277.

Full text

Abstract:

With the advancement of manufacturing processes, imaging sensors have become more and more sophisticated, the amount of image data generated is increasing, and application scenarios and functional algorithms have become more and more complex. The traditional serial processing method can no longer meet the real-time requirements of image processing. The use of hardware to accelerate image algorithms has become a basic trend in image acquisition and processing systems. Xilinx’s Zynq7000 series chip integrates a dual-core A9 series ARM processor (PS) and an A7 series FPGA (PL). The industry stand

APA, Harvard, Vancouver, ISO, and other styles

49

Kyriakos, Angelos, Elissaios-Alexios Papatheofanous, Charalampos Bezaitis, and Dionysios Reisis. "Resources and Power Efficient FPGA Accelerators for Real-Time Image Classification." Journal of Imaging 8, no. 4 (2022): 114. http://dx.doi.org/10.3390/jimaging8040114.

Full text

Abstract:

A plethora of image and video-related applications involve complex processes that impose the need for hardware accelerators to achieve real-time performance. Among these, notable applications include the Machine Learning (ML) tasks using Convolutional Neural Networks (CNNs) that detect objects in image frames. Aiming at contributing to the CNN accelerator solutions, the current paper focuses on the design of Field-Programmable Gate Arrays (FPGAs) for CNNs of limited feature space to improve performance, power consumption and resource utilization. The proposed design approach targets the design

APA, Harvard, Vancouver, ISO, and other styles

50

P., Visconti, Velazquez R., Del-Valle-Soto Carolina, and de Fazio R. "FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review." TELKOMNIKA (Telecommunication, Computing, Electronics and Control) 19, no. 4 (2021): 1291–306. https://doi.org/10.12928/telkomnika.v19i4.18400.

Full text

Abstract:

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel charac

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!