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Relevant bibliographies by topics / Independent-gate Asymmetric Double Gate MOSFET

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Academic literature on the topic 'Independent-gate Asymmetric Double Gate MOSFET'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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Journal articles on the topic "Independent-gate Asymmetric Double Gate MOSFET"

1

Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, Sheng Li, Long Zhang, Jiaxing Wei, Siyang Liu, Weifeng Sun, Weili Wu, and Song Bai. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (January 8, 2022): 457. http://dx.doi.org/10.3390/ma15020457.

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The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

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2

Singh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.

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Purpose This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs. Design/methodology/approach This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach. Findings It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement. Originality/value Compact Analytical models for undoped symmetric double gate MOSFETs.

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3

Abebe, H., E. Cumberbatch, H. Morris, V. Tyree, T. Numata, and S. Uno. "Symmetric and Asymmetric Double Gate MOSFET Modeling." JSTS:Journal of Semiconductor Technology and Science 9, no. 4 (December 30, 2009): 225–32. http://dx.doi.org/10.5573/jsts.2009.9.4.225.

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4

Zou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (January 13, 2022): 598. http://dx.doi.org/10.3390/ma15020598.

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In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure.

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5

Jung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.

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Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

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6

Jung, Hakkee. "Analysis for Gate Oxide Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 4 (April 30, 2014): 885–90. http://dx.doi.org/10.6109/jkiice.2014.18.4.885.

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7

Jung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.

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In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.

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8

Jung, Hakkee. "Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 6 (June 30, 2014): 1422–28. http://dx.doi.org/10.6109/jkiice.2014.18.6.1422.

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9

Ortiz-Conde, Adelmo, and Francisco J. García-Sánchez. "Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET." Solid-State Electronics 57, no. 1 (March 2011): 43–51. http://dx.doi.org/10.1016/j.sse.2010.10.023.

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10

Jung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Voltage of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 3 (March 31, 2014): 657–62. http://dx.doi.org/10.6109/jkiice.2014.18.3.657.

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Dissertations / Theses on the topic "Independent-gate Asymmetric Double Gate MOSFET"

1

Moolamalla, Himaja Reddy. "An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377751&SrchMode=1&sid=5&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277473834&clientId=28564.

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2

Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2346.

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For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two conﬁgurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

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3

Srivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2346.

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Abstract:

For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. In order to continue the technology scaling beyond 22nm node, it is clear that conventional bulk-MOSFET needs to be replaced by new device architectures, most promising being the Multiple-Gate MOSFETs (MuGFET). Intel in mid 2011 announced the use of bulk Tri-Gate FinFETs in 22nm high volume logic process for its next-gen IvyBridge Microprocessor. It is expected that soon other semiconductor companies will also adopt the MuGFET devices. As like bulk-MOSFET, an accurate and physical compact model is important for MuGFET based circuit design. Compact modeling effort for MuGFET started in late nineties with planar double gate MOSFET(DGFET),as it is the simplest structure that one can conceive for MuGFET devices. The models so far proposed for DG MOSFETs are applicable for common gate symmetric DG (SDG) MOSFETs where both the gates have equal oxide thicknesses. However, for practical devices at nanoscale regime, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. At the same time, Independently controlled DG(IDG) MOSFETs have gained tremendous attention owing to its ability to modulate threshold voltage and transconductance dynamically. Due to the asymmetric nature of the electrostatic, developing efficient compact models for asymmetric/independent DG MOSFET is a daunting task. In this thesis effort has been put to provide some solutions to this challenge. We propose simple surface-potential based compact terminal charge models, applicable for Asymmetric Double gate MOSFETs (ADG) in two conﬁgurations1) Common-gate 2) Independent-gate. The charge model proposed for the common-gate ADG (CDG) MOSFET is seamless between the symmetric and asymmetric devices and utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and can be easily implemented in any circuit simulator and extendable to short-channel devices. The charge model proposed for independent ADG(IDG)MOSFET is based on a novel piecewise linearization technique of surface potential along the channel. We show that the conventional “charge linearization techniques that have been used over the years in advanced compact models for bulk and double-gate(DG) MOSFETs are accurate only when the channel is fully hyperbolic in nature or the effective gate voltages are same. For other bias conditions, it leads to significant error in terminal charge computation. We demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel for a particular bias condition actually dictates if the conventional charge linearization technique could be applied or not. We propose a piecewise linearization technique that segments the channel into multiple sections where in each section, the assumption of quasi-linear relationship between the surface potentials remains valid. The cumulative sum of the terminal charges obtained for each of these channel sections yield terminal charges of the IDG device. We next present our work on modeling the non-ideal scenarios like presence of body doping in CDG devices and the non-planar devices like Tri-gate FinFETs. For a fully depleted channel, a simple technique to include body doping term in our charge model for CDG devices, using a perturbation on the effective gate voltage and correction to the coupling factor, is proposed. We present our study on the possibility of mapping a non-planar Tri-gate FinFET onto a planar DG model. In this framework, we demonstrate that, except for the case of large or tall devices, the generic mapping parameters become bias-dependent and an accurate bias-independent model valid for geometries is not possible. An efficient and robust “Root Bracketing Method” based algorithm for computation of surface potential in IDG MOSFET, where the conventional Newton-Raphson based techniques are inefficient due to the presence of singularity and discontinuity in input voltage equations, is presented. In case of small asymmetry for a CDG devices, a simple physics based perturbation technique to compute the surface potential with computational complexity of the same order of an SDG device is presented next. All the models proposed show excellent agreement with numerical and Technology Computer-Aided Design(TCAD) simulations for all wide range of bias conditions and geometries. The models are implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

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4

Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.

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Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally eﬃcient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, eﬃcient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational eﬃciency at the same level. Such eﬀort aims to generalize the compact model and also to capture the oxide thickness asymmetry eﬀect, which might prevail in practical devices due to process uncertainties and thus aﬀects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work eﬀort has been put to include Non-Quasistatic (NQS) eﬀects, diﬀerent small-geometry eﬀects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry eﬀects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

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5

Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.

Full text

Abstract:

Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally eﬃcient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, eﬃcient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this work we explore the possibility of developing models without this approximation, while preserving the computational eﬃciency at the same level. Such eﬀort aims to generalize the compact model and also to capture the oxide thickness asymmetry eﬀect, which might prevail in practical devices due to process uncertainties and thus aﬀects the device performance significantly. However solution to this modeling problem is nontrivial due to the bias-dependent asym-metric nature of the electrostatic. Using the single implicit equation based Poisson so-lution and the unique quasi-linear relationship between the surface potentials, previous researchers of our laboratory have reported the core model for such asymmetric CDG MOSFET. In this work eﬀort has been put to include Non-Quasistatic (NQS) eﬀects, diﬀerent small-geometry eﬀects, and noise model to this core, so that the model becomes suitable for practical applications. It is demonstrated that the quasi-linear relationship between the surface potentials remains preserved under NQS condition, in the presence of all small geometry eﬀects. This property of the device along with some other new techniques are used to develop the model while keeping the mathematical complexity at the same level of the models reported for the symmetric devices. Proposed model is verified against TCAD simulation for various device geometries and successfully imple-mented in professional circuit simulator. The model passes the source/drain symmetry test and good convergence is observed during standard circuit simulations.

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6

Liu, Shou-En, and 劉守恩. "Threshold Voltage Model of Asymmetry Double Gate MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23002033707927316207.

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7

Hung, Wan-Te, and 洪萬得. "The Investigation on Subthreshold Behavior Model for Asymmetrical Double-gate MOSFETs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/91003057503160193581.

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碩士
南台科技大學
電子工程系
95
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. A number of authors have ap-plied various simplifying assumptions to model the SCE of DG fully-depleted MOS-FETs analytically. Some of them make use of a parabolic potential approximation ap-proach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical threshold voltage model for fully depleted Asymmetric DG MOSFETs by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator. Without any fitting parameters, these analytical results are useful in predictive compact modeling of Asymmetric DG MOSFETs. The model shows the distribution of electric potential, short channel thresh-old voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing) and drain-induced barrier lowering (DIBL) effects. The new model is verified by published numerical simulations with close agreement. Due to its computational efficiency, this model can be applied for SPICE simulation.

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8

Hsun, Chiang Tsung, and 蔣宗勳. "The Investigation on Subthreshold Behavior Model for Asymmetrical Dual Material Double-gate MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87319086508650725079.

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碩士
南台科技大學
電子工程系
96
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. Besides, we use dual material on the front gate to overcome Short Channel Effect (SCE). A number of authors have applied various simplifying assumptions to model the SCE of DMDG fully-depleted MOSFETs analytically. Some of them make use of a parabolic potential approximation approach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical sub-threshold be-havior model for fully depleted ADMDG MOSFET’s by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation. Without any fitting parameters, these analytical results are useful in predictive compact modeling of ADMDG MOSFET’s. The model shows the distribution of elec-tric potential, electric field, short channel threshold voltage roll-off (ΔVTH), sub-threshold current and sub-threshold slope (Swing). The new model is verified by published numerical simulations with close agreement. Due to its computational effi-ciency, this model can be applied for SPICE simulation.

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Book chapters on the topic "Independent-gate Asymmetric Double Gate MOSFET"

1

Yadava, Narendra, Vimal K. Mishra, and R. K. Chauhan. "Analysis of N+N− Epi-Source Asymmetric Double Gate FD-SOI MOSFET." In Advances in Intelligent Systems and Computing, 541–49. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7566-7_54.

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2

Basak, Arighna, Arpan Deyasi, and Angsuman Sarkar. "Impact of Negative Bottom Gate Voltage for Improvement of RF/Analog Performance in Asymmetric Junctionless Dual Material Double Gate MOSFET." In Lecture Notes in Electrical Engineering, 153–62. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6301-8_12.

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Kumar, Amrish, Abhinav Gupta, and Sanjeev Rai. "A Comparative Analysis of Asymmetrical and Symmetrical Double Metal Double Gate SOI MOSFETs at the Zero-Temperature-Coefficient Bias Point." In Lecture Notes in Electrical Engineering, 517–26. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2685-1_49.

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Conference papers on the topic "Independent-gate Asymmetric Double Gate MOSFET"

1

Vaddi, Ramesh, S. Dasgupta, and R. P. Agarwal. "Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features." In 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2011. http://dx.doi.org/10.1109/icedsa.2011.5959057.

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2

Kim, Jae-joon, Keunwoo Kim, and Ching-te Chuang. "Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability." In 2006 Proceedings of the 32nd European Solid-State Circuits Conference. IEEE, 2006. http://dx.doi.org/10.1109/esscir.2006.307534.

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Kim, Jae-joon, Keunwoo Kim, and Ching-te Chuang. "Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability." In 2006 European Solid-State Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/essder.2006.307641.

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4

Jung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET." In Electrical Engineering 2013. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.37.07.

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Jilowa, Sudarshana, Sandeep Singh Gill, and Gurjot Kaur Walia. "Design of 3C-SiC symmetric and asymmetric double gate MOSFET." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593052.

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Hazarika, Mustafizur Rahman, and Nipanka Bora. "Performance analysis of 3-D asymmetric junctionless double gate MOSFET." In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389672.

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Liu, Feng, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, and Mansun Chan. "Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes." In 2008 9th International Symposium of Quality of Electronic Design (ISQED). IEEE, 2008. http://dx.doi.org/10.1109/isqed.2008.4479738.

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Ortiz-Conde, Adelmo, Francisco Garcia Sanchez, Slavica Malobabic, Juan Muci, and Ram�n Salazar. "Drain Current and Transconductance Model for the Undoped Body Asymmetric Double-Gate MOSFET." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306103.

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Riyadi, Munawar A. "Performance comparison of asymmetric drain/source topology in nanoscale Double Gate vertical MOSFET." In 2013 International Conference on Information Technology and Electrical Engineering (ICITEE). IEEE, 2013. http://dx.doi.org/10.1109/iciteed.2013.6676285.

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Mishra, Abhijit, Subir Kumar Maity, and Sayantika Dutta. "Effect of spacer dielectric of asymmetric underlap double gate MOSFET on SRAM performance." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8074067.

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