Academic literature on the topic 'Independent-gate Asymmetric Double Gate MOSFET'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Independent-gate Asymmetric Double Gate MOSFET.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Journal articles on the topic "Independent-gate Asymmetric Double Gate MOSFET"
Wei, Zhaoxiang, Hao Fu, Xiaowen Yan, Sheng Li, Long Zhang, Jiaxing Wei, Siyang Liu, Weifeng Sun, Weili Wu, and Song Bai. "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example." Materials 15, no. 2 (January 8, 2022): 457. http://dx.doi.org/10.3390/ma15020457.
Full textSingh, Ajay Kumar. "Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 2 (March 4, 2019): 815–28. http://dx.doi.org/10.1108/compel-08-2018-0327.
Full textAbebe, H., E. Cumberbatch, H. Morris, V. Tyree, T. Numata, and S. Uno. "Symmetric and Asymmetric Double Gate MOSFET Modeling." JSTS:Journal of Semiconductor Technology and Science 9, no. 4 (December 30, 2009): 225–32. http://dx.doi.org/10.5573/jsts.2009.9.4.225.
Full textZou, Yuan, Jue Wang, Hongyi Xu, and Hengyu Wang. "Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions." Materials 15, no. 2 (January 13, 2022): 598. http://dx.doi.org/10.3390/ma15020598.
Full textJung, Hakkee. "Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 163. http://dx.doi.org/10.11591/ijece.v9i1.pp163-169.
Full textJung, Hakkee. "Analysis for Gate Oxide Dependent Subthreshold Swing of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 4 (April 30, 2014): 885–90. http://dx.doi.org/10.6109/jkiice.2014.18.4.885.
Full textJung, Hakkee. "Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (February 1, 2021): 240. http://dx.doi.org/10.11591/ijece.v11i1.pp240-248.
Full textJung, Hakkee. "Bottom Gate Voltage Dependent Threshold Voltage Roll-off of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 6 (June 30, 2014): 1422–28. http://dx.doi.org/10.6109/jkiice.2014.18.6.1422.
Full textOrtiz-Conde, Adelmo, and Francisco J. García-Sánchez. "Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET." Solid-State Electronics 57, no. 1 (March 2011): 43–51. http://dx.doi.org/10.1016/j.sse.2010.10.023.
Full textJung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Voltage of Asymmetric Double Gate MOSFET." Journal of the Korea Institute of Information and Communication Engineering 18, no. 3 (March 31, 2014): 657–62. http://dx.doi.org/10.6109/jkiice.2014.18.3.657.
Full textDissertations / Theses on the topic "Independent-gate Asymmetric Double Gate MOSFET"
Moolamalla, Himaja Reddy. "An analysis on the simulation of the leakage currents of independent double gate SOI MOSFET transistors a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377751&SrchMode=1&sid=5&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277473834&clientId=28564.
Full textSrivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. https://etd.iisc.ac.in/handle/2005/2346.
Full textSrivatsava, J. "Compact Modeling Of Asymmetric/Independent Double Gate MOSFET." Thesis, 2012. http://etd.iisc.ernet.in/handle/2005/2346.
Full textSharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.
Full textSharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.
Full textLiu, Shou-En, and 劉守恩. "Threshold Voltage Model of Asymmetry Double Gate MOSFET." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23002033707927316207.
Full textHung, Wan-Te, and 洪萬得. "The Investigation on Subthreshold Behavior Model for Asymmetrical Double-gate MOSFETs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/91003057503160193581.
Full text南台科技大學
電子工程系
95
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. A number of authors have ap-plied various simplifying assumptions to model the SCE of DG fully-depleted MOS-FETs analytically. Some of them make use of a parabolic potential approximation ap-proach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical threshold voltage model for fully depleted Asymmetric DG MOSFETs by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation in both regions of Si body and gate insulator. Without any fitting parameters, these analytical results are useful in predictive compact modeling of Asymmetric DG MOSFETs. The model shows the distribution of electric potential, short channel thresh-old voltage roll-off (ΔVTH), subthreshold current, subthreshold slope (Swing) and drain-induced barrier lowering (DIBL) effects. The new model is verified by published numerical simulations with close agreement. Due to its computational efficiency, this model can be applied for SPICE simulation.
Hsun, Chiang Tsung, and 蔣宗勳. "The Investigation on Subthreshold Behavior Model for Asymmetrical Dual Material Double-gate MOSFETs." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87319086508650725079.
Full text南台科技大學
電子工程系
96
In recent years, studies about Double-Gate (DG) transistor have successively been proposed, and have attracted a lot of attention. As CMOS is scaled to the limit, dou-ble-gate (DG) MOSFET becomes increasingly important. Besides, we use dual material on the front gate to overcome Short Channel Effect (SCE). A number of authors have applied various simplifying assumptions to model the SCE of DMDG fully-depleted MOSFETs analytically. Some of them make use of a parabolic potential approximation approach for the device in the direction perpendicular to the surface. This results in a scale length proportional to the oxide and the silicon thickness. Large errors occur when one of thickness is much less than the other. Other approaches apply the superposition method to solve the 2-D boundary-value problem for the bulk MOSFETs. Most of them only put focus on device scaling scheme, threshold degradation by ignoring the 2-D ef-fects in the gate oxide. In order to give insight into the device physics, we need to de-velop a consolidated threshold voltage model for the DG transistor with fully 2-D ef-fects included in both silicon and gate oxide regions. In this thesis, we successfully develop a physical and analytical sub-threshold be-havior model for fully depleted ADMDG MOSFET’s by use of the 2-D analytical solu-tion in the entire region of the device based on fully closed-form solutions of Poisson’s equation. Without any fitting parameters, these analytical results are useful in predictive compact modeling of ADMDG MOSFET’s. The model shows the distribution of elec-tric potential, electric field, short channel threshold voltage roll-off (ΔVTH), sub-threshold current and sub-threshold slope (Swing). The new model is verified by published numerical simulations with close agreement. Due to its computational effi-ciency, this model can be applied for SPICE simulation.
Book chapters on the topic "Independent-gate Asymmetric Double Gate MOSFET"
Yadava, Narendra, Vimal K. Mishra, and R. K. Chauhan. "Analysis of N+N− Epi-Source Asymmetric Double Gate FD-SOI MOSFET." In Advances in Intelligent Systems and Computing, 541–49. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7566-7_54.
Full textBasak, Arighna, Arpan Deyasi, and Angsuman Sarkar. "Impact of Negative Bottom Gate Voltage for Improvement of RF/Analog Performance in Asymmetric Junctionless Dual Material Double Gate MOSFET." In Lecture Notes in Electrical Engineering, 153–62. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6301-8_12.
Full textKumar, Amrish, Abhinav Gupta, and Sanjeev Rai. "A Comparative Analysis of Asymmetrical and Symmetrical Double Metal Double Gate SOI MOSFETs at the Zero-Temperature-Coefficient Bias Point." In Lecture Notes in Electrical Engineering, 517–26. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2685-1_49.
Full textConference papers on the topic "Independent-gate Asymmetric Double Gate MOSFET"
Vaddi, Ramesh, S. Dasgupta, and R. P. Agarwal. "Two dimensional analytical subthreshold swing model of a double gate MOSFET with Gate-S/D underlap, asymmetric and independent gate features." In 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2011. http://dx.doi.org/10.1109/icedsa.2011.5959057.
Full textKim, Jae-joon, Keunwoo Kim, and Ching-te Chuang. "Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability." In 2006 Proceedings of the 32nd European Solid-State Circuits Conference. IEEE, 2006. http://dx.doi.org/10.1109/esscir.2006.307534.
Full textKim, Jae-joon, Keunwoo Kim, and Ching-te Chuang. "Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability." In 2006 European Solid-State Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/essder.2006.307641.
Full textJung, Hakkee. "Subthreshold Swing for Top and Bottom Gate Oxide Thickness of Asymmetric Double Gate MOSFET." In Electrical Engineering 2013. Science & Engineering Research Support soCiety, 2013. http://dx.doi.org/10.14257/astl.2013.37.07.
Full textJilowa, Sudarshana, Sandeep Singh Gill, and Gurjot Kaur Walia. "Design of 3C-SiC symmetric and asymmetric double gate MOSFET." In 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA). IEEE, 2016. http://dx.doi.org/10.1109/vlsi-sata.2016.7593052.
Full textHazarika, Mustafizur Rahman, and Nipanka Bora. "Performance analysis of 3-D asymmetric junctionless double gate MOSFET." In 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS). IEEE, 2017. http://dx.doi.org/10.1109/icecds.2017.8389672.
Full textLiu, Feng, Jin He, Yue Fu, Jinhua Hu, Wei Bian, Yan Song, Xing Zhang, and Mansun Chan. "Generic Carrier-Based Core Model for Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes." In 2008 9th International Symposium of Quality of Electronic Design (ISQED). IEEE, 2008. http://dx.doi.org/10.1109/isqed.2008.4479738.
Full textOrtiz-Conde, Adelmo, Francisco Garcia Sanchez, Slavica Malobabic, Juan Muci, and Ram�n Salazar. "Drain Current and Transconductance Model for the Undoped Body Asymmetric Double-Gate MOSFET." In 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/icsict.2006.306103.
Full textRiyadi, Munawar A. "Performance comparison of asymmetric drain/source topology in nanoscale Double Gate vertical MOSFET." In 2013 International Conference on Information Technology and Electrical Engineering (ICITEE). IEEE, 2013. http://dx.doi.org/10.1109/iciteed.2013.6676285.
Full textMishra, Abhijit, Subir Kumar Maity, and Sayantika Dutta. "Effect of spacer dielectric of asymmetric underlap double gate MOSFET on SRAM performance." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8074067.
Full text