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Dissertations / Theses on the topic 'Input buffer'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 July 2025

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1

Niemelä, J. (Jari). "Design and verification of a logic input buffer." Master's thesis, University of Oulu, 2014. http://urn.fi/URN:NBN:fi:oulu-201402121090.

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Two low-power logic input buffer topologies are designed, simulated and compared. The most important parameters of the buffers are input threshold voltage level stability and minimal current consumption. Topologies have been implemented earlier for a wider line width process, and now the intention is to move them to a narrower line width process without losing performance. Based on the simulations, a topology with the better performance and smaller area is chosen and layout for particular topology is designed. Layout parasitics effect to the performance is also verified by simulations. In this

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2

Lundberg, Jesper, and Ronja Mehtonen. "Utvärdering och analys av batchstorlekar, produktsekvenser och omställningstider." Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-11859.

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Volvo GTO is one of the strongest brands in the truck industry, with a long and proud history of world-leading innovations. The factory in Skövde produces diesel engines of various sizes to Volvo GTO. The project has been carried out on the processing part of grovdel crankshaft. Where the objective was to construct a simulation model that reflects flows 0, 1 and 2 on the crankshaft grovdel order to produce the best driving style for the size of the batches and sequences, focusing on PIA, between the stock and conversion-up times. A theoretical study intervention gave knowledge to the methodolo

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3

Jacobson, Mark Alan. "Input and response buffers in transcription handwriting." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/28862.

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4

Nguyen, Kim-Minh Carleton University Dissertation Engineering Electronics. "Module generators for the layout synthesis of BiCMOS input/output buffers." Ottawa, 1993.

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5

Charny, Anna. "Providing QoS guarantees in input buffered crossbar switches with speedup." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/9628.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 103-105).<br>This dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-bu

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6

Tabatabaee, Vahid. "Scheduling and rate provisioning for input-buffered cell based switch fabrics." College Park, Md. : University of Maryland, 2003. http://hdl.handle.net/1903/141.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2003.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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7

Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.

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The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synth

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8

Wang, Chen-Tai, and 王振泰. "The Design of a Serial Input Random Output Buffer." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/07289474930284679804.

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9

Liu, Dequan. "Joint buffer management and scheduling for input queued switches." Thesis, 2003. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2003-024.

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10

Peng, Chih-Yang, and 彭志洋. "Block and Input/Ouput Buffer Placement in Flip-Chip Design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61649670636516290542.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>91<br>The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as

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11

Hu, Ting-Wei, and 胡庭維. "Input Buffer Improved High Speed Asynchronous Successive Approximation Register ADC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/70012398542253459114.

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碩士<br>國立中興大學<br>電機工程學系所<br>104<br>This thesis presents an input buffer improved high speed Asynchronous successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The application is as a sub-ADC of a time-interleaved ADC. In order to enhance the converter’s effective number of bits, the input buffer is added. The frist design, Sarf2_34 ,has oscillations found during measurement. Thus a second design Sarf2_35 improve the input buffer circuit to solve, the output waveform oscillation issue. With TSMC 90nm GUTM manufacturing process, and sampling frequency as 166MHZ, measurement

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12

Varma, Ambrish Kant. "Improved behavioral modeling based on the input output buffer information specification." 2007. http://www.lib.ncsu.edu/theses/available/etd-01042007-012012/unrestricted/etd.pdf.

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13

Chao, Wen-Chang. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design." 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2907200414064000.

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14

Chao, Wen-Chang, and 趙文璋. "Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/6565c8.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>92<br>The flip-chip package gives the highest chip density of any packaging methods to support the pad-limited ASIC design. One of the most important characteristics of flip chip designs is that the input/output buffers could be placed anywhere inside a chip. For most practical designs, we have to control the timing of the input/output signals. This can be achieved through controlling the positions of bump balls, input/output buffers, and first-stage/last-stage cells in a flip chip. Specifically, we intend to minimize the path length between blocks and bump balls as

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15

Narayana, Sagar 1986. "Throughput-Efficient Network-on-Chip Router Design with STT-MRAM." Thesis, 2012. http://hdl.handle.net/1969.1/148157.

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As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizi

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16

Lin, Chun-Yuan, and 林俊源. "On the Design of Optical Buffer for Optical Input-Queued Switches with Quality of Service Guarantees." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/44759898443916227840.

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碩士<br>國立交通大學<br>資訊科學系所<br>93<br>This paper presents a quality of service (QoS) enable optical delay line (ODL) architecture to solve the problem of resource contention and support multilevel priority queues in an optical packet switch. ODL has been used in optical packet switches to resolve resource contention; however, the packets travel continuously in ODL limits the management of random access of the packets and increases the packet loss probability. Moreover, multiple ODL sets usually are needed to realize multiple priority queues in order to support QoS. In this paper, a new Unicast Recir

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17

Leonardo, David Barros. "Design of High-Bandwidth and High-Linearity Input Buffers for ADCs." Master's thesis, 2020. http://hdl.handle.net/10362/110350.

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Nowadays on-chip Input Buffers (IBs) for direct conversion front-ends are realized with a higher voltage supply than that of the core voltage of the technology, mainly for linearity purposes. This, in turn, makes it mandatory to have more than one voltage source to supply a single chip in addition to having devices capable of handling higher voltages. This work explores the possibility of having IBs supplied with the technology’s core voltage to standardize all of the devices and reducing the different voltage supply sources and/or voltage regulators needed for operating the front-end d

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18

Min, Geyong, and X. Jin. "Analytical Modelling and Optimization of Congestion Control for Prioritized Multi-Class Self-Similar Traffic." 2013. http://hdl.handle.net/10454/9689.

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No<br>Traffic congestion in communication networks can dramatically deteriorate user-perceived Quality-of-Service (QoS). The integration of the Random Early Detection (RED) and priority scheduling mechanisms is a promising scheme for congestion control and provisioning of differentiated QoS required by multimedia applications. Although analytical modelling of RED congestion control has received significant research efforts, the performance models reported in the current literature were primarily restricted to the RED algorithm only without consideration of traffic scheduling scheme for QoS dif

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19

He, Chen-Yu, and 何宸宇. "A Sub-ns-Access with Sub-mW/GHz 32Kb 5T SRAM Implementation and A Multi-Bit Buffer Design of ADC Input for In-SRAM Computing Architecture." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/kgce86.

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碩士<br>國立交通大學<br>電子研究所<br>108<br>This thesis has two portions, one is low power and high speed SRAM design. In this design, we propose a new 5T SRAM cells with multiple power supply voltages pulsed. Besides, we apply compact array architecture and open-BL to have smaller core area as compared to memory compiler. In idle, read or write mode, using assistant circuits and adaptive supply voltages of cells to optimize speed, power and reliability, respectively. Moreover, the design of tracking circuit is to ensure control correctness within PVT variation. In 28nm CMOS technology, the measurement re

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20

Chen, M., X. L. Jin, Y. Z. Wang, X. Q. Cheng, and Geyong Min. "Modelling priority queuing systems with varying service capacity." 2013. http://hdl.handle.net/10454/9635.

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No<br>Many studies have been conducted to investigate the performance of priority queuing (PQ) systems with constant service capacity. However, due to the time-varying nature of wireless channels in wireless communication networks, the service capacity of queuing systemsmay vary over time. Therefore, it is necessary to investigate the performance of PQ systems in the presence of varying service capacity. In addition, self-similar traffic has been discovered to be a ubiquitous phenomenon in various communication networks, which poses great challenges to performance modelling of scheduling syste

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21

Wu, Hsien. "Separate short-term memory buffers for input and output phonology." Thesis, 2003. http://hdl.handle.net/1911/18581.

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Evidence from brain-damaged patients suggests that there are separate buffers for input and output phonological retention in verbal short-term memory (STM). This possible distinction was investigated with college students (Experiment 1 to 3) and deaf signers of American Sign Language (ASL) (Experiment 4) using different verbal materials in a serial probed recall paradigm. It is reasoned that natural linguistic input (speech for hearing people and ASL for deaf people) would be stored in an input phonological buffer whereas internally generated phonology derived from reading, naming pictured obj

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22

"Performance analysis of iterative matching scheduling algorithms in ATM input-buffered switches." 1999. http://library.cuhk.edu.hk/record=b5889961.

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by Cheng Sze Wan.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.<br>Includes bibliographical references (leaves 72-[76]).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Background --- p.1<br>Chapter 1.2 --- Traffic Scheduling in Input-buffered Switches .。 --- p.3<br>Chapter 1.3 --- Organization of Thesis --- p.7<br>Chapter 2 --- Principle of Enchanced PIM Algorithm --- p.8<br>Chapter 2.1 --- Introduction --- p.8<br>Chapter 2.1.1 --- Switch Model --- p.9<br>Chapter 2.2 --- Enhanced Parallel Iterative Matching Algorithm (EPIM) --

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23

王翹楚. "Single-Buffered banyan network with input buffering and priority assignment on ATM networks." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/84787921776002104414.

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24

Shian-Sung, Shiu, and 徐獻松. "Burst Performance of Input/Output Buffered ATM Switch with Speed Up and Unblanced Traffic." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/10229832334604412958.

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碩士<br>國立臺灣科技大學<br>電機工程系<br>90<br>With the huge bandwidth (i.e., the data transmission rate) available from optical fiber, the performance bottleneck of ATM-based broadband network has shifted from data transmission rate to processing power of ATM switches and propagation delay of transmission media. With the stochastic nature of input traffic, buffering is an indispensable element of all ATM switches. Although due to the head-of-line effect the throughput with input buffering is significantly lower than that with output buffering, output buffering implies higher complexity. To balance the perf

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25

Huang, Chien-Chang, and 黃建章. "Area-Efficient Layout Design for Output and Input Buffers to Improve Driving Capability and ESD Robustness of CMOS VLSI." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/38572546648099296051.

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碩士<br>國立交通大學<br>電子研究所<br>84<br>In this thesis, we propose three new layout designs of output and input buffers of CMOS IC''s. While the CMOS technology has been scaled down into deep-submicron regime with thinner gate oxide, shorter channel length, shallow drain/source junction, LDD (lightly-doped drain) structure, and silicided diffusion, these advanced processes cause serious degradation on the ESD robustness of CMOS IC''s. To achieve the required ESD robustness, the output buffer, which

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26

Chen, Wen-Jyh, and 陳文智. "On Service Guarantees for Input Buffered Crossbar Switches: A Capacity Decomposition Approach by Birkhoff and von Neumann." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/08815334331093349207.

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碩士<br>國立清華大學<br>電機工程學系<br>87<br>Based on a decomposition result by Birkhoff and von Neumann for a doubly substochastic matrix, in this paper we propose a scheduling algorithm that is capable of providing service guarantees for input-buffered crossbar switches. Our service guarantees are uniformly good for all non-uniform traffic, and thus imply 100% throughput. The off-line computational complexity to identify the scheduling algorithm is O(N^4.5) for an N×N switch. Once the algorithm is identified, its on-line computational complexity is O(log N) and its on-line memory complexity is O(N^3log

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