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Relevant bibliographies by topics / Instruction set architecture

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Academic literature on the topic 'Instruction set architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 February 2022

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Journal articles on the topic "Instruction set architecture"

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Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

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Stallings, W. "Reduced instruction set computer architecture." Proceedings of the IEEE 76, no. 1 (1988): 38–55. http://dx.doi.org/10.1109/5.3287.

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Wang, L., and C. L. Wu. "Distributed instruction set computer architecture." IEEE Transactions on Computers 40, no. 8 (1991): 915–34. http://dx.doi.org/10.1109/12.83637.

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Zmily, Ahmad, and Christos Kozyrakis. "Block-aware instruction set architecture." ACM Transactions on Architecture and Code Optimization 3, no. 3 (September 2006): 327–57. http://dx.doi.org/10.1145/1162690.1162694.

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Milovanović, E. "The DLX instruction set architecture handbook." Microelectronics Journal 28, no. 5 (June 1997): 600–601. http://dx.doi.org/10.1016/s0026-2692(97)80956-1.

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Diefendorff, K., and E. Silha. "The PowerPC user instruction set architecture." IEEE Micro 14, no. 5 (October 1994): 30. http://dx.doi.org/10.1109/mm.1994.363069.

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Gloria, Alessandro De. "VISA: A variable instruction set architecture." ACM SIGARCH Computer Architecture News 18, no. 2 (May 1990): 76–84. http://dx.doi.org/10.1145/88237.88245.

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Kim, Dae-Hwan. "Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture." European Journal of Electrical Engineering and Computer Science 5, no. 2 (March 22, 2021): 13–17. http://dx.doi.org/10.24018/ejece.2021.5.2.308.

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Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.

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Kim, Dae-Hwan. "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture." Journal of the Korea Society of Computer and Information 18, no. 7 (July 31, 2013): 1–10. http://dx.doi.org/10.9708/jksci.2013.18.7.001.

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Wang, Jiawei, Ming Fu, Lei Qiao, and Xinyu Feng. "Formalizing SPARCv8 instruction set architecture in Coq." Science of Computer Programming 187 (February 2020): 102371. http://dx.doi.org/10.1016/j.scico.2019.102371.

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Dissertations / Theses on the topic "Instruction set architecture"

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Zmily, Ahmad Darweesh. "Block-aware instruction set architecture /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Schoepke, Olaf S. "Dense instruction set computer architecture." Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.332540.

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Glökler, Tilman Meyr Heinrich. "Design of energy-efficient application-specific instruction set processors /." Boston, Mass. [u.a.] : Kluwer Acad. Publ, 2004. http://www.loc.gov/catdir/enhancements/fy0820/2004041376-d.html.

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Wagstaff, Harry. "From high level architecture descriptions to fast instruction set simulators." Thesis, University of Edinburgh, 2015. http://hdl.handle.net/1842/14162.

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As computer systems become increasingly complex and diverse, so too do the architectures they implement. This leads to an increase in complexity in the tools used to design new hardware and software. One particularly important tool in hardware and software design is the Instruction Set Simulator, which is used to prototype new architectures and hardware features, verify hardware, and test and debug software. Many Architecture Description Languages exist which facilitate the description of new architectural or hardware features, and generate a tools such as simulators. However, these typically suffer from poor performance, are difficult to test effectively, and may be limited in functionality. This thesis considers three objectives when developing Instruction Set Simulators: performance, correctness, and completeness, and presents techniques which contribute to each of these. Performance is obtained by combining Dynamic Binary Translation techniques with a novel analysis of high level architecture descriptions. This makes use of partial evaluation techniques in order to both improve the translation system, and to improve the quality of the translated code, leading a performance improvement of over 2.5x compared to a naïve implementation. This thesis also presents techniques which contribute to the correctness objective. Each possible behaviour of each described instruction is used to guide the generation of a test case. Constraint satisfaction techniques are used to determine the necessary instruction encoding and context for each behaviour to be produced. It is shown that this is a significant improvement over benchmark-driven testing, and this technique has led to the discovery of several bugs and inconsistencies in multiple state of the art instruction set simulators. Finally, several challenges in ‘Full System’ simulation are addressed, contributing to both the performance and completeness objectives. Full System simulation generally carries significant performance costs compared with other simulation strategies. Crucially, instructions which access memory require virtual to physical address translation and can now cause exceptions. Both of these processes must be correctly and efficiently handled by the simulator. This thesis presents novel techniques to address this issue which provide up to a 1.65x speedup over a state of the art solution.

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Bennett, Richard Vincent. "Increasing the efficacy of automated instruction set extension." Thesis, University of Edinburgh, 2011. http://hdl.handle.net/1842/5789.

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The use of Instruction Set Extension (ISE) in customising embedded processors for a specific application has been studied extensively in recent years. The addition of a set of complex arithmetic instructions to a baseline core has proven to be a cost-effective means of meeting design performance requirements. This thesis proposes and evaluates a reconfigurable ISE implementation called “Configurable Flow Accelerators” (CFAs), a number of refinements to an existing Automated ISE (AISE) algorithm called “ISEGEN”, and the effects of source form on AISE. The CFA is demonstrated repeatedly to be a cost-effective design for ISE implementation. A temporal partitioning algorithm called “staggering” is proposed and demonstrated on average to reduce the area of CFA implementation by 37% for only an 8% reduction in acceleration. This thesis then turns to concerns within the ISEGEN AISE algorithm. A methodology for finding a good static heuristic weighting vector for ISEGEN is proposed and demonstrated. Up to 100% of merit is shown to be lost or gained through the choice of vector. ISEGEN early-termination is introduced and shown to improve the runtime of the algorithm by up to 7.26x, and 5.82x on average. An extension to the ISEGEN heuristic to account for pipelining is proposed and evaluated, increasing acceleration by up to an additional 1.5x. An energyaware heuristic is added to ISEGEN, which reduces the energy used by a CFA implementation of a set of ISEs by an average of 1.6x, up to 3.6x. This result directly contradicts the frequently espoused notion that “bigger is better” in ISE. The last stretch of work in this thesis is concerned with source-level transformation: the effect of changing the representation of the application on the quality of the combined hardwaresoftware solution. A methodology for combined exploration of source transformation and ISE is presented, and demonstrated to improve the acceleration of the result by an average of 35% versus ISE alone. Floating point is demonstrated to perform worse than fixed point, for all design concerns and applications studied here, regardless of ISEs employed.

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Ponnala, Kalyan. "DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/58.

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The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate. Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing on increasingly wide DATA LARs (Line Associative Registers) as a way to both improve data access speed and increase efficiency of SWAR processing. Although the base concept of DATA LARs predates this thesis, this thesis presents the first instruction set architecture specification complete enough to allow construction of a detailed prototype hardware design. This design was implemented and tested using a hardware simulator.

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Curtis, Bryce Allen. "A special instruction set multiple chip computer for DSP : architecture and compiler design." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15736.

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Mapes, Glenn. "An instruction set simulator for the 8086 16-bit microprocessor." Virtual Press, 1985. http://liblink.bsu.edu/uhtbin/catkey/416976.

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The intent of this thesis is to show the usefulness simulating of an instruction set in software and to demonstrate the feasibility of doing so by providing the framework of a simulation program.The design of new computer architectures and computer based control systems is a trial and error process. Normal design practice is to design and build a prototype of the new system and then evaluate the performance of the prototype. Designing complex systems in this manner is very time consuming and expensive; using a software program to simulate the operation of the new system can help solve certain design problems and shorten the development time and effort.The instruction set simulator executes a subset of the 8086 instruction set and contains routines that are useful in debugging the target software.The feasibility of implementing an instruction set simulator to solve certain design problems has been demonstrated by implementing the most commonly used op codes from the 8086 instruction set.Ball State UniversityMuncie, IN 47306

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Degenbaev, Ulan [Verfasser], and Wolfgang J. [Akademischer Betreuer] Paul. "Formal specification of the x86 instruction set architecture / Ulan Degenbaev. Betreuer: Wolfgang J. Paul." Saarbrücken : Saarländische Universitäts- und Landesbibliothek, 2012. http://d-nb.info/105227885X/34.

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Bauer, Heiner. "Dynamic instruction set extension of microprocessors with embedded FPGAs." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-222858.

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Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, however, with the significant advantage of post-fabrication flexibility. Not only does this offer similar gains in performance but also the flexibility to configure each device individually. This thesis explored the benefit of a tight coupled and fine-grained reconfigurable microprocessor. In contrast to previous research, a detailed design space exploration of logical architectures for island-style field programmable gate arrays (FPGAs) has been performed in the context of a commercial 22nm process technology. Other research projects either reused general purpose architectures or spent little effort to design and characterize custom fabrics, which are critical to system performance and the practicality of frequently proposed high-level software techniques. Here, detailed circuit implementations and a custom area model were used to estimate the performance of over 200 different logical FPGA architectures with single-driver routing. Results of this exploration revealed similar tradeoffs and trends described by previous studies. The number of lookup table (LUT) inputs and the structure of the global routing network were shown to have a major impact on the area delay product. However, results suggested a much larger region of efficient architectures than before. Finally, an architecture with 5-LUTs and 8 logic elements per cluster was selected. Modifications to the microprocessor, whichwas based on an industry proven instruction set architecture, and its software toolchain provided access to this embedded reconfigurable fabric via custom instructions. The baseline microprocessor was characterized with estimates from signoff data for a 28nm hardware implementation. A modified academic FPGA tool flow was used to transform Verilog implementations of custom instructions into a post-routing netlist with timing annotations. Simulation-based verification of the system was performed with a cycle-accurate processor model and diverse application benchmarks, ranging from signal processing, over encryption to computation of elementary functions. For these benchmarks, a significant increase in performance with speedups from 3 to 15 relative to the baseline microprocessor was achieved with the extended instruction set. Except for one case, application speedup clearly outweighed the area overhead for the extended system, even though the modeled fabric architecturewas primitive and contained no explicit arithmetic enhancements. Insights into fundamental tradeoffs of island-style FPGA architectures, the developed exploration flow, and a concrete cost model are relevant for the development of more advanced architectures. Hence, this work is a successful proof of concept and has laid the basis for further investigations into architectural extensions and physical implementations. Potential for further optimizationwas identified on multiple levels and numerous directions for future research were described
Zunehmend komplexere Anwendungen und Besonderheiten moderner Halbleitertechnologien haben zu einer großen Nachfrage an leistungsfähigen und gleichzeitig sehr energieeffizienten Mikroprozessoren geführt. Konventionelle Architekturen versuchen den Befehlsdurchsatz durch Parallelisierung zu steigern und stellen anwendungsspezifische Befehlssätze oder Hardwarebeschleuniger zur Steigerung der Energieeffizienz bereit. Rekonfigurierbare Prozessoren ermöglichen ähnliche Performancesteigerungen und besitzen gleichzeitig den enormen Vorteil, dass die Spezialisierung auf eine bestimmte Anwendung nach der Herstellung erfolgen kann. In dieser Diplomarbeit wurde ein rekonfigurierbarer Mikroprozessor mit einem eng gekoppelten FPGA untersucht. Im Gegensatz zu früheren Forschungsansätzen wurde eine umfangreiche Entwurfsraumexploration der FPGA-Architektur im Zusammenhang mit einem kommerziellen 22nm Herstellungsprozess durchgeführt. Bisher verwendeten die meisten Forschungsprojekte entweder kommerzielle Architekturen, die nicht unbedingt auf diesen Anwendungsfall zugeschnitten sind, oder die vorgeschlagenen FGPA-Komponenten wurden nur unzureichend untersucht und charakterisiert. Jedoch ist gerade dieser Baustein ausschlaggebend für die Leistungsfähigkeit des gesamten Systems. Deshalb wurden im Rahmen dieser Arbeit über 200 verschiedene logische FPGA-Architekturen untersucht. Zur Modellierung wurden konkrete Schaltungstopologien und ein auf den Herstellungsprozess zugeschnittenes Modell zur Abschätzung der Layoutfläche verwendet. Generell wurden die gleichen Trends wie bei vorhergehenden und ähnlich umfangreichen Untersuchungen beobachtet. Auch hier wurden die Ergebnisse maßgeblich von der Größe der LUTs (engl. "Lookup Tables") und der Struktur des Routingnetzwerks bestimmt. Gleichzeitig wurde ein viel breiterer Bereich von Architekturen mit nahezu gleicher Effizienz identifiziert. Zur weiteren Evaluation wurde eine FPGA-Architektur mit 5-LUTs und 8 Logikelementen ausgewählt. Die Performance des ausgewählten Mikroprozessors, der auf einer erprobten Befehlssatzarchitektur aufbaut, wurde mit Ergebnissen eines 28nm Testchips abgeschätzt. Eine modifizierte Sammlung von akademischen Softwarewerkzeugen wurde verwendet, um Spezialbefehle auf die modellierte FPGA-Architektur abzubilden und eine Netzliste für die anschließende Simulation und Verifikation zu erzeugen. Für eine Reihe unterschiedlicher Anwendungs-Benchmarks wurde eine relative Leistungssteigerung zwischen 3 und 15 gegenüber dem ursprünglichen Prozessor ermittelt. Obwohl die vorgeschlagene FPGA-Architektur vergleichsweise primitiv ist und keinerlei arithmetische Erweiterungen besitzt, musste dabei, bis auf eine Ausnahme, kein überproportionaler Anstieg der Chipfläche in Kauf genommen werden. Die gewonnen Erkenntnisse zu den Abhängigkeiten zwischen den Architekturparametern, der entwickelte Ablauf für die Exploration und das konkrete Kostenmodell sind essenziell für weitere Verbesserungen der FPGA-Architektur. Die vorliegende Arbeit hat somit erfolgreich den Vorteil der untersuchten Systemarchitektur gezeigt und den Weg für mögliche Erweiterungen und Hardwareimplementierungen geebnet. Zusätzlich wurden eine Reihe von Optimierungen der Architektur und weitere potenziellen Forschungsansätzen aufgezeigt

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Books on the topic "Instruction set architecture"

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Reduced instruction set computer--RISC--architecture. Letchworth, Hertfordshire, England: Research Studies Press, 1987.

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Sailer, Philip M. The DLX instruction set architecture handbook. San Francisco, Calif: Morgan Kaufmann Publishers, 1996.

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Konsek, Marian B. ISPY: An instruction set analysis tool. Urbana, Ill. (1304 W. Springfield, Urbana 61801): Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.

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Reduced instruction set computer architectures for VLSI. Cambridge, Mass: MIT Press, 1985.

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Sites, Richard L. Alpha AXP architecture reference manual. 2nd ed. Boston: Digital Press, 1995.

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James, Goodman. A programmer's view of computer architecture: With examples from the MIPS RISC architecture. Forth Worth, Tex: Saunders College Pub., 1993.

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1962-, Miller Karen, ed. A programmer's view of computer architecture: With Assembly Language examples from the MIPS RISC architecture. Forth Worth, Tex: Saunders College Pub., 1993.

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Joe, Heinrich, ed. MIPS RISC architecture. Englewood Cliffs, N.J: Prentice Hall, 1992.

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Kane, Gerry. MIPS R2000 RISC architecture. Englewood Cliffs, NJ: Prentice Hall, 1987.

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Feldman, James M. Computer architecture: A designer's text based on a generic RISC. New York: McGraw-Hill, 1994.

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Book chapters on the topic "Instruction set architecture"

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Trio, Jean-Michel. "Instruction Set." In 8086–8088 Architecture and Programming, 143–62. London: Macmillan Education UK, 1985. http://dx.doi.org/10.1007/978-1-349-08186-8_6.

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Gilreath, William F., and Phillip A. Laplante. "Instruction Set Completeness." In Computer Architecture: A Minimalist Perspective, 55–71. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0237-1_8.

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Burrell, Mark. "Building An Instruction Set." In Fundamentals of Computer Architecture, 271–81. London: Macmillan Education UK, 2004. http://dx.doi.org/10.1007/978-1-137-11313-9_16.

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Chalk, B. S. "Reduced Instruction Set Computers." In Computer Organisation and Architecture, 156–80. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13871-5_9.

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Chalk, B. S., A. T. Carter, and R. W. Hind. "Reduced instruction set computers." In Computer Organisation and Architecture, 177–87. London: Macmillan Education UK, 2004. http://dx.doi.org/10.1007/978-0-230-00060-5_10.

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Gilreath, William F., and Phillip A. Laplante. "One Instruction Set Computing." In Computer Architecture: A Minimalist Perspective, 1–3. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0237-1_1.

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Brunst, Holger, Andreas Knüpfer, Valentina Salapura, Joseph A. Fisher, Paolo Faraboschi, Cliff Young, and Franco P. Preparata. "Vector Extensions, Instruction-Set Architecture (ISA)." In Encyclopedia of Parallel Computing, 2129–35. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_259.

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Sunter, Steve. "IEEE 1149.4 Architecture and Instruction Set." In Analog and Mixed-Signal Boundary-Scan, 39–60. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4499-6_3.

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Lam, Siew-Kei, Deng Yun, and Thambipillai Srikanthan. "Morphable Structures for Reconfigurable Instruction Set Processors." In Advances in Computer Systems Architecture, 450–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_36.

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Wang, Jiawei, Ming Fu, Lei Qiao, and Xinyu Feng. "Formalizing SPARCv8 Instruction Set Architecture in Coq." In Dependable Software Engineering. Theories, Tools, and Applications, 300–316. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-69483-2_18.

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Conference papers on the topic "Instruction set architecture"

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Jachimie, Nathan, Fernando Martinez-Vallin, and Jafar Saniie. "CReconfigurable finite field instruction set architecture." In the 2007 ACM/SIGDA 15th international symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1216919.1216954.

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Claver, José M., María I. Castillo, and Rafael Mayo. "Improving Instruction Set Architecture learning results." In the 2004 workshop. New York, New York, USA: ACM Press, 2004. http://dx.doi.org/10.1145/1275571.1275590.

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Fu, X., L. Riesebos, M. A. Rol, Jeroen van Straten, J. van Someren, N. Khammassi, I. Ashraf, et al. "eQASM: An Executable Quantum Instruction Set Architecture." In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 2019. http://dx.doi.org/10.1109/hpca.2019.00040.

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Bhatia, Nitin, Meenakshi D'Souza, and Sujit Kumar Chakrabarti. "Formalizing GPU Instruction Set Architecture in Coq." In ISEC'19: 12th Innovations in Software Engineering Conference. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3299771.3299798.

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Kim, A., Seok Joong Hwang, and Seon Wook Kim. "Effective Instruction Fetch Stage Design for 16-Bit Instruction Set Architecture." In 2008 IEEE 8th International Conference on Computer and Information Technology Workshops. CIT Workshops 2008. IEEE, 2008. http://dx.doi.org/10.1109/cit.2008.workshops.107.

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Huang, Ziqiang, Andrew D. Hilton, and Benjamin C. Lee. "Decoupling Loads for Nano-Instruction Set Computers." In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2016. http://dx.doi.org/10.1109/isca.2016.43.

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Liu, Shaoli, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, and Tianshi Chen. "Cambricon: An Instruction Set Architecture for Neural Networks." In 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE, 2016. http://dx.doi.org/10.1109/isca.2016.42.

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Kong, J. H., L. M. Ang, and K. P. Seng. "Minimal Instruction Set AES Processor using Harvard Architecture." In 2010 3rd IEEE International Conference on Computer Science and Information Technology (ICCSIT 2010). IEEE, 2010. http://dx.doi.org/10.1109/iccsit.2010.5564522.

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Wu, I.-Wei, Zhi-Yuan Chen, Jyh-Jiun Shann, and Chung-Ping Chung. "Instruction set extension exploration in multiple-issue architecture." In the conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1403375.1403560.

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Dharshana, K. S., Kannan Balasubramanian, and M. Arun. "Encrypted computation on a one instruction set architecture." In 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE, 2016. http://dx.doi.org/10.1109/iccpct.2016.7530376.

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