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Journal articles on the topic 'Instruction set architecture'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 February 2022

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1

Shen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.

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This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

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2

Stallings, W. "Reduced instruction set computer architecture." Proceedings of the IEEE 76, no. 1 (1988): 38–55. http://dx.doi.org/10.1109/5.3287.

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3

Wang, L., and C. L. Wu. "Distributed instruction set computer architecture." IEEE Transactions on Computers 40, no. 8 (1991): 915–34. http://dx.doi.org/10.1109/12.83637.

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4

Zmily, Ahmad, and Christos Kozyrakis. "Block-aware instruction set architecture." ACM Transactions on Architecture and Code Optimization 3, no. 3 (September 2006): 327–57. http://dx.doi.org/10.1145/1162690.1162694.

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5

Milovanović, E. "The DLX instruction set architecture handbook." Microelectronics Journal 28, no. 5 (June 1997): 600–601. http://dx.doi.org/10.1016/s0026-2692(97)80956-1.

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6

Diefendorff, K., and E. Silha. "The PowerPC user instruction set architecture." IEEE Micro 14, no. 5 (October 1994): 30. http://dx.doi.org/10.1109/mm.1994.363069.

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7

Gloria, Alessandro De. "VISA: A variable instruction set architecture." ACM SIGARCH Computer Architecture News 18, no. 2 (May 1990): 76–84. http://dx.doi.org/10.1145/88237.88245.

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8

Kim, Dae-Hwan. "Addressing Mode and Bit Extensions to the Thumb-2 Instruction Set Architecture." European Journal of Electrical Engineering and Computer Science 5, no. 2 (March 22, 2021): 13–17. http://dx.doi.org/10.24018/ejece.2021.5.2.308.

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Thumb-2 is the most recent instruction set architecture for ARM processors which are one of the most widely used embedded processors. In this paper, two extensions are proposed to improve the performance of the Thumb-2 instruction set architecture, which are addressing mode extensions and sign/zero extensions combined with data processing instructions. To speed up access to an element of an aggregated data, the proposed approach first introduces three new addressing modes for load and store instructions. They are register-plus-immediate offset addressing mode, negative register offset addressing mode, and post-increment register offset addressing mode. Register-plus-immediate offset addressing mode permits two offsets and negative register offset allows offset to be a negative value of a register content. Post-increment register offset mode automatically modifies the offset address after the memory operation. The second is the sign/zero extension combined with a data processing instruction which allows the result of a data processing operation to be sign/zero extended to accelerate a type conversion. Several least frequently used instructions are reduced to provide the encoding space for the new extensions. Experiments show that the proposed approach improves performance by an average of 8.6% when compared to the Thumb-2 instruction set architecture.

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9

Kim, Dae-Hwan. "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture." Journal of the Korea Society of Computer and Information 18, no. 7 (July 31, 2013): 1–10. http://dx.doi.org/10.9708/jksci.2013.18.7.001.

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10

Wang, Jiawei, Ming Fu, Lei Qiao, and Xinyu Feng. "Formalizing SPARCv8 instruction set architecture in Coq." Science of Computer Programming 187 (February 2020): 102371. http://dx.doi.org/10.1016/j.scico.2019.102371.

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11

Goodacre, J., and A. N. Sloss. "Parallelism and the ARM instruction set architecture." Computer 38, no. 7 (July 2005): 42–50. http://dx.doi.org/10.1109/mc.2005.239.

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12

Chen, Yunji, Huiying Lan, Zidong Du, Shaoli Liu, Jinhua Tao, Dong Han, Tao Luo, et al. "An Instruction Set Architecture for Machine Learning." ACM Transactions on Computer Systems 36, no. 3 (August 16, 2019): 1–35. http://dx.doi.org/10.1145/3331469.

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13

Novkovic, Teodora, Zeljko Lukac, Petar Jovanovic, and Ivan Kastelan. "Graphic Library Optimization for MIPS Architecture." Elektronika ir Elektrotechnika 26, no. 2 (April 25, 2020): 69–76. http://dx.doi.org/10.5755/j01.eie.26.2.25871.

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The aim of this paper and research was to analyse the efficiency of the compiler-generated code for the graphics library and to present results obtained by optimization for the MIPS (Million Instructions Per Second) architecture. Libpng is the official Portable Network Graphics reference library for use in applications that read, create, and manipulate PNG (Portable Network Graphics) raster image files. Given the data structure in the PNG files, as well as the capabilities of the MIPS instruction set, it was expected that significant improvements could be made. Graphic library libpng is optimized by using MIPS instruction set extension and tested on MIPS Malta 74K platform. Test results show, that by using MIPS optimization test, execution times are substantially improved. Our libpng optimization have achieved performance increase of 10 %–78 % depending on optimized routine.

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14

Liu, J., F. Chow, T. Kong, and R. Roy. "Variable instruction set architecture and its compiler support." IEEE Transactions on Computers 52, no. 7 (July 2003): 881–95. http://dx.doi.org/10.1109/tc.2003.1214337.

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15

Hollingsworth, W., H. Sachs, and A. J. Smith. "The Clipper processor: instruction set architecture and implementation." Communications of the ACM 32, no. 2 (February 1989): 200–219. http://dx.doi.org/10.1145/63342.63346.

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16

Reshadi, Mehrdad, Nikil Dutt, and Prabhat Mishra. "A retargetable framework for instruction-set architecture simulation." ACM Transactions on Embedded Computing Systems 5, no. 2 (May 2006): 431–52. http://dx.doi.org/10.1145/1151074.1151083.

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17

Kim, Dae-Hwan. "The Compressed Instruction Set Architecture for the OpenRISC Processor." Journal of the Korea Society of Computer and Information 17, no. 10 (October 31, 2012): 11–23. http://dx.doi.org/10.9708/jksci/2012.17.10.011.

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18

徐, 明毅. "Research on Instruction Set Architecture of 40-Bit Processor." Computer Science and Application 09, no. 09 (2019): 1667–82. http://dx.doi.org/10.12677/csa.2019.99186.

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19

Kwon, Young-Jun, Xiarong Ma, and Hyuk Jae Lee. "PARE: instruction set architecture for efficient code size reduction." Electronics Letters 35, no. 24 (1999): 2098. http://dx.doi.org/10.1049/el:19991420.

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20

Fox, Kiefer, Vangen, and Whalen. "Reduced Instruction Set Architecture for a GaAs Microprocessor System." Computer 19, no. 10 (October 1986): 71–81. http://dx.doi.org/10.1109/mc.1986.1663074.

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21

Pitkänen, Teemu, Jarno K. Tanskanen, Risto Mäkinen, and Jarmo Takala. "Parallel Memory Architecture for Application-Specific Instruction-Set Processors." Journal of Signal Processing Systems 57, no. 1 (April 26, 2008): 21–32. http://dx.doi.org/10.1007/s11265-008-0173-y.

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22

DAHLEM, MARC, ANOOP BHAGYANATH, and KLAUS SCHNEIDER. "Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP." Theory and Practice of Logic Programming 18, no. 3-4 (July 2018): 438–51. http://dx.doi.org/10.1017/s1471068418000170.

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AbstractConventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the relatively low number of programmer-visible registers. Therefore, more recent processor architectures expose their datapaths so that the compiler (1) can schedule parallel instructions to different processing units and (2) can make effective use of local storage of the processing units. Among these architectures, the Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture whose processing units are equipped with first-in first-out (FIFO) buffers at their input and output ports.In contrast to register-based machines, the optimal code generation for SCAD is still a matter of research. In particular, SAT and SMT solvers were used to generate optimal resource constrained and optimal time constrained schedules for SCAD, respectively. As Answer Set Programming (ASP) offers better flexibility in handling such scheduling problems, we focus in this paper on using an answer set solver for both resource and time constrained optimal SCAD code generation. As a major benefit of using ASP, we are able to generatealloptimal schedules for a given program which allows one to study their properties. Furthermore, the experimental results of this paper demonstrate that the answer set solver can compete with SAT solvers and outperforms SMT solvers.This paper is under consideration for acceptance in TPLP.

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23

Chua, Kyle Matthew Chan, Janz Aeinstein Fauni Villamayor, Lorenzo Campos Bautista, and Roger Luis Uy. "Implementation of hyyrö’s bit-vector algorithm using advanced vector extensions 2." International Journal of Advances in Intelligent Informatics 5, no. 3 (October 29, 2019): 230. http://dx.doi.org/10.26555/ijain.v5i3.362.

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The Advanced Vector Extensions 2 (AVX2) instruction set architecture was introduced by Intel’s Haswell microarchitecture that features improved processing power, wider vector registers, and a rich instruction set. This study presents an implementation of the Hyyrö’s bit-vector algorithm for pairwise Deoxyribonucleic Acid (DNA) sequence alignment that takes advantage of Single-Instruction-Multiple-Data (SIMD) computing capabilities of AVX2 on modern processors. It investigated the effects of the length of the query and reference sequences to the I/O load time, computation time, and memory consumption. The result reveals that the experiment has achieved an I/O load time of ϴ(n), computation time of ϴ(n*⌈m/64⌉), and memory consumption of ϴ(n). The implementation computed more extended time complexity than the expected ϴ(n) due to instructional and architectural limitations. Nonetheless, it was par with other experiments, in terms of computation time complexity and memory consumption.

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24

Murray, Alastair C., Richard V. Bennett, Björn Franke, and Nigel Topham. "Code transformation and instruction set extension." ACM Transactions on Embedded Computing Systems 8, no. 4 (July 2009): 1–31. http://dx.doi.org/10.1145/1550987.1550989.

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25

Christou, George, Giorgos Vasiliadis, Vassilis Papaefstathiou, Antonis Papadogiannakis, and Sotiris Ioannidis. "On Architectural Support for Instruction Set Randomization." ACM Transactions on Architecture and Code Optimization 17, no. 4 (December 22, 2020): 1–26. http://dx.doi.org/10.1145/3419841.

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26

MAJZOUB, S., and H. DIAB. "INSTRUCTION-SET EXTENSION FOR CRYPTOGRAPHIC APPLICATIONS ON RECONFIGURABLE PLATFORM." Journal of Circuits, Systems and Computers 16, no. 06 (December 2007): 911–27. http://dx.doi.org/10.1142/s0218126607004076.

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Reconfigurable Systems represent a middle trade-off between speed and flexibility in the processor design world. It provides performance close to the custom-hardware and yet preserves some of the general-purpose processor flexibility. Recently, the area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse-grain hardware. Since the field is still in its developing stage, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents the mapping and performance analysis of two encryption algorithms, namely Rijndael and Twofish, on a coarse grain reconfigurable platform, namely MorphoSys. MorphoSys is a reconfigurable architecture targeted for multimedia applications. Since many cryptographic algorithms involve bitwise operations, bitwise instruction set extension was proposed to enhance the performance. We present the details of the mapping of the bitwise operations involved in the algorithms with thorough analysis. The methodology we used can be utilized in other systems.

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27

Becker, J., and A. Thomas. "Scalable Processor Instruction Set Extension." IEEE Design and Test of Computers 22, no. 2 (February 2005): 136–48. http://dx.doi.org/10.1109/mdt.2005.43.

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28

Balensiefer, Steven, Lucas Kregor-Stickles, and Mark Oskin. "An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures." ACM SIGARCH Computer Architecture News 33, no. 2 (May 2005): 186–96. http://dx.doi.org/10.1145/1080695.1069986.

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29

Shen, Zheng, Hu He, Xu Yang, Di Jia, and Yihe Sun. "Architecture design of a variable length instruction set VLIW DSP." Tsinghua Science and Technology 14, no. 5 (October 2009): 561–69. http://dx.doi.org/10.1016/s1007-0214(09)70118-x.

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30

Rico, Rafael, Juan-Ignacio Pérez, and José Antonio Frutos. "The impact of x86 instruction set architecture on superscalar processing." Journal of Systems Architecture 51, no. 1 (January 2005): 63–77. http://dx.doi.org/10.1016/j.sysarc.2004.07.002.

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31

Jones, Gary, and Elias Stipidis. "Architecture and instruction set design of an ATM network processor." Microprocessors and Microsystems 27, no. 8 (September 2003): 367–79. http://dx.doi.org/10.1016/s0141-9331(03)00064-4.

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32

Nemirovsky, Daniel, Nikola Markovic, Osman Unsal, Mateo Valero, and Adrian Cristal. "Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model." IEEE Micro 35, no. 5 (September 2015): 6–14. http://dx.doi.org/10.1109/mm.2015.109.

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33

Salinas, M. H., B. W. Johnson, and J. H. Aylor. "Implementation-independent model of an instruction set architecture in VHDL." IEEE Design & Test of Computers 10, no. 3 (September 1993): 42–54. http://dx.doi.org/10.1109/54.232471.

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34

M, Kamaraju, and Chinavenkateswararao G. "Low Power Reduced Instruction Set Architecture Using Clock Gating Technique." International Journal of VLSI Design & Communication Systems 4, no. 5 (October 31, 2013): 35–51. http://dx.doi.org/10.5121/vlsic.2013.4503.

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35

Yazdanbakhsh, Amir, Mostafa E. Salehi, and Sied Mehdi Fakhraie. "Customized pipeline and instruction set architecture for embedded processing engines." Journal of Supercomputing 68, no. 2 (February 6, 2014): 948–77. http://dx.doi.org/10.1007/s11227-013-1075-8.

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36

Park, Sungkyung, and Chester Sungchung Park. "Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750132. http://dx.doi.org/10.1142/s0218126617501328.

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Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m W, and 0.06[Formula: see text]m W, respectively, at 10[Formula: see text]MHz in a 0.18[Formula: see text][Formula: see text]m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50[Formula: see text][Formula: see text]W/MHz with 10,800 gates in a 0.18[Formula: see text][Formula: see text]m CMOS process.

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37

BERGSTRA, J. A., and C. A. MIDDELBURG. "On the operating unit size of load/store architectures." Mathematical Structures in Computer Science 20, no. 3 (February 4, 2010): 395–417. http://dx.doi.org/10.1017/s0960129509990314.

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We introduce a strict version of the concept of a load/store instruction set architecture in the setting of Maurer machines. We take the view that transformations on the states of a Maurer machine are achieved by applying threads as considered in thread algebra to the Maurer machine. We study how the transformations on the states of the main memory of a strict load/store instruction set architecture that can be achieved by applying threads depend on the operating unit size, the cardinality of the instruction set and the maximal number of states of the threads.

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38

Lee, Sheayun, Jaejin Lee, Chang Yun Park, and Sang Lyul Min. "Selective code transformation for dual instruction set processors." ACM Transactions on Embedded Computing Systems 6, no. 2 (May 2007): 10. http://dx.doi.org/10.1145/1234675.1234677.

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39

Franke, Björn. "Statistical Performance Modeling in Functional Instruction Set Simulators." ACM Transactions on Embedded Computing Systems 11S, no. 1 (June 2012): 1–22. http://dx.doi.org/10.1145/2180887.2180899.

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40

Nerheim-Wolfe, Rosalee. "Providing a laboratory for instruction set design." ACM SIGCSE Bulletin 24, no. 1 (March 1992): 163–67. http://dx.doi.org/10.1145/135250.134543.

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41

Ivannikov, A. D. "Emulators as a Tool for Control Digital System Software Debugging." INFORMACIONNYE TEHNOLOGII 27, no. 7 (July 8, 2021): 339–49. http://dx.doi.org/10.17587/it.27.339-349.

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The simulation of control digital systems at the architecture level, that is, emulation of the instruction set, memory cells and internal programmable registers, as well as the interrupt system and direct memory access is considered. Emulators are used for debugging embedded digital system software and in the development of new custom processors. Requirements for emulators are formalized. It is shown that the main requirements are adequate simulation of digital systems at the architecture level, the presence of a set of convenient debugging modes, as well as high efficiency of emulators, that is, the minimum possible average number of instrumental computer instructions required to simulate one instruction of the target digital system. A classification of the debugging capabilities of emulators and possible ways of implementing debugging modes is given. The composition of the emulators is described. A graphical model of the structure of the emulator is proposed. The simulation process for each instruction is presented as a sequence of execution of smaller operations. If different instructions include the same operations, these operations can be performed by the same software modules. These modules can be included in all the corresponding blocks of the emulator that simulate the execution of instructions, or the emulator can include only one copy of each operational program module, and the module can be accessed while simulating the corresponding instruction. Determination of the structure of the emulator is formalized as an extreme task, the objective function of which is the minimum average time for simulating the execution of one instruction of the target digital system, and the limitation is the maximum allowable memory size of the instrumental computer occupied by the emulator. A practical method for determining the structure of the emulator is proposed.

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42

Wang, Guang, and Yin Sheng Gao. "An Implementation of Configurable SIMD Core on FPGA." Applied Mechanics and Materials 336-338 (July 2013): 1925–29. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.1925.

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In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.

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43

Braun, G., A. Nohl, A. Hoffmann, O. Schliebusch, R. Leupers, and H. Meyr. "A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 12 (December 2004): 1625–39. http://dx.doi.org/10.1109/tcad.2004.836734.

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44

Kim, Dae-Hwan. "AMEX: Extending Addressing Mode of 16-bit Thumb Instruction Set Architecture." Journal of the Korea Society of Computer and Information 17, no. 11 (November 30, 2012): 1–10. http://dx.doi.org/10.9708/jksci/2012.17.11.001.

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45

Clark, Nathan, Jason Blome, Michael Chu, Scott Mahlke, Stuart Biles, and Krisztian Flautner. "An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors." ACM SIGARCH Computer Architecture News 33, no. 2 (May 2005): 272–83. http://dx.doi.org/10.1145/1080695.1069993.

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46

Lee, Ruby B., and A. Murat Fiskiran. "PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing." Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 40, no. 1 (May 2005): 85–108. http://dx.doi.org/10.1007/s11265-005-4940-8.

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47

Mesman, B., Q. Zhao, N. Busa, and K. Leijten-Nowak. "Reconfigurable Instruction-Set Application-Tuning for DSP." Journal of Circuits, Systems and Computers 12, no. 03 (June 2003): 333–51. http://dx.doi.org/10.1142/s0218126603000787.

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In current System-on-Chip (SoC) design, the main engineering trade-off concerns hardware efficiency and design effort. Hardware efficiency traditionally regards cost versus performance (in high-volume electronics), but recently energy consumption emerged as a dominant criterion, even in products without batteries. "The" most effective way to increase HW efficiency is to exploit application characteristics in the HW. The traditional way of looking at HW design tends to consider it a time-consuming and tedious task, however. Given the current lack of HW designers, and the pressure of time-to-market, clearly a desire exists to fine-balance the merits and effort of tuning your HW to your application. This paper discusses methods and tool support for HW application-tuning at different levels of granularity. Furthermore we treat several ways of applying reconfigurable HW to allow both silicon reuse and the ability to tune the HW to the application after fabrication. Our main focus is on a methodology for application-tuning the architecture of DSP datapaths. Our primary contribution is on reusing and generalizing this methodology to application-tuning DSP instruction sets, and providing tool support for efficient compilation for these instruction sets. Furthermore, we propose an architecure for a reconfigurable instruction-decoder, enabling application-tuning of the instruction-set after fabrication.

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48

DOROJEVETS, MIKHAIL. "ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 521–29. http://dx.doi.org/10.1142/s0129156402001435.

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The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

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49

Qiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.

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In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

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50

Gao, Xiao Peng, and Ping Yang Guo. "PPSim: A Cycle-Accurate Simulator for PowerPC Instruction Set." Applied Mechanics and Materials 325-326 (June 2013): 1766–69. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1766.

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Simulators play an important part in computer architecture research. As for specific microarchitecture study, which focuses on the accurate behavior of out-of-order scheduling, ALU contention, and function unit management, an over-simplified abstraction is not sufficient to represent modern processor organizations. Thus cycle-accurate simulators are introduced to describe the accurate behavior in target microarchitecture. In cycle-accurate simulators, the timing feature within function units is simulated. This paper presents PPSim, a cycle-accurate PowerPC instruction set simulator, which models the cache, branch prediction, and out of order pipeline in PowerPC microarchitecture.

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