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Dissertations / Theses on the topic 'Instructional Design Architecture'

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Published: 4 June 2021
Last updated: 3 February 2022

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1

Butgereit, Laura Lee. "C3TO : a scalable architecture for mobile chat based tutoring." Thesis, Nelson Mandela Metropolitan University, 2010. http://hdl.handle.net/10948/1511.

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C³TO (Chatter Call Centre/Tutoring Online) is a scalable architecture to support mobile online tutoring using chat protocols over cell phones. It is the scalability of this architecture which is the primary focus of this dissertation. Much has been written lamenting the state of mathematics education in South Africa. It is not a pretty story. In order to help solve this mathematical crisis, the “Dr Math” research project was started in January, 2007. “Dr Math” strove to assist school pupils with their mathematics homework by providing access to tutors from a nearby university to help them. The school pupils used MXit on their cell phones and the tutors used normal computer workstations. The original “Dr Math” research project expected no more than twenty to thirty school pupils to participate. Unexpectedly thousands of school pupils started asking “Dr Math” to assist them with their mathematics homework. The original software could not scale. The original software could not cater for the thousands of pupils needing help. The scalability problems which existed in the original “Dr Math” project included: hardware scalability issues, software scalability problems, lack of physical office space for tutors, and tutor time being wasted by trivial questions. C³TO tackled these scalability concerns using an innovative three level approach by implementing a technological feature level, a tactical feature level, and a strategic feature level in the C³TO architecture. The technological level included specific components, utilities, and platforms which promoted scalability. The technological level provided the basic building blocks with which to construct a scalable architecture. The tactical level arranged the basic building blocks of the technological level into a scalable architecture. The tactical level provided short term solutions to scalability concerns by providing easy configurability and decision making. The strategic level attempted to answer the pupils questions before they actually arrived at the tutor thereby reducing the load on the human tutors. C³TO was extensively tested and evaluated. C³TO supported thousands of school pupils with their mathematics homework over a period of ten months. C³TO was used to support a small conference. C³TO was used to encourage people to volunteer their time in participation of Mandela Day. C³TO was used to support “Winter School” during the winter school holiday. In all these cases, C³TO proved itself to be scalable.
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Oda, Caroline W. "The impact of dual-processing metacognitive scaffolding on architectural student writing." Thesis, Capella University, 2015. http://pqdtopen.proquest.com/#viewpdf?dispub=3737247.

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Practicing architects and architectural educators have called for better writing by architecture graduates; however, there appears to be a gap in published empirical studies on instructional designs that address the problem of developing student architects’ writing fluency. Writing well is an especially challenging process for architecture students in design studios because learners must transform the concepts in their visual metaphors, design spaces, and physical models into written language. The study investigated whether architecture students in the treatment group showed greater writing fluency and critical thinking after using sketching as a metacognitive process than did the control group that used words in an identical online lesson. Fifty-six architecture design studio students participated in the quasi-experimental online intervention designed to help students describe their design projects in writing. Student papers following the online sketching intervention were scored using The Cognitive Level and Quality Writing Assessment, Critical Thinking Rubric. Although the one-way ANOVA analysis of mean scores on students’ papers showed no statistical difference between the treatment group, which used sketching, and the control group, which used words, sketching stimulated students in the treatment group to write lengthy posts critiquing each other’s sketches. The finding suggests that online instruction using sketching as a metacognitive scaffolding tool should be further explored as a strategy to engage architecture students in writing practice.

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Helps, C. Richard G. "Evolving Information Technology: A Case Study of the Effects of Constant Change on Information Technology Instructional Design Architecture." BYU ScholarsArchive, 2010. https://scholarsarchive.byu.edu/etd/2388.

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A major challenge for Information Technology (IT) programs is that the rapid pace of evolution of computing technology leads to frequent redesign of IT courses. The problem is exacerbated by several factors. Firstly, the changing technology is the subject matter of the discipline and is also frequently used to support instruction; secondly, this discipline has only been formalized as a four-year university program within recent years and there is a lack of established textbooks and curriculum models; finally, updating courses is seldom rewarded in a higher education system that favors research and teaching for promotion and tenure. Thus, continuously updating their courses place a significant burden on the faculty. A case study approach was used to describe and explain the change processes in updating IT courses. Several faculty members at two institutions were interviewed and course changes were identified and analyzed. The analysis revealed a set of recurrent themes in change processes. An instructional design architecture approach also revealed a set of design domains representing the structure of the change processes. The design domains were analyzed in terms of the design decisions they represented, and also in terms of structures, functions and activities, which are related to Structures-Behaviors-Functions (SBF) analysis. The design domains model helped to explain both negative and positive outcomes that were observed in the data. When design efforts impact multiple domains the design is likely to be more difficult. Understanding the design domain architecture will assist future designers in this discipline.
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Thompson, Jo. "Pueblo Home: An interactive multimedia CD-ROM on Pueblo architecture." CSUSB ScholarWorks, 1995. https://scholarworks.lib.csusb.edu/etd-project/988.

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Llorca, Bofí Josep. "The generative, analytic and instructional capacities of sound in architecture : fundamentals, tools and evaluation of a design methodology." Doctoral thesis, Universitat Politècnica de Catalunya, 2018. http://hdl.handle.net/10803/664194.

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The disciplines of space and time form two domains to which it is daring to compare, since it is obvious that they are of a different nature. Music happens in time, while architecture happens in space. However, from the first treatises on both architecture and music, repeated calls for comparison, complementarity and influence of both disciplines can be read, at least to the observation of certain common orders between the two domains. In this doctoral thesis we do not question this whole theoretical corpus that has been enriching the relationship between both disciplines. We received it and joined that stream of knowledge. What we do notice, however, is the almost impertinent question that follows: can sound help the architect in his daily tasks? And, therefore, what are the contributions of sound to the architect? To do this we must seek the connection in the principles of both arts, where we can detach ourselves from time and space, and approach the most universal of art forms. The architect, in his daily work, is faced with three particular tasks: the architectural project, the architectural analysis and the teaching of architecture. Each of the three tasks is connected with the other two tasks: the project is carried out again with the analysis and transmitted to the new architect; the analysis supports the project decisions and gives tools to the disciple; and the teaching has the project as its purpose and the analysis as its method. The thesis presented here shows what sound offers to the task of the project, to that of analysis and to that of teaching. These three tasks are approached from three premises: theoretical foundations, tools and evaluation. The interaction of the three tasks with the three premises gives rise to nine lines of work that articulate the chapters of the thesis. The first, fourth and seventh chapters approach the three tasks from the premise of theoretical foundations, foundations that perhaps because they are obvious, have been ignored or overlooked but which constitute the nature of both disciplines. The first shows, by the hand of two 20th century authors - the architect Dom Hans van der Laan and the composer Olivier Messiaen - that creation in both disciplines is of a systematic nature. The fourth one revaluates the analytical systems of representation of form both in architecture and in music which, starting with the basic characteristics of its elements, lead to a symbolic notation and a tool for the analysis of the work: the plan and the score. The seventh introduces the student of architecture to the growing separation between music and architecture that has been accentuated to this day. The second, fifth and eighth chapters approach the three particular tasks from the premise of tools, working tools that help to understand more directly the influence of architecture on sound. The second places virtual reality and auralization techniques at the service of the architectural and urban planning project, enhancing the sound experience in these projects. The fifth deals with the acoustic analysis of exterior spaces and their relationship with the urban configuration of these spaces. The eighth section presents the study of acoustic heritage as an educational tool. The third, sixth and ninth chapters deal with the three tasks from the premise of evaluation, a check that ensures the influence of sound on them through teaching experiments. The third argues and exemplifies that a sound landscape can be the engine and generator of an architectural design. The sixth one reviews the methods for evaluating the subjective and objective parameters of architectural acoustics. The ninth shows that in teaching sound to architects, "learning by listening" should be given priority over "passive learning".
Las disciplinas del espacio y del tiempo forman dos dominios a los que resulta atrevido comparar, pues es obvio que son de naturaleza distinta. La música ocurre en el tiempo, mientras que la arquitectura en el espacio. No obstante, desde los primeros tratados tanto de arquitectura como de música, se pueden leer repetidas llamadas a la comparación, al complemento y a la influencia de ambas disciplinas, cuanto menos a la constatación de ciertos órdenes comunes entre ambos dominios. En esta tesis doctoral no ponemos en cuestión todo este corpus teórico que ha venido enriqueciendo la relación entre ambas disciplinas. La recibimos y nos unimos a esa corriente de conocimiento. En lo que sí reparamos, en cambio, es en la pregunta casi impertinente que surge seguidamente: ¿puede el sonido ayudar al arquitecto en sus tareas diarias? Y, por tanto, ¿cuáles son las contribuciones del sonido para el arquitecto? Para ello debemos buscar la conexión en los principios de ambas artes, allí donde podemos despegarnos del tiempo y del espacio, y acercarnos a la más universal de las formas de arte. El arquitecto, en su tarea diaria, se enfrenta a tres tareas particulares: el proyecto arquitectónico, el análisis arquitectónico y la enseñanza de la arquitectura. Cada una de las tres tareas está conectada con las otras dos: el proyecto se reconduce con el análisis y se transmite al nuevo arquitecto; el análisis soporta las decisiones de proyecto y da herramientas al discípulo; y la enseñanza tiene como fin el proyecto y como método el análisis. La tesis aquí presentada pone de manifiesto lo que el sonido ofrece a la tarea del proyecto, a la del análisis y a la de la enseñanza. Estas tres tareas son abordadas desde tres premisas: los fundamentos teóricos, las herramientas y la evaluación. La interacción de las tres tareas con las tres premisas da lugar a nueve líneas de trabajo que articulan los capítulos de la tesis. Los capítulos primero, cuarto y séptimo abordan las tres tareas desde la premisa de los fundamentos teóricos, fundamentos que quizá por ser obvios, se han obviado o pasado por alto pero que constituyen la naturaleza de ambas disciplinas. El primero muestra, de la mano de dos autores del siglo XX ?el arquitecto Dom Hans van der Laan y el compositor Olivier Messiaen- que la creación en ambas disciplinas es de naturaleza sistemática. El cuarto revaloriza los sistemas analíticos de representación de la forma tanto en arquitectura como en música que, empezando por las características básicas de sus elementos, conducen a una notación simbólica y una herramienta de análisis de la obra: el plano y la partitura. El séptimo presenta al estudiante de arquitectura la creciente separación entre la música y la arquitectura que se ha venido acentuando hasta nuestros días. Los capítulos segundo, quinto y octavo abordan las tres tareas particulares desde la premisa de las herramientas, útiles de trabajo que ayudan a comprender de modo más directo la influencia de la arquitectura en el sonido. El segundo sitúa la realidad virtual y las técnicas de auralización al servicio del proyecto de arquitectura y urbanismo, potenciando la experiencia sonora en estos proyectos. El quinto aborda el análisis acústico de espacios exteriores y su relación con la configuración urbana de estos espacios. El octavo presenta el estudio del patrimonio acústico como herramienta pedagógica. Los capítulos tercero, sexto y noveno abordan las tres tareas desde la premisa de la evaluación, comprobación que asegura mediante experimentos docentes la influencia del sonido en ellas. El tercero argumenta y ejemplifica que un paisaje sonoro puede ser el motor y generador de un diseño arquitectónico. El sexto realiza una revisión de los métodos de evaluación de los parámetros subjetivos y objetivos de la acústica arquitectónica. El noveno muestra que en la enseñanza del sonido para los arquitectos debe priorizarse "aprender escuchando" antes que el "aprendizaje pasivo".
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Santos, Marcelo Correia dos [UNESP]. "Televisão digital e Educação a distância: modelo de ambiente virtual de aprendizagem para mídia audiovisual." Universidade Estadual Paulista (UNESP), 2011. http://hdl.handle.net/11449/89530.

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Made available in DSpace on 2014-06-11T19:24:05Z (GMT). No. of bitstreams: 0 Previous issue date: 2011-12-19Bitstream added on 2014-06-13T19:26:41Z : No. of bitstreams: 1 santos_mc_me_bauru.pdf: 3239205 bytes, checksum: 1955bfda018fbb0798bb705d54a6a319 (MD5)
Universidade Estadual Paulista (UNESP)
A televisão, como indústria audiovisual, passa nesta era de convergência digital por um processo de hibridização através das novas tecnologias da informação e comunicação. Essa convergência de dispositivos e linguagens transmidiáticos vem agregar a este meio de comunicação o recurso da interatividade, constituindo uma interface de mediação entre o meio e a audiência interagente. O processo criativo de concepção e desenvolvimento de um modelo de aplicação interativa para Televisão Digital sobre a plataforma do middleware Ginga, do SBTVD, caracteriza-se como um projeto de investigação centrado na inovação tecnológica educacional em mídia audiovisual e na consequente transformação social, produzindo um modelo de Ambiente Virtual de Aprendizagem para Educação a Distância inserido no contexto de convergência de linguagens e mídias da contemporaneidade. Empregando na pesquisa um quadro teórico-metodológico interdisciplinar, tem como objetivo gerar um modelo conceitual de aplicação interativa destinado a servir de plataforma para a criação de conteúdos instrucionais focados em EaD através da mídia TV Digital
Television, as an audiovisual industry, is passing, in this era of digital convergence, by a hybridization process due to new information and communication technologies. This convergence of transmedia devices and languages has come to add to this medium the property of interactive communication, providing an interface through mediation between the audience and the mass media. The creative process of designing and developing a model for interactive Digital Television appliction, on the platform of middleware Ginga and SBTVD, has been characterized as a research project focused on educational innovation in the audiovisual media and the consequent social transformation, producing a model of the Virtual Learning Environment for Distance Education within the context of convergence of languages and media in these contemporary times. Employing in this research an interdisciplinary theoretical and methodological framework, the project aims to generate a conceptual model of interactive application designed to serve as a platform for creating instructional content focused on distance education through the medium knowed as Digital TV
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Santos, Marcelo Correia dos. "Televisão digital e Educação a distância : modelo de ambiente virtual de aprendizagem para mídia audiovisual /." Bauru : [s.n.], 2011. http://hdl.handle.net/11449/89530.

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Orientador: Vânia Cristina Pires Nogueira Valente
Banca: Humberto Ferasoli Filho
Banca: Dariel de Carvalho
Resumo: A televisão, como indústria audiovisual, passa nesta era de convergência digital por um processo de hibridização através das novas tecnologias da informação e comunicação. Essa convergência de dispositivos e linguagens transmidiáticos vem agregar a este meio de comunicação o recurso da interatividade, constituindo uma interface de mediação entre o meio e a audiência interagente. O processo criativo de concepção e desenvolvimento de um modelo de aplicação interativa para Televisão Digital sobre a plataforma do middleware Ginga, do SBTVD, caracteriza-se como um projeto de investigação centrado na inovação tecnológica educacional em mídia audiovisual e na consequente transformação social, produzindo um modelo de Ambiente Virtual de Aprendizagem para Educação a Distância inserido no contexto de convergência de linguagens e mídias da contemporaneidade. Empregando na pesquisa um quadro teórico-metodológico interdisciplinar, tem como objetivo gerar um modelo conceitual de aplicação interativa destinado a servir de plataforma para a criação de conteúdos instrucionais focados em EaD através da mídia TV Digital
Abstract: Television, as an audiovisual industry, is passing, in this era of digital convergence, by a hybridization process due to new information and communication technologies. This convergence of transmedia devices and languages has come to add to this medium the property of interactive communication, providing an interface through mediation between the audience and the mass media. The creative process of designing and developing a model for interactive Digital Television appliction, on the platform of middleware Ginga and SBTVD, has been characterized as a research project focused on educational innovation in the audiovisual media and the consequent social transformation, producing a model of the Virtual Learning Environment for Distance Education within the context of convergence of languages and media in these contemporary times. Employing in this research an interdisciplinary theoretical and methodological framework, the project aims to generate a conceptual model of interactive application designed to serve as a platform for creating instructional content focused on distance education through the medium knowed as Digital TV
Mestre
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Wang, Liang. "Instruction scheduling for a family of multiple instruction issue architectures." Thesis, University of Hertfordshire, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.358493.

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Echols, Stuart Patton. "Teaching design : a qualitative study of design studio instruction /." Thesis, This resource online, 1994. http://scholar.lib.vt.edu/theses/available/etd-12042009-020304/.

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Glökler, Tilman Meyr Heinrich. "Design of energy-efficient application-specific instruction set processors /." Boston, Mass. [u.a.] : Kluwer Acad. Publ, 2004. http://www.loc.gov/catdir/enhancements/fy0820/2004041376-d.html.

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Bennett, J. P. "A methodology for automated design of computer instruction sets." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.232796.

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Ponnala, Kalyan. "DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/58.

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The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate. Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing on increasingly wide DATA LARs (Line Associative Registers) as a way to both improve data access speed and increase efficiency of SWAR processing. Although the base concept of DATA LARs predates this thesis, this thesis presents the first instruction set architecture specification complete enough to allow construction of a detailed prototype hardware design. This design was implemented and tested using a hardware simulator.
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Taha, Tarek M. "A parallelism, instruction throughput, and cycle time model of computer architectures." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/13279.

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Trainis, Simon Andrew. "Architectural trade-offs in the design of a multiple instruction issue processor." Thesis, University of Hertfordshire, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241551.

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Santos, Givaldo Almeida dos. "Ambientes virtuais de aprendizagem : análise das arquiteturas pedagógicas do curso de Bacharelado em Administração Pública do Cesad/UFS." Universidade Federal de Sergipe, 2012. https://ri.ufs.br/handle/riufs/4742.

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The increasing use of educational softwares in the process of teaching and learning between geographically dispersed citizens in the contemporary society is an emergent concern in the studies of researchers of the area of Education in the field of Distance Education (EaD). Education Online uses the Information and Communication Technologies (ICT) to operate its processes in order to provide learning through collaborative practices in distance learning courses that want to use a pedagogical architecture in accordance with the teaching digital network technologies and teaching resources in digital format. Thus, this research contributes to the development and/or customization of educational softwares that must consider human factors as a central element. In particular, the Virtual Learning Environments (VLE) used in EaD, because of the difficulties encountered by users in the use of the interfaces educational digital environments. So, the methodology adopted in this research paper is a case study in a qualitative and quantitative standpoint, which has the main objective to suggest recommendations for projects of interfaces centered on the learner to the concepts of Usability Engineering, Human-Computer Interface and Constructivist Pedagogy. The Analyses on the pedagogical architecture of VLE/CESAD/UFS, from the interactions of four groups of students in distance learning course in Bachelor of Public Administration of the Centre of Distance Education of the Federal University of Sergipe in the period 2011.1, showed the results that confirm the learning style of the students as a more human factor to guide the designs of VLE centered in the apprentice. But also to provide synergy between collective intelligence, digital network technologies and learning through collaborative practices. The results also show that it is possible to lead the interface and instructional design of the virtual environment in tune with the style of the students learning to improve the technical and pedagogical usability of digital and educational interfaces. Usability
A crescente utilização de softwares educacionais no processo de ensino e de aprendizagem entre sujeitos geograficamente dispersos na sociedade contemporânea é uma preocupação emergente nos estudos de pesquisadores da área de Educação a Distância (EaD). A Educação Online utiliza as Tecnologias de Informação e Comunicação (TIC) para operacionalizar seus processos, a fim de proporcionar uma aprendizagem através de práticas colaborativas em cursos à distância que pretendem utilizar uma arquitetura pedagógica em conformidade com as tecnologias digitais em rede e recursos didáticos em formato digital. Sendo assim, este trabalho de pesquisa vem contribuir com o desenvolvimento e/ou customização de softwares educacionais que devem considerar os fatores humanos como elemento central através de uma arquitetura pedagógica que prioriza o estilo de aprendizagem dos alunos. Em especial, os Ambientes Virtuais de Aprendizagem (AVA) utilizados na EaD, tendo em vista as dificuldades encontradas por seus usuários na utilização das interfaces educacionais destes ambientes digitais. Neste sentido, a metodologia adotada neste trabalho de pesquisa é o estudo de caso em uma perspectiva quantitativa e qualitativa, com o objetivo principal de sugerir recomendações para projetos de interfaces centradas no aprendiz à luz dos conceitos de Engenharia de Usabilidade, Interface Humano-Computador e Pedagogia Construtivista. As análises sobre a arquitetura pedagógica do AVA/CESAD/UFS, a partir das interações de quatro grupos de alunos do curso a distância de Bacharelado em Administração Pública do Centro Superior de Educação a Distância da Universidade Federal de Sergipe no período 2011.1, apresentaram resultados que confirmam o estilo de aprendizagem dos alunos como mais um fator humano para nortear os designs de AVA centrados no aprendiz. Como também, para proporcionar a sinergia entre inteligência coletiva, tecnologias digitais em rede e aprendizagem através de práticas colaborativas. Os resultados também demonstram que é possível conduzir os designs de interface e instrucional do ambiente virtual em sintonia com o estilo de aprendizagem dos alunos para aperfeiçoar a usabilidade técnica e pedagógica das interfaces educacionais digitais através da Arquitetura Pedagógica de Estilos de Aprendizagem (APEA).
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Kane, Andrew. "An instruction systolic array architecture for multiple neural network types." Thesis, Loughborough University, 1998. https://dspace.lboro.ac.uk/2134/16031.

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Modern electronic systems, especially sensor and imaging systems, are beginning to incorporate their own neural network subsystems. In order for these neural systems to learn in real-time they must be implemented using VLSI technology, with as much of the learning processes incorporated on-chip as is possible. The majority of current VLSI implementations literally implement a series of neural processing cells, which can be connected together in an arbitrary fashion. Many do not perform the entire neural learning process on-chip, instead relying on other external systems to carry out part of the computation requirements of the algorithm. The work presented here utilises two dimensional instruction systolic arrays in an attempt to define a general neural architecture which is closer to the biological basis of neural networks - it is the synapses themselves, rather than the neurons, that have dedicated processing units. A unified architecture is described which can be programmed at the microcode level in order to facilitate the processing of multiple neural network types. An essential part of neural network processing is the neuron activation function, which can range from a sequential algorithm to a discrete mathematical expression. The architecture presented can easily carry out the sequential functions, and introduces a fast method of mathematical approximation for the more complex functions. This can be evaluated on-chip, thus implementing the entire neural process within a single system. VHDL circuit descriptions for the chip have been generated, and the systolic processing algorithms and associated microcode instruction set for three different neural paradigms have been designed. A software simulator of the architecture has been written, giving results for several common applications in the field.
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Curtis, Bryce Allen. "A special instruction set multiple chip computer for DSP : architecture and compiler design." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15736.

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Moustakas, Evangelos. "Design and simulation of a primitive RISC architecture using VHDL /." Online version of thesis, 1991. http://hdl.handle.net/1850/11229.

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Shee, Seng Lin Computer Science &amp Engineering Faculty of Engineering UNSW. "ADAPT : architectural and design exploration for application specific instruction-set processor technologies." Awarded by:University of New South Wales, 2007. http://handle.unsw.edu.au/1959.4/35404.

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This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.
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Hor, Tze-man, and 賀子文. "The design and programming of a powerful short-wordlength processor using context-dependent machine instructions." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1985. http://hub.hku.hk/bib/B31206906.

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Hor, Tze-man. "The design and programming of a powerful short-wordlength processor using context-dependent machine instructions /." [Hong Kong : University of Hong Kong], 1985. http://sunzi.lib.hku.hk/hkuto/record.jsp?B12320845.

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Akinlofa, Olurotimi Richard. "An investigation into the cognitive effects of instructional interface visualisations." Thesis, Robert Gordon University, 2013. http://hdl.handle.net/10059/925.

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An investigation is conducted into the cognitive effects of using different computer based instructions media in acquisition of specific novel human skills. With recent rapid advances in computing and multimedia instructional delivery, several contemporary research have focussed on the best practices for training and learning delivered via computer based multimedia simulations. More often than not, the aim has been cost minimisation through an optimisation of the instructional delivery process for efficient knowledge acquisition. The outcome of such research effort in general have been largely divergent and inconclusive. The work reported in this thesis utilises a dual prong methodology to provide a novel perspective on the moderating effects of computer based instructional visualisations with a focus on the interaction of interface dynamism with target knowledge domains and trainee cognitive characteristics. The first part of the methodology involves a series of empirical experiments that incrementally measures/compares the cognitive benefits of different levels of instructional interface dynamism for efficient task representation and post-acquisition skilled performance. The first of these experiments utilised a mechanical disassembly task to investigate novel acquisition of procedural motor skills by comparing task comprehension and performance. The other experiments expanded the initial findings to other knowledge domains as well as controlled for potential confounding variables. The integral outcome of these experiments helped to define a novel framework for describing multimodal perception of different computer based instruction types and its moderating effect on post-learning task performance. A parallel computational cognitive modelling effort provided the complementary methodology to investigate cognitive processing associated with different instructional interfaces at a lower level of detail than possible through empirical observations. Novel circumventions of some existing limitations of the selected ACT-R 6.0 cognitive modelling architecture were proposed to achieve the precision required. The ACT-R modifications afforded the representation of human motor movements at an atomic level of detail and with a constant velocity profile as opposed to what is possible with the default manual module. Additional extensions to ACT-R 6.0 also allowed accurate representation of the noise inherent in the recall of spatial locations from declarative memory. The method used for this representation is potentially extendable for application to 3-D spatial representation in ACT-R. These novel propositions are piloted in a proof-of-concept effort followed by application to a more complete, naturally occurring task sequence. The modelling methodology is validated with established human data of skilled task performances. The combination of empirical observations and detailed cognitive modelling afforded novel insights to the hitherto controversial findings on the cognitive benefits of different multimodal instructional presentations. The outcome has implications for training research and development involving computer based simulations.
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Wang, Zhanyu. "The design and implementation of a discussion forum module to function within the architectural constraints of an existing Open Source Software (OSS) learning management system (to meet target-user requirements)." Thesis, Peninsula Technikon, 2004. http://hdl.handle.net/20.500.11838/1381.

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Thesis (MTech (Information Technology))--Peninsula Technikon,Cape Town, 2004
Higher education and online discussions are an integral part of collaboratively based e-Learning systems. However, there problems can be associated with current online discussion models. For example, it can be easy to set open-ended discussions which attract little participation and to assess contributions can be difficult or time-consuming. Students may not achieve the expected learning outcomes without proper structure and management in online discussions. This paper proposes to design and implement a discussion forum object to function within the architectural constraints of an existing Oss learning management system (to meet target user requirements) that is a web-based environment for online discussions where the facilitator can structure each discussion according to its nature and where learning requirements are using already designed templates.
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Sun, Ke. "The design and implementation of an assignment management module to function within the architectural constraints of an existing Open Source Software (OSS) learning management system (to meet target-user requirements)." Thesis, Peninsula Technikon, 2004. http://hdl.handle.net/20.500.11838/1388.

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Thesis (MTech (Information Technology))--Peninsula Technikon, Cape Town, 2004
This document describes the design and implementation of an Assignment Management Module (AMM) to function within the architectural constraints of an eXisting open-source software (OSS) Leaming Management System (LMS). The project is established for Infonmation Technology Department Master Degree Project of the Peninsula Technikon. The Assignment Management Module will be constructed in orders to make it easier to create, mark, and manage assignments and record individual student perfonmances. The design entailed work on different function blocks like a user's authorisation, files uploadfdownload and mailing reminder unit as well as writing and testing of the application code on the intemet/intranet. The development process of the project to explore how to fu lfi11 software engineering methodology in an open-source environment, also presents details of the design architecture and technologies to be used, as well as being mindful of its future directions. The target audience of this document is anyone with an interest in an open-source software project in general, and in a Learning Management System in particular. If the reader has also been a contributor to Learning Management System, and especially to the management of assignments, this document may provide additional value, in that it strives to present a new approach to the understanding of such a module.
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Zhang, Na. "The design and implementation of an assessment management module to function within the architectural constraints of an existing Open Source Software (OSS) learning management system (to meet target-user requirements)." Thesis, Peninsula Technikon, 2004. http://hdl.handle.net/20.500.11838/1371.

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Thesis (MTech (Information Technology))--Peninsula Technikon, 2004
This dissertation was written in fulfillment of the requirements for the degree Master of Technology in the Faculty of Information Technology at the Peninsula Technikon in South Africa. The dissertation covers the introduction of the study; the reviews of the case, Free and Open Source Software; the discussion of methodology of software project management in terms of software engineering; the analysis of assessment methods; the techniques of using PHP, MySQL, Apache and CVS; and the implementation of a test module. The research represents the consideration of the problem, namely that there are few free assessment manager programmes that can be used for the quick and efficient deployment of academic assessments. An experimental research method was used to with the aim of solving the above problem. In other words, a test management system module had to be designed and implemented to function within the architectural constraints of a developing Open Source Software (OSS) Learning Management System (LMS), which is called Knowledge Environment for Web-based Learning Next Generation (KEWL.NextGen). The test management system is a module developed on Object-Oriented Programming (OOP) in PHP and MySQL application. The scripts of this test module are written under the KEWL.NextGen' application framework, which is based on a close approximation of model, view and controller (MVC) design III pattem. Now the entire source coding of the test module has been uploaded to Web site http://kngforge.uwc.ac.za. This test module can be used for the creation and management of an online test. It provides facilities to create a new test, and to preview, edit, delete and mark an existing test. Three question types have been achieved, namely multiple-choice, true/false and short answer.
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Cholmsky, Paul. "Using modular architectures within distributed learning environments, a means for improving the efficiency of instructional design and development processes." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ59243.pdf.

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Li, Weidong, and 李衛東. "A computer-supported participative design jury." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2005. http://hub.hku.hk/bib/B32121556.

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Mapes, Glenn. "An instruction set simulator for the 8086 16-bit microprocessor." Virtual Press, 1985. http://liblink.bsu.edu/uhtbin/catkey/416976.

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The intent of this thesis is to show the usefulness simulating of an instruction set in software and to demonstrate the feasibility of doing so by providing the framework of a simulation program.The design of new computer architectures and computer based control systems is a trial and error process. Normal design practice is to design and build a prototype of the new system and then evaluate the performance of the prototype. Designing complex systems in this manner is very time consuming and expensive; using a software program to simulate the operation of the new system can help solve certain design problems and shorten the development time and effort.The instruction set simulator executes a subset of the 8086 instruction set and contains routines that are useful in debugging the target software.The feasibility of implementing an instruction set simulator to solve certain design problems has been demonstrated by implementing the most commonly used op codes from the 8086 instruction set.Ball State UniversityMuncie, IN 47306
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Varanasi, Archana. "Course grained low power design flow using UPF /." Online version of thesis, 2009. http://hdl.handle.net/1850/11768.

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Yuan, Fangfang. "Assessing the impact of processor design decisions on simulation based verification complexity using formal modeling with experiments at instruction set architecture level." Thesis, University of Bristol, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.566838.

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The Instruction Set Architecture (ISA) describes the key functionalities of a processor design and is the most comprehensible format for enabling humans to understand the structure of the entire processor design. This thesis first introduces the construction of a generic ISA formal model with mathematical notations rather than programming languages, and demonstrates the extensions towards specific ISA designs. The stepwise refinement modeling technique gives rise to the hierarchically structured model, which eases the overall comprehensibility of the ISA and reduces the effort required for modeling similar designs. The ISA models serve as self-consistent, complete, and unambiguous specifications for coding, while helping engineers explore different design options beforehand. In the design phase, a selection of features is available to architects in order for the design to be trimmed towards a particular optimization target, e.g. low power consumption or fast computation, which can be assessed before implementation. However, taking verification into consideration, there is to my knowledge no way to estimate the difficulty of verifying a design before coding it. There needs to be a platform and a metric, from which both functional and non-functional properties can be quantitatively represented and then compared before implementation. Hence, this thesis secondly pro- poses a metric, based on the formally reasoned extension of the generic ISA models, as an estimator of some non-functional property, i.e. the verification complexity for achieving verification goals. The main claim of this thesis is that the verification complexity in simulation-based verification can be accurately retrieved from a hierarchically constructed ISA formal model in which the functionalities are fully specified with the correctness preserved. The modeling structure allows relative comparisons at a reasonably high level of abstraction brought by the hierarchically constructed formalization. The analysis on the experimental ISA emulator assesses the quality of the metric and concludes the applicability of the proposed metric.
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Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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32

Stanić, Milan. "Design of energy-efficient vector units for in-order cores." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/405647.

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In the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all computer systems. Technology feature size scaling leads to higher power density and therefore to complex and costly cooling. While power dissipation is critical for high-performance systems such as data centers due to large power usage, for mobile systems battery life is a primary concern. In the low-end mobile processor market, power, energy and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. The ultimate goal in low-end systems is also to increase performance, but only if area/energy budget is not compromised. Vector architectures have been traditionally applied to the supercomputing domain with many successful incarnations. The energy efficiency and high performance of vector processors, as well as their applicability in other emerging domains, encourage pursuing further research on vector architectures. However adding support for them using conventional design incurs area and power overheads that would not be acceptable for low-end mobile processors and also there is a lack of appropriate tools to perform this research. In this thesis, we propose an integrated vector-scalar design for the low-power ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner. We complement this with an advanced integrated design which features three energy-performance efficient ideas: (1) chaining from the memory hierarchy, (2) direct result forwarding and (3) memory shape instructions. This thesis also presents two tools for measuring and analyzing an application suitability for vector microarchitectures. The first tool is VALib, a library that enables hand-crafted vectorization of applications and its main purpose is to collect data for detailed instruction level characterization and to generate input traces for the second tool. The second tool is SimpleVector, a fast trace-driven simulator that is used to estimate the execution time of a vectorized application on a candidate vector microarchitecture. The thesis also evaluates characteristics of Knights Corner processor with simple in-order SIMD cores. Acquired knowledge is applied in the integrated design.
En los últimos 15 años, la potencia disipada y el consumo de energía se han convertido en elementos cruciales del diseño de la práctica totalidad de sistemas de computación. El escalado del tamaño de los transistores conlleva densidades de potencia más altas y, en consecuencia, sistemas de refrigeración más complejos y costosos. Mientras que la potencia disipada es crítica para sistemas de alto rendimiento, como por ejemplo centros de datos, debido a su uso de gran potencia, para sistemas móviles la duración de la batería es la preocupación principal. Para el mercado de procesadores móviles de prestaciones más modestas, los límites permitidos para la potencia, energía y área del chip son significativamente más bajas que para los servidores, ordenadores de sobremesa, portátiles o móviles de gama alta. El objetivo final en sistemas de gama baja es igualmente el de incrementar el rendimiento, pero sólo si el "presupuesto" para energía o área no se ve comprometido. Tradicionalmente, las arquitecturas vectoriales han sido usadas en el ámbito de la supercomputación, con diversas implementaciones exitosas. La eficiencia energética y el alto rendimiento de los procesadores vectoriales, así como que se puedan aplicar a ámbitos emergentes, motivan a continuar la investigación en arquitecturas vectoriales. No obstante, añadir soporte paravectores basado en diseños convencionales conlleva incrementos de potencia y área que no son aceptables para procesadores móviles de gama baja. Además, no existen herramientas apropiadas para realizar esta investigación. En esta tesis, proponemos un diseño integrado vectorial-escalar para arquitecturas ARM de bajo consumo, que principalmente reutiliza el hardware escalar ya presente en el procesador para implementar el soporte de ejecución de instrucciones vectoriales. El elemento clave del diseño es nuestro modelo de ejecución por bloques propuesto en la tesis, que agrupa instrucciones de cómputo vectorial para ejecutarlas de manera coordinada. Complementamos esto con un diseño integrado avanzado que implementa tres ideas para incrementar el rendimiento eficientemente en cuanto a la energía consumida: (1) encadenamiento (chaining) desde la jerarquía de memoria, (2) reenvío (forwarding) directo de los resultados, y (3) instrucciones de memoria "shape", con patrones de acceso complejos. Además, esta tesis presenta dos herramientas para medir y analizar lo apropiado de usar microarquitecturas vectoriales para una aplicación. La primera herramienta es VALib, una biblioteca que permite la vectorización manual de aplicaciones, cuyo propósito principal es el de recolectar datos para una caracterización detallada a nivel de instrucción, así como el de generar trazas para la segunda herramienta, SimpleVector. SimpleVector es un simulador rápido basado en trazas que estima el tiempo de ejecución de una aplicación vectorial en la microarquitectura vectorial candidata. Finalmente, la tesis también evalúa las características del procesador Knight's Corner, con unidades SIMD en orden sencillas. Lo aprendido en estos análisis se ha aplicado en el diseño integrado.
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Bauer, Heiner. "Dynamic instruction set extension of microprocessors with embedded FPGAs." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-222858.

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Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, however, with the significant advantage of post-fabrication flexibility. Not only does this offer similar gains in performance but also the flexibility to configure each device individually. This thesis explored the benefit of a tight coupled and fine-grained reconfigurable microprocessor. In contrast to previous research, a detailed design space exploration of logical architectures for island-style field programmable gate arrays (FPGAs) has been performed in the context of a commercial 22nm process technology. Other research projects either reused general purpose architectures or spent little effort to design and characterize custom fabrics, which are critical to system performance and the practicality of frequently proposed high-level software techniques. Here, detailed circuit implementations and a custom area model were used to estimate the performance of over 200 different logical FPGA architectures with single-driver routing. Results of this exploration revealed similar tradeoffs and trends described by previous studies. The number of lookup table (LUT) inputs and the structure of the global routing network were shown to have a major impact on the area delay product. However, results suggested a much larger region of efficient architectures than before. Finally, an architecture with 5-LUTs and 8 logic elements per cluster was selected. Modifications to the microprocessor, whichwas based on an industry proven instruction set architecture, and its software toolchain provided access to this embedded reconfigurable fabric via custom instructions. The baseline microprocessor was characterized with estimates from signoff data for a 28nm hardware implementation. A modified academic FPGA tool flow was used to transform Verilog implementations of custom instructions into a post-routing netlist with timing annotations. Simulation-based verification of the system was performed with a cycle-accurate processor model and diverse application benchmarks, ranging from signal processing, over encryption to computation of elementary functions. For these benchmarks, a significant increase in performance with speedups from 3 to 15 relative to the baseline microprocessor was achieved with the extended instruction set. Except for one case, application speedup clearly outweighed the area overhead for the extended system, even though the modeled fabric architecturewas primitive and contained no explicit arithmetic enhancements. Insights into fundamental tradeoffs of island-style FPGA architectures, the developed exploration flow, and a concrete cost model are relevant for the development of more advanced architectures. Hence, this work is a successful proof of concept and has laid the basis for further investigations into architectural extensions and physical implementations. Potential for further optimizationwas identified on multiple levels and numerous directions for future research were described
Zunehmend komplexere Anwendungen und Besonderheiten moderner Halbleitertechnologien haben zu einer großen Nachfrage an leistungsfähigen und gleichzeitig sehr energieeffizienten Mikroprozessoren geführt. Konventionelle Architekturen versuchen den Befehlsdurchsatz durch Parallelisierung zu steigern und stellen anwendungsspezifische Befehlssätze oder Hardwarebeschleuniger zur Steigerung der Energieeffizienz bereit. Rekonfigurierbare Prozessoren ermöglichen ähnliche Performancesteigerungen und besitzen gleichzeitig den enormen Vorteil, dass die Spezialisierung auf eine bestimmte Anwendung nach der Herstellung erfolgen kann. In dieser Diplomarbeit wurde ein rekonfigurierbarer Mikroprozessor mit einem eng gekoppelten FPGA untersucht. Im Gegensatz zu früheren Forschungsansätzen wurde eine umfangreiche Entwurfsraumexploration der FPGA-Architektur im Zusammenhang mit einem kommerziellen 22nm Herstellungsprozess durchgeführt. Bisher verwendeten die meisten Forschungsprojekte entweder kommerzielle Architekturen, die nicht unbedingt auf diesen Anwendungsfall zugeschnitten sind, oder die vorgeschlagenen FGPA-Komponenten wurden nur unzureichend untersucht und charakterisiert. Jedoch ist gerade dieser Baustein ausschlaggebend für die Leistungsfähigkeit des gesamten Systems. Deshalb wurden im Rahmen dieser Arbeit über 200 verschiedene logische FPGA-Architekturen untersucht. Zur Modellierung wurden konkrete Schaltungstopologien und ein auf den Herstellungsprozess zugeschnittenes Modell zur Abschätzung der Layoutfläche verwendet. Generell wurden die gleichen Trends wie bei vorhergehenden und ähnlich umfangreichen Untersuchungen beobachtet. Auch hier wurden die Ergebnisse maßgeblich von der Größe der LUTs (engl. "Lookup Tables") und der Struktur des Routingnetzwerks bestimmt. Gleichzeitig wurde ein viel breiterer Bereich von Architekturen mit nahezu gleicher Effizienz identifiziert. Zur weiteren Evaluation wurde eine FPGA-Architektur mit 5-LUTs und 8 Logikelementen ausgewählt. Die Performance des ausgewählten Mikroprozessors, der auf einer erprobten Befehlssatzarchitektur aufbaut, wurde mit Ergebnissen eines 28nm Testchips abgeschätzt. Eine modifizierte Sammlung von akademischen Softwarewerkzeugen wurde verwendet, um Spezialbefehle auf die modellierte FPGA-Architektur abzubilden und eine Netzliste für die anschließende Simulation und Verifikation zu erzeugen. Für eine Reihe unterschiedlicher Anwendungs-Benchmarks wurde eine relative Leistungssteigerung zwischen 3 und 15 gegenüber dem ursprünglichen Prozessor ermittelt. Obwohl die vorgeschlagene FPGA-Architektur vergleichsweise primitiv ist und keinerlei arithmetische Erweiterungen besitzt, musste dabei, bis auf eine Ausnahme, kein überproportionaler Anstieg der Chipfläche in Kauf genommen werden. Die gewonnen Erkenntnisse zu den Abhängigkeiten zwischen den Architekturparametern, der entwickelte Ablauf für die Exploration und das konkrete Kostenmodell sind essenziell für weitere Verbesserungen der FPGA-Architektur. Die vorliegende Arbeit hat somit erfolgreich den Vorteil der untersuchten Systemarchitektur gezeigt und den Weg für mögliche Erweiterungen und Hardwareimplementierungen geebnet. Zusätzlich wurden eine Reihe von Optimierungen der Architektur und weitere potenziellen Forschungsansätzen aufgezeigt
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34

Chung, Kin-wah, and 鍾健華. "Plover cove dam building." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1994. http://hub.hku.hk/bib/B31981999.

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35

El, Mawas Nour. "Architecture pour la co-conception des jeux sérieux participatifs et intensifs en connaissances." Thesis, Troyes, 2013. http://www.theses.fr/2013TROY0020/document.

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Cette thèse identifie et vise à affronter certains verrous scientifiques concernant la conception des scenarios des serious games, leurs utilisations par un meilleur partage entre les concepteurs dans des contextes d’apprentissage ciblés. Les constats motivant ce travail sont (1) la participation indispensable des formateurs dans la phase de conception en se basant sur leurs expertises et leurs objectifs pédagogiques, (2) la nécessité grandissante pour les formateurs experts de formaliser les scénarios décrivant les situations complexes rarement se produisant, (3) la non-adéquation des systèmes-auteurs des jeux sérieux existants à cette population de concepteurs, permettant seulement un nombre limité de scénarios à cause de leurs couts élevés, (4) le faible niveau de réutilisation des scénarios déjà produits dans la vie quotidienne. Notre problématique consiste à lever certains verrous existants dans la conception des jeux sérieux pour la formation dans des domaines d’expertises complexes avec l’hypothèse qu’une meilleure organisation de la connaissance et de la coopération va faciliter la conception. L’étude de cette problématique s’effectue en proposant l’architecture ARGILE (Architecture for Representations, Games, Interactions, and Learning among Experts) adaptée au jeu sérieux « participatif et intensif en connaissances »
This PhD aims to confront some scientific challenges concerning the scenarios’ conception of Serious Games, their use through a better share by designers within the context of targeted learning. The findings motivating our work are (1) the significant participation of trainers in the design phase, (2) the growing needs for expert trainers to formalize scenarios describing rarely complex situations, (3) the divergence of existing serious games to these designers which cover a limited number of scenarios due to their high cost, (4) the low re-use’ level of scenarios that have already happened in daily life.Our questioning will lead us to see how we must design serious games for training in complex areas of expertise where reference knowledge is neither stabilized nor unanimous, but rather dynamic and continuously evolving. After having examined the principal mains of application of the Serious Game and having defined it, the study of this questioning led us to propose the ARGILE (Architecture for Representations, Games, Interactions, and Learning Among Experts) architecture, suitable for "participatory and knowledge-intensive" serious games
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黃朝龍 and Chiu-lung Dennis Wong. "An audio-visual centre at Stanley Street." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2001. http://hub.hku.hk/bib/B31986110.

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Yip, Wan-hung, and 葉韞紅. "The relative functions of text and drawing in computer-supported collaborative problem-solving." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2000. http://hub.hku.hk/bib/B31225494.

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DIRKS, STEFANIE. "An Appalachian Arts Project: A New Model to Promote Communal Art Interaction." University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1211923981.

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39

Husár, Adam. "Implementace obecného assembleru." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412779.

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This thesis describes the design of the universal assembler that represents a part of the Lissom project. You will be provided with the description of the assembler architectures and their usual tasks. Special attention is paid to GNU assembler. Designed assembler consists of the fixed and the generated part. The generated part is created automatically from the description of instruction set, that is defined using architecture and instructions set description language ISAC. Using this approach, it is possible to change assembler target architecture automatically. The second part of thesis describes the Parserlib2 library implementation that is a part of the Lissom project and provides the information about the target instruction set for an assembler generator.
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Bertrand, François. "Conception descendante appliquée aux microprocesseurs VLSI." Phd thesis, Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316026.

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Dans la méthode de conception sûre et descendante CAPRI applicable aux circuits intégrés VLSI, on analyse les spécifications initiales à la définition de l'architecture du circuit. La méthode proposée est une méthode par affinements successifs de spécifications dans laquelle on distingue: 1) le choix des algorithmes; 2) le choix du chemin de données associé aux blocs fonctionnels; 3) le choix de la structure de la partie contrôle. Application de la démarche descendante au microordinateur 80 C48 d'INTEL en technologie CMOS
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Cheng, Shi-You, and 程士祐. "Low-Power Instruction Cache Architecture Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/51203641355516975879.

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碩士
國立交通大學
電子工程系所
94
Recent remarkable advances of VLSI technology have been increasing processor speed and DRAM capacity. However, the advances also have introduced a large, growing performance gap between processor and main memory. Cache memories have long been employed on processor chips in order to bridge the processor-memory performance gap. In order to improve the performance of the memory system further, the most straightforward approach is to increase the cache size, and then increase the cache-hit rates. However, this approach also increases the power dissipated in cache accesses significantly. Therefore, the low-power cache architectures have become one of the most important issues. In this thesis, we propose a low-power instruction cache architecture by utilizing the four techniques, including memory sub-banking, two-phased cache, pre-tag checking, and signal “seq” for tag-memory access skipping. By these techniques, we can eliminate as many unnecessary tag-memory and data-memory accesses as possible to achieve the goal of low power consumption. Experimental results show that the proposed instruction cache can reduce about 54% power consumption compared to the conventional two-way set associative cache.
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Ye, Yi-Lin, and 葉奕麟. "Design Instruction Analyzer in the Hyper-scalar Architecture." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/e9bc8r.

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碩士
國立中山大學
電機工程學系研究所
104
When the Hyper-scalar microprocessor system architecture performs the same thread, it cause the delay of data transmit and reduce the performance due to the dependence between instructions which result in a frequently data interact between cores in the Virtual Shared Register File (VSRF) transmission. Therefore, we propose Instruction Analyzer to solve the problem of dependence between instructions. When an instruction depends on another instruction, both of the instructions would be issued to the same core as far as possible. In order to improve the whole architecture performance, the number of data interaction between cores will be substantially reduced in the VSRF Before being issued to the appropriate core, instructions must be analyzed according to dependence by Instruction Analyzer. There are four stages in the whole procedure. First, Instruction Fetch: In order to improve the parallelism of instruction level, it will cooperate with Branch Predictor and fetch four instructions at the same time in this stage. Second, Register Tag: Operand tags and conditional tags will be generated according to the dependence between instructions. Register destination tag will be determined according to the most appropriate result of the operand tags and the conditional tags. Third, Dependence Analyzer: Core tags will be generated according to the register tags and decide the core which the instruction will be issued to. Fourth, Dispatch: Cycle tags will be generated according to the core tags and decide when the instruction must be issued. The result of cycle tags will be recorded in the Defer Table. This stage is the most important part of Instruction Analyzer. There must be a PC Detector that judge whether Instruction Analyzer fetch the correct instructions. When the Instruction Analyzer fetches wrong instructions, a compensation mechanism would direct the PC to correct the instruction address. We verify whether this architecture could efficiently issue instructions by testing programs and reduce the number of data interaction between cores in the VSRF. According to the simulation result, the number of data interaction between cores in the VSRF reduces to half after Instruction Analyzer is applied. Therefore, we implement Instruction Analyzer that not only raise the core usage but also reduce the number of data interaction between cores in the VSRF.
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43

Su, Heng-I., and 蘇恆毅. "An Instruction Set Architecture Simulator for Embedded Processor Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/05833976379712231803.

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Abstract:
碩士
國立清華大學
電機工程學系
90
The design evaluation of embedded processors at each level is an important issue, the architecture level especially. The accurate evaluation at the architecture level is the key to improving the system performance, but it is not easy to fix the complete design at the architecture level. The designers need to spend a lot of time in exploring different architectures based on the applications. Without an appropriate simulation tool for performance evaluation, exploring different processor architectures would be painful, if possible. An instruction set architecture simulator is a simulation tool which attempts to simplify this work. In this thesis, we propose an instruction-accurate and cycle-accurate instruction set architecture simulator for embedded processor design. It helps us easily and quickly describing different embedded processors, using a simple architecture description method which we developed. According to the simulation results, it is easy for us choose the highest performance architecture with an acceptable area overhead. A debugging environment also is provided for debugging, which is important for application software development. It allows easy modification of the source code. If there are some special opcodes which our simulator does not support, one can revise the source code with the proposed environment. In our experiment, we simulated and evaluated the performance of some processor architectures. Based on the results, we were able to modify the architectures to improve their performance. The performance improvement varies from 19% to 42% in these cases.
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44

Hu, Ya-Lun, and 胡亞倫. "Design and Evaluation of Advanced RISC Instruction Set Architecture." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/03080070015891954595.

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Abstract:
碩士
國立中正大學
資訊工程所
94
In embedded domain, performance and power consumption are usually the design constraints. And a good instruction set architecture plays a key role in that. A successful embedded processor must be accompanied with an excellent instruction set, such as most popular processor in embedded domain - ARM. In this paper we propose sub-computing instruction, load and store mask instruction, prefetch instruction and repeat instruction to improve performance. And we also propose compression instructions to improve code density. Besides, we develop an instruction level cycle accurate C simulator for evaluating and refining our design. Finally, we compare our design with ARM using MiBench benchmark suite.
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45

Chen, Jhen-Syuan, and 陳振軒. "Design of Adaptive Instruction Codec Architecture for Network-on-Chip." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/j84g4m.

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碩士
國立臺北科技大學
電腦與通訊研究所
102
The multicore system-on-chip (SoC) rapid development in recently. Messages exchanging between Processing Elements (PEs) are quite frequently. When using the traditional bus architecture cannot be requirement of the high performance. The Network-on-Chip (NoC) architecture was proposed to solve problems with multi-core architecture communication but it derived some problems, such as throughput, power consumption, deadlock and area. In this thesis, an Adaptive Instruction Codec Architecture (AICA) is proposed to improve the throughput and reduce the power consumption of network interface in network-on-chip. NoC transmission large amounts of data and instructions in which have high repeatability and similarity. The proposed AICA architecture decrease packet transmission by reducing the redundancy of instruction. The transmission channel can accommodate more encoded packets, so that the router improves bandwidth utilization and throughput. On the other hand, the encoded packet can reduce power consumption by reducing router transmission times, then the power consumption in network interface will be reduced. The experimental results show that the proposed AICA method can improve 23.5% on throughput and reduce 30.3% on power consumption.
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46

Chiu, Tai-En, and 邱泰恩. "An extensible instruction set architecture design and its toolchain implementation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/31263591761985977538.

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Abstract:
碩士
國立成功大學
電腦與通信工程研究所
96
The design methodology of embedded processors can adapt to the design flow of Application-Specific Instruction-Set Processor (ASIP) to perform various types of operations more efficiently. In this thesis, we present a design of extensible instruction set architecture (ISA) for ASIP systems. By removing the less frequently used functionality of the ARMv4 ISA and rearranging its binary encoding, we obtain an extended instruction encoding space. This extended space can be added with special-purpose instructions without any constraint. To use this extensible ISA, we also implement the corresponding software toolchain that includes an assembler, a linker, and some basic libraries. To verify the software toolchain, we modify our RISC32 processor to perform verification. We first use our toolchain to generate an executable binary image, and then execute this image by an HDL simulator which is our RISC32 processor. At last, we compare the simulator’s output results with the referenced ones for correctness checking.
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47

Wang, Albert, and 王伯文. "Improving instruction set design of embedded microcontroller architecture based on Transport-Triggered Architecture and VLIW." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74214506110234397499.

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Abstract:
碩士
國立臺灣科技大學
電子工程系
93
In this paper, we propose a new design concept of instruction set design based on Very Long Instruction Word (VLIW) and Transport Triggered Architecture(TTA). VLIW has advantages on highly parallel ability and easy for hardware implementation. But it also has disadvantages with poorly code density and binary compatible. Differ from traditional architecture, TTA archives operation by data movement. Because the only operation is move, implementations of TTA are more simple than other architecture and ease to extend other specific applications. Bus TTA has the same disadvantages with VLIW. We will analyze and propose improvements for VLIW and TTA on two aspects: For the disadvantages of VLIW, we propose instruction tag to improve flexibilities and binary compatible issues. For TTA, we propose a multiple-source instruction format that between TTA and traditional RISC architecture for code density issue. And we will have a instruction set implementation that combine 2 concepts.
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48

du, ling-yan, and 杜領諺. "Design of instructions scheduling Mechanism in Hyper-Threading Architecture for Improving Performance." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/51612898326456326807.

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Abstract:
碩士
國立中山大學
電機工程學系研究所
92
In the microprocessor system, exploiting ILP is an important key for improving performance. As instructions scheduling mechanism is designed complicated for employing ILP more efficient, the hardware cost will become larger in opposition. In the nowadays processor, they adopt the multiple scheduler queues to issue instructions so that the hardware cost will be not larger. But in this scheduling mechanism, it could successive issue the instructions that have dependence. This situation can makes that the utilization of execution units is not saturated. In the hyperthreading architecture, the instructions in the scheduler queue have high degree of parallelism. If we can decrease the probability of situation that successive issue the instructions that have dependence, the utilization of execution units will heighten. In this paper, we propose the scheduling mechanism called as priority-scheduling buffer to replace the original scheduler queues. The scheduling mechanism will divide an original scheduler queue into multiple virtual scheduler queues according to the dependence of instructions. the instructions that have dependence will dispatch into the same virtual scheduler queue. The instructions can be issued from the ahead of different virtual scheduler queues. This can reduce the probability that successive issues the instructions that have dependence. According to result of simulation in SPEC CINT2000, we adopt the Intel Pentium 4 for basic architecture of our simulation. In the five threads executing simultaneously, the performance will increase 7.14% average that compares with the original scheduler queue.
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49

Nagarajan, Ramadass 1977. "Design and evaluation of a technology-scalable architecture for instruction-level parallelism." Thesis, 2007. http://hdl.handle.net/2152/3534.

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50

"Investigations in CPU design: a triple-instruction computer." Chinese University of Hong Kong, 1994. http://library.cuhk.edu.hk/record=b5887224.

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Abstract:
Wai-Tung Chung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.
Includes bibliographical references (leaves 102-104).
Chapter 1. --- Introduction --- p.1
Chapter 1.1 --- Central Processing Unit innovation
Chapter 1.2 --- Long Instruction Word computer
Chapter 1.3 --- Prior attempts
Chapter 2. --- The new architecture --- p.11
Chapter 2.1 --- The triple-instruction word
Chapter 2.2 --- Functional view of the architecture
Chapter 2.3 --- Inter-functional units synchronization
Chapter 2.4 --- Instruction set design
Chapter 2.5 --- Special features
Chapter 3. --- Simulation of the architecture --- p.39
Chapter 3.1 --- Computer architecture simulation
Chapter 3.2 --- The simulation language used: APL
Chapter 3.3 --- Simulation environment
Chapter 3.4 --- Simulation design
Chapter 3.5 --- The micro-architecture
Chapter 3.6 --- Implementation details
Chapter 4. --- The supporting environment --- p.53
Chapter 4.1 --- The environment
Chapter 4.2 --- The Pseudo-machine configuration
Chapter 4.3 --- Assembly language description
Chapter 4.4 --- Details of the utilities
Chapter 5. --- Evaluation --- p.53
Chapter 5.1 --- Case Study
Chapter 5.2 --- Results and comparison
Chapter 5.3 --- Summary
Chapter 6. --- Discussion and conclusion --- p.96
Chapter 6.1 --- The triple-instruction computer
Chapter 6.2 --- Use of APL for architectural simulation
Chapter 6.3 --- Further considerations
Chapter 7. --- References --- p.81
Chapter 8. --- Appendix I: Program listing for the TIC simulator
Chapter 9. --- Appendix II: Screen dump of the simulation runs
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