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Relevant bibliographies by topics / Integrated circuit chip

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Academic literature on the topic 'Integrated circuit chip'

Author: Grafiati

Published: 4 June 2025

Last updated: 23 June 2025

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Journal articles on the topic "Integrated circuit chip"

1

Yordanov, Hristomir, and Peter Russer. "Integrated on-chip antennas for communication on and between monolithic integrated circuits." International Journal of Microwave and Wireless Technologies 1, no. 4 (2009): 309–14. http://dx.doi.org/10.1017/s1759078709990407.

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The rate of signal transmission on or between monolithic integrated circuits is limited by the cross-talk and the dispersion due to the wired interconnects. The bandwidth limitations can be overcome by wireless chip-to-chip and on-chip interconnects via integrated antennas. In this work the utilization of the electronic circuit ground planes as radiating elements for the integrated antennas has been proposed. This allows for optimal usage of chip area, as the antennas share the same metallization structure as the circuits. By exciting the interconnects between the patch areas in transmission line modes as well as in antenna modes, the interference between signals from circuit to circuit and antenna excitation signals is minimized. This has been achieved by inserting a transformer in the antenna feeding network. Examples of possible antenna and feeding structures have been investigated numerically. Scaled prototypes of the integrated antennas have been manufactured and measured.

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Lee, Edward T., and Eddy T. Lee. "On integrated circuit chip reduction." Kybernetes 29, no. 3 (2000): 381–86. http://dx.doi.org/10.1108/03684920010795286.

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Farah, Wahaj, and Vinay M. "Integrated Circuits - Its Development and Uses." Advancement of Signal Processing and its Applications 4, no. 3 (2022): 1–4. https://doi.org/10.5281/zenodo.6349270.

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<em>An integrated circuit, sometimes known as a monolithic integrated circuit, is a set of electrical circuits on a single compact flat piece (or "chip") of semiconductor material, usually silicon. A compact chip has a large number of tiny MOSFETs (metal–</em><em>oxide</em><em>–</em><em>semiconductor field</em><em>–effect transistors). As a result, circuits created with discrete electrical components are orders of magnitude smaller, quicker, and less expensive. Because of the IC's mass production capability, dependability, and building-block approach to integrated circuit design, standardized ICs have quickly replaced discrete transistor designs. ICs have transformed the world of electronics by being employed in practically every electronic equipment. Computers, cellphones, and other digital home gadgets have become inextricably linked to the structure of modern civilizations, thanks to the small size and low cost of integrated circuits (ICs) like modern computer processors and microcontrollers. </em>

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Hu, Jian-Guo, Wen-Zhuo Mei, Jin Wu, Jia-Wei Li, and De-Ming Wang. "A Fully Integrated RFID Reader SoC." Micromachines 14, no. 9 (2023): 1691. http://dx.doi.org/10.3390/mi14091691.

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The traditional RFID reader module relies on a discrete original design. This design integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a PCB board, leading to bottlenecks in cost, power consumption, stability and reliability. To align with the trend towards high integration, miniaturization and low power consumption in RFID reader, this paper introduces a fully integrated RFID Reader SoC. The SoC employs the open-source Cortex-M0 core to integrate the RF transceiver, analog circuits, baseband protocol processing, memory and interface circuits into one chip. It’s compatible with ISO/IEC 14443 A-type and B-type and ISO/IEC 15693 transmission protocols and rates. Manufactured using a 0.18 μm process, the chip is compatible with multiple standards. The optimized design of the digital baseband control circuit results in a chip area of only 11.95 mm2 offering clear advantages in both area and integration compared to similar work.

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Enomoto, Yoshinori, Hideo Monma, Shunzo Ohta, and Takeshi Sasaki. "4703483 Chip on chip type integrated circuit device." Microelectronics Reliability 28, no. 3 (1988): 498. http://dx.doi.org/10.1016/0026-2714(88)90406-4.

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ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.

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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

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Yordanov, Hristomir, and Peter Russer. "Antennas embedded in CMOS integrated circuits." Facta universitatis - series: Electronics and Energetics 23, no. 2 (2010): 169–77. http://dx.doi.org/10.2298/fuee1002169y.

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In this work we propose novel integrated antennas for chip-to-chip wireless interconnects. In order to save chip area, the available CMOS circuit ground planes can be used as radiating elements. The interference between the integrated antennas and the on-chip circuit interconnects should be minimised. This can be obtained by introducing a transformer in the antenna feeding network.

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VAHEDI, HALEH, STEFANO GREGORI, and RADU MURESAN. "ON-CHIP POWER-EFFICIENT CURRENT FLATTENING CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 03 (2009): 565–79. http://dx.doi.org/10.1142/s0218126609005332.

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This paper presents a control circuit which regulates the current consumption of integrated circuits using current injection and voltage scaling techniques. The control circuit can be integrated with smart cards as a countermeasure against power analysis attacks and electromagnetic emanation analysis attacks. We have designed the proposed circuit in 0.18 μm CMOS technology at 1.8 V power supply. The simulation results show that the circuit controls the current through the power supply pin of a model of a smart card microcontroller and attenuates the peak-to-peak current variations by 95%. The power dissipation overhead of the control circuit is less than 20% of the original power dissipation of the smart card microcontroller. Comparing the layout area of the proposed circuit with that of an ASIC 3-DES algorithm in the same technology shows that the control circuit only constitutes 4% of the cryptographic processor. The proposed circuit proves to be especially useful for smart cards and small portable devices, where power dissipation and chip area are critical.

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Beha, Johannes G., Russell Dreyfus, Jeffrey A. Kash, and Gary W. Rubloff. "4703260 Full chip integrated circuit tester." Microelectronics Reliability 28, no. 3 (1988): 497. http://dx.doi.org/10.1016/0026-2714(88)90404-0.

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Beha, Johannes G., Russell W. Dreyfus, Jeffrey A. Kash, and Gary W. Rubloff. "4845425 Full chip integrated circuit tester." Microelectronics Reliability 30, no. 3 (1990): i. http://dx.doi.org/10.1016/0026-2714(90)90542-u.

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Dissertations / Theses on the topic "Integrated circuit chip"

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Bakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.

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Leung, Lydia Lap Wai. "Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LEUNG.

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Mesgarzadeh, Behzad. "Circuit Techniques for On-Chip Clocking and Synchronization." Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7505.

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Jin, Yalin. "Radio-frequency integrated-circuit design for CMOS single-chip UWB systems." Thesis, [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2724.

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Zhu, Qi. "Helix-type compliant off-chip interconnect for microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17541.

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Osborn, Tyler Nathaniel. "All-copper chip-to-substrate interconnects for high performance integrated circuit devices." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28211.

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Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.

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Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.

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He, Yingchun. "VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36845.

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Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.<br>Master of Science

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Lerch, Terence. "Thermal evaluation of an integrated circuit chip using infrared imaging and finite element techniques /." Online version of thesis, 1991. http://hdl.handle.net/1850/11113.

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Aulagnier, Guillaume. "Optimisation de convertisseurs DC-DC SoC (System on Chip) pour l'automobile." Phd thesis, Toulouse, INPT, 2015. http://oatao.univ-toulouse.fr/19512/1/AULAGNIER_Guillaume.pdf.

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L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.

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Books on the topic "Integrated circuit chip"

1

Kellerman, David. Prevalent single chip packages for integrated circuit packages. Business Communications Co., 1997.

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J, Mergens Markus P. On-chip ESD protection in integrated circuits: Device physics, modeling, circuit simulation. Hartung-Gorre, 2001.

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Pasricha, Sudeep. On-Chip Communication Architectures: System on Chip Interconnect. Elsevier, 2008.

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Wang, Albert Z. H. On-chip ESD protection for integrated circuits: An IC design perspective. Kluwer Academic Publishers, 2002.

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Madisetti, V. A platform-centric approach to system-on-chip (SOC) design. Springer, 2010.

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Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Elsevier/Morgan Kaufmann, 2008.

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Pasricha, Sudeep. On-chip communication architectures: System on chip interconnect. Elsevier / Morgan Kaufmann Publishers, 2008.

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8

Yoo, Hoi-Jun. Low-power NoC for high-performace SoC design. Taylor & Francis, 2008.

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Yoo, Hoi-Jun. Low-Power NoC for High-Performance SoC Design. Taylor and Francis, 2008.

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Fakhfakh, Mourad. Analog/RF and Mixed-Signal Circuit Systematic Design. Springer Berlin Heidelberg, 2013.

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Book chapters on the topic "Integrated circuit chip"

1

Lajolo, M., L. Lavagno, M. Sonza Reorda, and M. Violante. "Early Power Estimation for System-on-Chip Designs." In Integrated Circuit Design. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_11.

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Weik, Martin H. "large-scale integrated-circuit chip." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_9947.

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Craninckx, Jan. "A Fully Integrated Single-Chip BluetoothTM Transceiver." In Analog Circuit Design. Springer US, 2002. http://dx.doi.org/10.1007/0-306-47951-6_16.

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Tehranipoor, Mohammad, Hassan Salmani, and Xuehui Zhang. "Counterfeit ICs: Detection and Prevention of Recycled ICs Using On-Chip Sensors." In Integrated Circuit Authentication. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00816-5_10.

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Dutta, Santanu. "Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip." In Integrated Circuit Design. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_24.

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Yang, Kun, Shupeng Zhong, Quan Kong, Changyou Men, and Nianxiong Nick Tan. "Low Power Energy Metering Chip." In Ultra-Low Power Integrated Circuit Design. Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9973-3_7.

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Floryan, Caspar, David Issadore, and Robert M. Westervelt. "Programmable Hybrid Integrated Circuit/Microfluidic Chips." In Point-of-Care Diagnostics on a Chip. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29268-2_2.

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Jain, Abhishek, Andrea Veggetti, Dennis Crippa, and Pierluigi Rolandi. "An On-Chip Flip-Flop Characterization Circuit." In Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-17752-1_5.

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Mardiguian, Michel. "Controlling Radiated Emissions at Chip and Integrated Circuit Level." In Controlling Radiated Emissions by Design. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-04771-3_5.

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Verghese, Nishath K., Timothy J. Schmerbeck, and David J. Allstot. "Chip/Package Shielding and Good Circuit Design Practice." In Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits. Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2239-3_11.

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Conference papers on the topic "Integrated circuit chip"

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Hui, Wenhao, Ren Shen, Pui-In Mak, Rui P. Martins, Ka-Meng Lei, and Yanwei Jia. "Single-Cell Electric Impedance Sensor Based on Integrated Circuit Chip." In 2024 IEEE BioSensors Conference (BioSensors). IEEE, 2024. http://dx.doi.org/10.1109/biosensors61405.2024.10712687.

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Harini, S., Varun Balaji, Hariharasudhan S M, and S. Santhiya. "Integrated Circuit Chip Detection." In 2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE). IEEE, 2024. http://dx.doi.org/10.1109/ic-etite58242.2024.10493311.

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Ngo, Trong-Hieu, Tae-Woo Lee, and Hyo-Hoon Park. "Multi-channel clock and data recovery circuit for chip-to-chip optical interconnects." In Integrated Optoelectronic Devices 2008, edited by Alexei L. Glebov and Ray T. Chen. SPIE, 2008. http://dx.doi.org/10.1117/12.763154.

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Kayano, Yoshiki, Ryosuke Yanagisawa, and Hiroshi Inoue. "Negative group delay circuit fabricated in an integrated circuit chip." In 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility. IEEE, 2010. http://dx.doi.org/10.1109/apemc.2010.5475515.

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Clymer, B. D., and J. W. Goodman. "Detection of optically distributed clock signals for very large scale integrated circuits." In OSA Annual Meeting. Optica Publishing Group, 1985. http://dx.doi.org/10.1364/oam.1985.tue1.

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The miniaturization of integrated circuit elements by scaling in very large scale integrated circuits (VLSI) has created a great deal of interest in the timing skew associated with transmitting signals via circuit lines to remote locations on a chip. As device sizes decrease and chip sizes increase with technological advances, the speed of the circuits on a VLSI chip becomes limited by signal transmission delays rather than device switching delays. Of particular interest is the clock signal that allows the system operations to be timed synchronously with one another. Parasitic transmission line capacitance and resistance over varying path lengths for this widely distributed signal cause a skew in its arrival time at different locations on the chip. In our approach, the 3-D nature of imaging optics is utilized to distribute the clock signal to multiple detectors. The chip is divided into functional areas within which transmission line delays are negligible, and the clock signal is distributed optically to a detector in each region. In this manner, interregional skew effects are reduced to the variation of switching speeds of the detectors and amplifiers in different functional areas, and intraregional skew effects are negligible. In addition, the division of the chip into smaller areas allows the capacitive load for each clock driver to be orders of magnitude less than that typical of chip-wide clock drivers. SPICE circuit simulations show that this difference in loading allows the optical clock driver transition delay to be less than the chip-wide electronic clock driver transition delay by a factor of 4. Design and fabrication of test circuits to measure transition delay for the optical circuit and photocurrent leakage effects in 4-µm CMOS technology are now in progress.

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Lim, Soon, Jian Hua Bi, Lian Choo Goh, Soh Ping Neo, and Sudhindra Tatti. "Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy." In ISTFA 1999. ASM International, 1999. http://dx.doi.org/10.31399/asm.cp.istfa1999p0109.

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Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

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Horimatsu, T., Y. Oikawa, M. Makiuchi, and M. Sasaki. "Low noise flip-chip integrated photoreceiver with an InGaAs-PIN photodiode and a GaAs IC." In Integrated and Guided Wave Optics. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/igwo.1988.tub1.

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Very small input capacitance and high transconductance of the first stage transistor in optical front-end receiver circuit are required to minimize the circuit noise for high bit-rate operation. However, even if bare-chip-assembling is adopted, the excess capacitance due to chip assembly degrades the receiver performance. To minimize the total input capacitance of the receiver circuit, an optoelectronic integrated circuit (OEIC) has been studied for use in the 1.3 ~ 1. 5 μm wavelength range (1) (2), but the integration scale of electronic devices and the material selectivity are limited by the difficulty of the chip fabrication process in InP based OEICs. In this paper, we describe the low-noise and high-speed performance of the flip-chip integrated (3) photoreceiver which consists of an InGaAs-PIN photodiode with very small capacitance and a GaAs pre-amplifier IC, and show the great potentials for long-wavelength optical transmission systems.

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da Silva, M. B., B. Kaczer, G. Van der Plas, G. I. Wirth, and G. Groeseneken. "On-chip circuit for massively parallel BTI characterization." In 2011 IEEE International Integrated Reliability Workshop (IIRW). IEEE, 2011. http://dx.doi.org/10.1109/iirw.2011.6142596.

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Boyer, A., S. Ben Dhia, C. Lemoine, and B. Vrignon. "Characterizing integrated circuit susceptibility with on-chip sensors." In 2012 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC). IEEE, 2012. http://dx.doi.org/10.1109/apemc.2012.6237884.

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Li, C. S., and C. M. Olsen. "Analysis of crosstalk penalty in dense optical chip interconnects using single-mode waveguides." In Integrated Photonics Research. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/ipr.1991.tud7.

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It has been shown that passive waveguides based on silicon nitride1 or polyimide2 are suitable for very short distance interconnections, such as the interconnections between chips on a multi-chip module, a printed-circuit-board, or a backplane interconnections in a digital system. Although suffering more loss than fiber, passive waveguides have the potential of providing much closer spacing and planar crossover geometries, as well as integration of modulators, optical amplifiers, and receivers on the same substrate. The density of a waveguide array is mainly limited by the coupling induced crosstalk between adjacent waveguides. Waveguide coupling effects have been intensively studied3,4 but have not been related to the system requirements. In this paper, a crosstalk model is developed and used to analyze the system requirements for a passive waveguide array environment.

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Reports on the topic "Integrated circuit chip"

1

Tang, Hong, and Chee-Wei Wong. (DARPA) Optical Radiation Cooling and Heating In Integrated Devices: Circuit cavity optomechanics for cooling and amplification on a silicon chip. Defense Technical Information Center, 2015. http://dx.doi.org/10.21236/ada626747.

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