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Bakir, Muhannad S. "Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration." Diss., Available online, Georgia Institute of Technology, 2004:, 2003. http://etd.gatech.edu/theses/available/etd-04082004-180010/unrestricted/bakir%5Fmuhannad%5Fs%5F200312%5Fphd.pdf.
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Leung, Lydia Lap Wai. "Low-loss on-chip interconnects for silicon integrated radio-frequency and microwave systems /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LEUNG.
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Mesgarzadeh, Behzad. "Circuit Techniques for On-Chip Clocking and Synchronization." Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7505.
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Jin, Yalin. "Radio-frequency integrated-circuit design for CMOS single-chip UWB systems." Thesis, [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2724.
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Zhu, Qi. "Helix-type compliant off-chip interconnect for microelectronic packaging." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17541.
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Osborn, Tyler Nathaniel. "All-copper chip-to-substrate interconnects for high performance integrated circuit devices." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28211.
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Thesis (M. S.)--Chemical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Kohl, Paul; Committee Member: Bidstrup Allen, Sue Ann; Committee Member: Fuller, Thomas; Committee Member: Hesketh, Peter; Committee Member: Hess, Dennis; Committee Member: Meindl, James.
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Mehrotra, Gaurav. "Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/22594.
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He, Yingchun. "VLSI Implementation of a Run-time Configurable Computing Integrated Circuit - The Stallion Chip." Thesis, Virginia Tech, 1998. http://hdl.handle.net/10919/36845.
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Reconfigurable computing architectures are gaining popularity as a replacement for general-purpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Run-time Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a full-custom configurable computing "FPGA"-like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a follow-up configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. Effort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.<br>Master of Science
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Lerch, Terence. "Thermal evaluation of an integrated circuit chip using infrared imaging and finite element techniques /." Online version of thesis, 1991. http://hdl.handle.net/1850/11113.
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Aulagnier, Guillaume. "Optimisation de convertisseurs DC-DC SoC (System on Chip) pour l'automobile." Phd thesis, Toulouse, INPT, 2015. http://oatao.univ-toulouse.fr/19512/1/AULAGNIER_Guillaume.pdf.
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L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.
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Koh, Sau W. "Fatigue modeling of nano-structured chip-to-package interconnections." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/28263.
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Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Rao R. Tummala; Committee Co-Chair: Ashok Saxena; Committee Member: Karl Jacob; Committee Member: Suresh Sitaraman; Committee Member: Thomas H. Sanders, Jr.
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Cho, Choongeol. "RF circuit nonlinearity characterization and modeling for embedded test." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013086.
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Belfiore, Guido, Laszlo Szilagyi, Ronny Henker, and Frank Ellinger. "Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect." SPIE, 2015. https://tud.qucosa.de/id/qucosa%3A34801.
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This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (<BER < 10^12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 2^7-1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.
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Sundaresan, Krishnan. "Activity-aware modeling and design optimization of on-chip signal interconnects." Diss., Connect to online resource - MSU authorized users, 2006.
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Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006.<br>Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.
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Choudhury, Abhishek. "Chip-last embedded low temperature interconnections with chip-first dimensions." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37104.
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Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection.
This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.
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Xu, Yuanzhe, and 徐远哲. "Variational analysis for 3D integrated circuit on-chip structures based on process-variation-aware electromagnetic-semiconductor coupledsimulation." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47047616.
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Lyson, Kyle Joshua. "On-chip automatic tuning of CMOS active inductors for use in radio frequency integrated circuit (RFIC) applications." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/lyson/LysonK1206.pdf.
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Anbalagan, Pranav. "Limitations and opportunities for wire length prediction in gigascale integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22670.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.<br>Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
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Kacker, Karan. "Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26464.
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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Mao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.
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Barabadi, Banafsheh. "Transient Joule heating in nano-scale embedded on-chip interconnects." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51786.
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Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to have a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. A computationally efficient and accurate multi-scale transient thermal methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The proposed technique has the capability of handling several decades of length scale from tens of millimeter at “package” level to several nanometers at “interconnects” level at a considerably lower computational cost, while maintaining satisfactory accuracy. This ability also applies for time scales from seconds to microseconds corresponding to various transient thermal events. The proposed method also provides the ability to rapidly predict thermal responses under different power input patterns, based on only a few representative detailed simulations, without compromising the desired spatial and temporal resolutions. It is demonstrated that utilizing the proposed model, the computational time is reduced by at least two orders of magnitude at every step of modeling.
Additionally, a novel experimental platform was developed to evaluate rapid transient Joule heating in embedded nanoscale metallic films representing buried on-chip interconnects that are not directly accessible. Utilizing the state-of-the-art sub-micron embedded resistance thermometry the effect of rapid transient power input profiles with different amplitudes and frequencies were studied. It is also demonstrated that a spatial resolution of 6 µm and thermal time constant of below 1 µs can be achieved using this technique. Ultimately, the size effects on the thermal and material properties of embedded metallic films were studied. A state-of-the-art technique to extract thermal conductivity of embedded nanoscale interconnects was developed. The proposed structure is the first device that has enabled the conductivity measurement of embedded metallic films on a substrate. It accounts for the effect of the substrate and interface without compromising the sensitivity of the device to the thermal conductivity of the metallic film. Another advantage of the proposed technique is that it can be integrated within the structure and be used for measurements of embedded or buried structures such as nanoscale on chip interconnects, without requiring extensive micro-fabrication. The dependence of the thermal conductivity on temperature was also investigated. The experimentally measured values for thermal conductivity and its dependence on temperature agree well with previous studies on free-standing nanoscale metallic bridges.
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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Honrao, Chinmay. "Fine-pitch Cu-snag die-to-die and die-to-interposer interconnections using advanced slid bonding." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50333.
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Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections.
A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology.
Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process.
To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections.
FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized.
A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.
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Lin, Ta-Hsuan. "Assembly process development, reliability and numerical assessment of copper column flexible flip chip technology." Diss., Online access via UMI:, 2008.
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Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.<br>Includes bibliographical references.
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Tinguy, Pierre. "Etude et développement d’un oscillateur à quartz intégré." Thesis, Besançon, 2011. http://www.theses.fr/2011BESA2017/document.
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Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pour<br>The increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a TO-8 enclosure (Ø15.2 mm)
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Okereke, Raphael Ifeanyi. "Electroplated multi-path compliant copper interconnects for flip-chip packages." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51800.
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The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material.
Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges.
The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The
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thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.
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Bonnard, Rémi. "Burst CMOS image sensor with on-chip analog to digital conversion." Thesis, Strasbourg, 2016. http://www.theses.fr/2016STRAD006/document.
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Ce travail vise à étudier l’apport des technologies d’intégration 3D à l’imagerie CMOS ultra-rapide. La gamme de vitesse d’acquisition considérée ici est du million au milliard d’images par seconde. Cependant au-delà d’une dizaine de milliers d’images par seconde, les architectures classiques de capteur d’images sont limitées par la bande passante des buffers de sortie. Pour atteindre des fréquences supérieures, une architecture d’imageur burst est utilisée où une séquence d’une centaine d’images est acquise et stockée dans le capteur. Les technologies d’intégration 3D ont connu un engouement depuis une dizaine d’années et sont considérées comme une solution complémentaire aux travaux menés sur les dispositifs (transistors, composants passifs) pour améliorer les performances des circuits intégrés. Notre choix s’est porté sur une technologie où les circuits intégrés sont directement empilés avant la mise en boitier (3D-SIC). La densité d’interconnexions entre les différents circuits est suffisante pour permettre l’implémentation d’interconnexions au niveau du pixel. L’intégration 3D offre d’intéressants avantages à l’imagerie intégrée car elle permet de déporter l’électronique de lecture sous le pixel. Elle permet ainsi de maximiser le facteur de remplissage du pixel tout en offrant une large place aux circuits de conditionnement du signal. Dans le cas de l’imagerie burst, cette technologie permet de consacrer une plus grande surface aux mémoires dédiées au stockage de la séquence d’image et ce au plus proche des pixels. Elle permet aussi de réaliser sur la puce la conversion analogique numérique des images acquises<br>This work aims to study the inflows of the 3D integration technology to ultra-high speed CMOS imaging. The acquisition speed range considered here is between one million to one billion images per second. However above ten thousand images per second, classical image sensor architectures are limited by the data bandwidth of the output buffers. To reach higher acquisition frequencies, a burst architecture is used where a set of about one hundred images are acquired and stored on-chip. 3D integration technologies become popular more than ten years ago and are considered as a complementary solution to the technological improvements of the devices. We have chosen a technology where integrated circuits are stacked on the top of each other (3D-SIC). The interconnection density between the circuits is high enough to enable interconnections at the pixel level. The 3D integration offers some significant advantages because it allows deporting the readout electronic below the pixel. It thus increases the fill factor of the pixel while offering a wide area to the signal processing circuit. For burst imaging, this technology provides more room to the memory dedicated to the image storage while staying close to the pixel. It also allows implementing analog to digital converter on-chip
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Chen, Tingsu. "CMOS High Frequency Circuits for Spin Torque Oscillator Technology." Licentiate thesis, KTH, Integrerade komponenter och kretsar, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-139588.
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Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.<br><p>QC 20140114</p>
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Zheng, Leo Young. "Modeling and experiments of underfill flow in a large die with a non-uniform bump pattern." Diss., Online access via UMI:, 2008.
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Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.<br>Includes bibliographical references.
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Farner, William Robert. "On-chip probe metrology /." Online version of thesis, 2008. http://hdl.handle.net/1850/6207.
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Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.
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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embedded systems in terms of abstract functions and interconnected blocks. A promising complementary approach to SLD is the use of models of computation (MoCs) to formally describe the execution semantics of functions and blocks through a set of rules. However, also when this formalization is used, there is no clear way to synthesize system-level models into software (SW) and hardware (HW) towards a NoC-based MPSoC implementation, i.e., there is a lack of system design automation (SDA) techniques to rapidly synthesize and prototype system-level models onto heterogeneous NoC-based MPSoCs. In addition, many of the proposed solutions require large overhead in terms of SW components and memory requirements, resulting in complex and customized multi-processor platforms. In order to tackle the problem, a novel model-based SDA flow has been developed as part of the thesis. It starts from a system-level specification, where functions execute according to the synchronous MoC, and then it can rapidly prototype the system onto an FPGA configured as an heterogeneous NoC-based MPSoC. In the first part of the thesis the HeartBeat model is proposed as a model-based technique which fills the abstraction gap between the abstract system-level representation and its implementation on the multiprocessor prototype. Then details are provided to describe how this technique is automated to rapidly prototype the modeled system on a flexible platform, permitting to adjust the system specification until the designer is satisfied with the results. Finally, the proposed SDA technique is improved defining a methodology to automatically explore possible design alternatives for the modeled system to be implemented on a heterogeneous NoC-based MPSoC. The goal of the exploration is to find an implementation satisfying the designer's requirements, which can be integrated in the proposed SDA flow. Through the proposed SDA flow, the designer is relieved from implementation details and the design time of systems targeting heterogeneous NoC-based MPSoCs on FPGA is significantly reduced. In addition, it reduces possible design errors proposing a completely automated technique for fast prototyping. Compared to other SDA flows, the proposed technique targets a bare-metal solution, avoiding the use of an operating system (OS). This reduces the memory requirements on the FPGA platform comparing to related work targeting MPSoC on FPGA. At the same time, the performance (throughput) of the modeled applications can be increased when the number of processors of the target platform is increased. This is shown through a wide set of case studies implemented on FPGA.<br><p>QC 20140609</p>
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Staiculescu, Daniela. "Design rules for RF and microwave flip-chip." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13265.
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Graupner, Achim. "Robuster Entwurf und statistische Modellierung für Bildsensoren mit hochparalleler analoger Bildverarbeitungseinheit." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-108459.
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Die gemeinsame Integration von Bildsensor und analoger hochparalleler Verarbeitungseinheit stellt eine Möglichkeit zur Realisierung von leistungsfähigen ein-chip Bildaufnahmesystemen dar. Die vorliegende Arbeit liefert Beiträge zum systematischen Entwurf von derartigen Systemen und analysiert bekannte und neuartige Schaltungstechniken bezüglich ihrer Eignung für deren Implementierung. Anhand des vom Autor mitentwickelten CMOS-Bildsensors mit hochparalleler analoger Bildverarbeitungseinheit werden die vorgestellten Methoden und Schaltungstechniken demonstriert. Die Problematik beim Entwurf hochparalleler analoger Systeme besteht in der im Vergleich zu digitalen Systemen geringen Automatisierbarkeit. Es ist kein top-down-Entwurf möglich, da nicht jede beliebige Funktion mit beliebiger Genauigkeit realisierbar ist. Um die jeweilige Genauigkeit der Funktionsblöcke bei der Analyse des hochparallelen Systems berücksichtigen zu können, sind rechenaufwendige Simulationen nötig. Um diesen Rechenaufwand zu senken, wird vorgeschlagen, für die Simulation des Gesamtsystems einen angepaßten Simulator und für die Analyse der schaltungstechnischen Realisierung der Funktionsblöcke konventionelleWerkzeuge für elektrische Netzwerke zu verwenden. Die beiden Simulationsdomänen werden mit Hilfe von numerischen Verhaltensmodellen verbunden. Durch diese Trennung wird die Simulation des Gesamtsystems als Bestandteil des Entwurfsflusses praktikabel. Für die Bewertung, inwieweit die zufälligen Schwankungen der Bauelementeparameter das Verhalten von Baublöcken beeinflussen, wird die Varianzanalyse als Alternative zur konventionellen Monte-Carlo-Analyse vorgeschlagen. Die Varianzanalyse ist wesentlich weniger rechenaufwendig und liefert genaue Resultate für alle Schaltungseigenschaften mit hinreichend glatten Parameterabhängigkeiten, wenn die Bauelementeparameter als normalverteilt und statistisch unabhängig angenommen werden können. Sie hat darüberhinaus den Vorteil, das Schaltungsverständnis für den Entwerfer zu erhöhen, da sofort die Bauelementeparameter mit dem größten Einfluß auf das Schaltungsverhalten identifiziert werden können. Der Vergleich verschiedener Schaltungstechniken hat gezeigt, daß zeitdiskrete wertkontinuierliche Verfahren, bei denen die Information als Strom repräsentiert wird, für die Realisierung von hochparallelen analogen Systemen besonders geeignet sind. Als besonderer Vorteil ist die weitestgehende Unabhängigkeit des Verhaltens derartiger Schaltungen von Bauelementeparametern hervorzuheben.Weitere Schaltungstechniken, deren Verhalten von zufälligen Parameterabweichungen nur wenig beeinflußt werden, sind in einer Taxonomie zusammengefaßt. Es wurde ein CMOS-Bildsensor mit hochparalleler analoger Bildverarbeitungseinheit und digitaler Ausgabe realisiert. Der current-mode-Bildsensor ist separat von der Verarbeitungseinheit angeordnet. Es wurden vier verschiedene Realisierungsmöglichkeiten untersucht und eine konventionelle integrierende voltage-mode Pixelzelle mit nachfolgendem differentiellen Spannungs- Strom-Wandler realisiert. Das Rechenfeld ist für die räumliche Faltung oder lineare Transformation von Bilddaten mit digital bereitzustellenden Koeffizienten ausgelegt. Dessen Operation basiert auf einer bit-weisen analogen Verarbeitung. Der Schaltkreis wurde erfolgreich getestet. Die nachgewiesene Bildqualität deckt sich in guter Näherung mit den bei der Simulation des Gesamtsystems getroffenen Vorhersagen<br>The joined implementation of an image sensor and a highly parallel analog processing unit is an advantageous approach for realizing efficient single-chip vision systems. This thesis proposes a design flow for the development of such systems. Moreover known and novel circuit techniques are analysed with respect for their suitability for the implementation of highly parallel systems. The presented methodologies and circuit techniques are demonstrated at the example of a CMOS image sensor with an embedded highly parallel analog image processing unit in whose design the author was involved. One of the major problems in designing highly parallel analog circuits is the low automation compared to the design of digital circuits. As not every function can be realized with arbitrary accuracy top-down-design is not feasible. So, when analysing the system behaviour the respective precision of each function block has to be considered. As this is a very demanding task in terms of computing power, it is proposed to use a dedicated tool for the simulation of the system and conventional network analysis tools for the inspection of the circuit realizations. Both simulation domains are combined by means of numerical behavioural models. By using separate tools system-simulations of highly parallel analog systems as a part of the design flow become practicable. Variance analysis basing on parameter sensitivities is proposed as an alternative to the conventional Monte-Carlo-analysis for investigating the influence of random device parameter variations on the system behaviour. Variance analysis requires much less computational effort while providing accurate results for all circuit properties with sufficiently smooth parameter dependencies if the random parameters can be assumed normally distributed and statistically independent. Additionally, variance analysis increases the designer’s knowledge about the circuit, as the device parameters with the highest influence on the circuit performance can immediately be identified. The comparison of various circuit techniques has shown, that sampled-time continuous-valued current-mode principles are the best choice for realizing highly parallel analog systems. A distinctive advantage of such circuits is their almost independence from device parameters. A selection of further circuit techniques with low sensitivity to random device parameter variations are summarized in a taxonomy. A CMOS image sensor with embedded highly parallel analog image processing unit has been implemented. The image sensor provides a current-mode output and is arranged separate from the processing unit. Four different possibilities for realizing an image sensor have been analysed. A conventional integrating voltage-mode pixel cell with a succeeding differential voltage- to-current-converter has been selected. The processing unit is designed for performing spatial convolution and linear transformation with externally provided digital kernels. It operates in bit-wise analog manner. The chip has been tested successfully. The measured image quality in good approximation corresponds with the estimations made with system simulations
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Neto, Hugo Daniel Barbosa. "Packaging of photonic integrated circuits." Master's thesis, Universidade de Aveiro, 2017. http://hdl.handle.net/10773/23552.
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Mestrado em Engenharia Eletrónica e Telecomunicações<br>With the continuous evolution of optical communication systems, emerged a need for high-performance optoelectronic elements at lower costs. Photonic packaging plays a key role for the next-generation of optical devices.
In this work a standard packaging design rules is described, covering both the electrical and optical-packaging exploring both active and passive adjusting techniques, as well as the thermal management of the photonic integrated circuit (PIC).
First a process for fiber-to-chip coupling with custom made ball-lensed fibers, is performed and tested initially in a testing-chip and thereafter in a manufactured practical study-case composed by a silicon holder with an InP distributed feedback (DFB) laser. The process of manufacturing etched V-grooves for fiber alignment is approached in detail.
After this, for electrical interconnects and radio frequency (RF) packaging, both wire-bonding and flip-chip technique are discussed, and a characterization of the s-parameters in a PIC with wire-bonding is presented.
A technique based on ruthenium-based sensors and platinum and titanium-based sensors for thermal control of the PIC is studied and the tested using a custom made PCB designed exclusively for that purpose.<br>Com a constante evolução dos sistemas de comunicação óticos veio a necessidade de componentes optoelectrónicos de elevada performance a custos relativamente baixos. O encapsulamento ótico tem um papel chave nos dispositivos óticos de última geração.
Neste trabalho são descritas as regras de um processo de encapsulamento padrão, que abrange tanto o encapsulamento elétrico e ótico onde são exploradas técnicas de ajustamento ativas e passivas bem como o controlo térmico do circuito ótico integrado (PIC).
No início foi efetuado um processo de acoplamento da fibra ao chip com fibras de lente esférica personalizadas, numa primeira usando um chip de teste e de seguida num caso de estudo prático que consiste numa estrutura composta por um holder de silício com um laser de realimentação distribuída (DFB). É abordado em detalhe o processo de fabricação de V-grooves para o alinhamento da fibra com o chip.
De seguida são apresentadas e discutidas as técnicas de wire-bonding e flip-chip para o encapsulamento elétrico e ligação dos conectores de radiofrequência (RF), é feito um estudo onde são apresentados os resultados da caraterização dos parâmetros S de um PIC com wire-bonding.
Para o controlo térmico do módulo é apresentada uma técnica baseada em sensores de temperatura de ruténio e sensores de Platina e titânio testada numa PCB personalizada
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Viale, Benjamin. "Development of predictive analysis solutions for the ESD robustness of integrated circuits in advanced CMOS technologies." Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI117.
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Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer<br>As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues
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Philippon-Martin, Audrey. "Étude d’une nouvelle filière de composants sur technologie nitrure de gallium : conception et réalisation d’amplificateurs distribués de puissance large bande à cellules cascodes en montage flip-chip et technologie MMIC." Limoges, 2007. https://aurore.unilim.fr/theses/nxfile/default/862a35bd-117b-4bc6-b2a0-044747ee2ff7/blobholder:0/2007LIMO4025.pdf.
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Ces travaux de recherche se rapportent à l’étude de transistors HEMTs en Nitrure de Gallium pour l’amplification de puissance micro-onde. Une étude des caractéristiques des matériaux grand gap et plus particulièrement du GaN est réalisée afin de mettre en exergue l’adéquation de leurs propriétés pour des applications de puissance hyperfréquence telle que l’amplification large bande. Dans ce contexte, des résultats de caractérisations et modélisations électriques de composants passifs et actifs sont présentés. Les composants passifs dédiés aux conceptions de circuits MMIC sont décrits et différentes méthodes d’optimisation que ce soit au niveau électrique ou électromagnétique sont explicitées. Les modèles non linéaires de transistors impliqués dans nos conceptions sont de même détaillés. Le fruit de ces travaux concerne la conception d’amplificateurs distribués de puissance large bande à base de cellules cascode de HEMTs GaN, l’un étant reportés en flip-chip sur un substrat d’AlN, le second en technologie MMIC. La version MMIC permet d’atteindre 6. 3W sur la bande 4-18GHz à 2dB de compression. Ces résultats révèlent les fortes potentialités attendues des composants HEMTs GaN<br>The aim of this study is to assess the potentialities of HEMTs AlGaN/GaN transistors for RF power applications. The properties of wide band-gap materials and especially the GaN material are analysed in order to highlight their capabilities for applications to wideband power amplifiers. Modeling of passive components is explained and the design guide library on SiC substrate is implemented. Characterization results as well as linear and nonlinear simulations are presented on devices and circuits. The results of this work give concrete expression to the design of wideband power amplifiers showing a distributed architecture of cascode cells using GaN HEMTs, the first one flip-chip mounted onto an AlN substrate and the second one in MMIC technology. One MMIC version allows to obtain 6. 3W over a 4 to 18GHz bandwidth at 2dB compression input power. These results bring to light famous potentialities assigned to HEMTs GaN components
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Ren, Qiu-shi. "Dynamic optical interconnection for integrated circuit chips /." The Ohio State University, 1991. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487687485810817.
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Liu, Le-Chin Eugene. "Global routing and pin assignment for multi-layer chip-level layout /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/5898.
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Feero, Brett Stanley. "Three dimensional networks-on-chip a performance evaluation /." Online access for everyone, 2008. http://www.dissertations.wsu.edu/Thesis/Spring2008/b_feero_042208.pdf.
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Meisenzahl, Eric J. "A test chip approach to routine process control /." Online version of thesis, 1988. http://hdl.handle.net/1850/10562.
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Wong, Siu-Kei. "Low power techniques on nanometer scale instruction bus and network-on-chip /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20WONGS.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 73-76). Also available in electronic version. Access restricted to campus users.
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Wu, Wei-Chung. "On-chip charge pumps." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13451.
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Zarkesh-Ha, Paymen. "Global interconnect modeling for a Gigascale System-on-a-Chip (GSoC)." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13027.
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Tinguy, Pierre. "Etude et développement d'un oscillateur à quartz intégré." Phd thesis, Université de Franche-Comté, 2011. http://tel.archives-ouvertes.fr/tel-00675277.
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Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d'entretien de type Colpitts,la mise en forme et jusqu'à l'adaptation du signal à sa charge d'utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s'orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del'architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l'avons reportée par flip chip sur une interfacespécifique pour
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Gore, Kapil Suhling J. C. Jaeger Richard C. "Vibration analysis of test chips with integrated piezoresistive stress sensors." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Summer/Theses/GORE_KAPIL_36.pdf.
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Tsui, Yat Kit. "Design and fabrication of a flip-chip-on-chip multi-chip module with 3D packaging structure and through-silicon-via for underfill dispensing /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?MECH%202004%20TSUI.
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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.<br>Includes bibliographical references (leaves 116-127). Also available in electronic version. Access restricted to campus users.
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Guo, Xiaoling. "CMOS intra-chip wireless clock distribution." [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011427.
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Bonatto, Alexsandro Cristóvão. "Controle adaptativo para acesso à memória compartilhada em sistemas em chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/109193.
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Acessos simultâneos gerados por Elementos de Processamento (EP) contidos nos Sistemas em Chip (SoC) para um único canal de memória externa coloca desafios que requerem uma atenção especial por constituírem o gargalo para o desempenho de processamento. No caso em que os EPs são microprocessadores, a questão fica ainda mais evidente, pois a taxa de aumento da velocidade dos microprocessadores excede a taxa de aumento da velocidade da DRAM. Ambas aumentam exponencialmente, mas a expoente dos microprocessadores é maior do que a das memórias. Este efeito é denominado de “muro de memória” (Memory Wall) e representa que o gargalo de processamento está relacionado à diferença de velocidade. Neste cenário, novas estratégias de controle de acesso são necessárias para melhorar o desempenho. Plataformas heterogêneas de processamento multimídia são formadas por diversos EPs. Os acessos con- correntes à regiões de memória não contíguas em uma DRAM reduzem a largura de banda e aumentam a latência de acesso aos dados, degradando o desempenho de processamento. Esta tese mostra que a eficiência computacional pode ser melhorada com o uso de um fluxo de projeto centralizado em memória, ou seja, orientado para os aspectos funcionais da DRAM. Neste trabalho é apresentado um subsistema de memória com gerenciamento adaptativo de compar- tilhamento do canal de memória entre múltiplos clientes. Esta tese apresenta a arquitetura de um controlador de memória com comportamento predizível que faz a avaliação do pior caso de execução para as transações solicitadas pelos clientes em tempo de execução. Um modelo baseado em atrasos é utilizado para prever os piores casos para o conjunto de clientes. O sub-sistema de memória centraliza a comunicação de dados e gerencia os acessos dos diversos EPs do sistema, de forma que a comunicação seja atendida de acordo com as necessidades de cada aplicação. São apresentadas três contribuições principais: 1) um método de projeto de sistemas integrados centralizado em memória, que orienta o projeto para os aspectos funcionais da me- mória compartilhada; 2) um modelo baseado em atrasos para estimar o pior caso de execução do sistema, quanto aos tempos de resposta e largura de banda mínima alocada por cliente; 3) um árbitro adaptativo para gerenciamento dos acessos à memória externa com garantias de prazos de execução das transações.<br>The number of Processing Elements (PE) contained in a System-on-Chip (SoC) follows the growth of the number of transistors per chip. A SoC composed of multiple PEs, in some ap- plications such as multimedia, implements algorithms that handle large volumes of data and justify the use of an external memory with large capacity. External memory accesses are shared by multiple PEs adding challenges that may have special attention because they constitute the bottleneck for performance and relevant factor for power consumption. In the case where the PEs are microprocessors, this issue becomes even more evident as the rate of increase of speed of microprocessors exceeds the rate of increase in speed of DRAM. This effect is called “mem- ory wall” and represents that the bottleneck processing is related to the speed of data access. In this scenario, new access control strategies are needed to improve processing performance. Heterogeneous platforms for multimedia processing are formed by several PEs. The concur- rent accesses to DRAM reduce bandwidth and increase latency access to data, degrading the processing performance. This thesis shows that significant improvements in computational effi- ciency can be obtained using a design methodology oriented to the functional aspects of DRAM through a memory subsystem with adaptive management. It is presented the data communica- tion architecture for integration of PEs system based on an analytical model to reduce latency and guarantee Quality of Service (QoS). The memory subsystem is organized as a hierarchy of memories, with a proposed integration of PEs oriented centered in the main memory. The memory subsystem centralized data communication and manages the access of several PEs sys- tem so that communication is served according to the needs of each application. This thesis proposes three major contributions: 1) a methodology for design integrated systems based on the memory-centric design approach, 2) an analytical model based on delays used to evaluate the worst-case performance of the memory subsystem, 3) an arbiter for adaptive management of accesses to the external memory with guaranteed execution times of transactions.
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Pourbakhsh, Seyed Alireza. "Dummy TSV-Based Timing Optimization for 3D On-Chip Memory." Thesis, North Dakota State University, 2016. https://hdl.handle.net/10365/29093.
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Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies are stacked vertically, and through silicon vias (TSVs) are used to transfer power and signals between different dies. The electrical characteristic of TSVs can be modeled with equivalent circuits consisted of passive elements. In this thesis, we use “dummy” TSVs as electrical delay units in 3D SRAMs. Our results prove that dummy TSVs based delay units are as effective as conventional delay cells in performance, increase the operational frequency of SRAM up to 110%, reduce the usage of silicon area up to 88%, induce negligible power overhead, and improve robustness against voltage supply variation and fluctuation.
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Ranganathan, Lavakumar. "Sensor-array chip hybrid for simultaneous multiple analyte detection /." Full text open access at:, 2007. http://content.ohsu.edu/u?/etd,260.
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