Relevant bibliographies by topics / Integrated Circuit Fabrication

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Integrated Circuit Fabrication'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Integrated Circuit Fabrication"

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Abelson, L. A., and G. L. Kerber. "Superconductor integrated circuit fabrication technology." Proceedings of the IEEE 92, no. 10 (October 2004): 1517–33. http://dx.doi.org/10.1109/jproc.2004.833652.

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Takeda, Yasunori, Tomohito Sekine, Rei Shiwaku, Tomohide Murase, Hiroyuki Matsui, Daisuke Kumaki, and Shizuo Tokito. "Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor." Applied Sciences 8, no. 8 (August 9, 2018): 1331. http://dx.doi.org/10.3390/app8081331.

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The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.
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Rao, S., A. J. Strojwas, J. P. Lehoczky, and M. J. Schervish. "Monitoring multistage integrated circuit fabrication processes." IEEE Transactions on Semiconductor Manufacturing 9, no. 4 (1996): 495–505. http://dx.doi.org/10.1109/66.542165.

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Lam, H. W. "SIMOX SOI for integrated circuit fabrication." IEEE Circuits and Devices Magazine 3, no. 4 (July 1987): 6–11. http://dx.doi.org/10.1109/mcd.1987.6323126.

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Resnick, D. J., W. J. Dauksher, D. Mancini, K. J. Nordquist, T. C. Bailey, S. Johnson, N. Stacey, et al. "Imprint lithography for integrated circuit fabrication." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 6 (2003): 2624. http://dx.doi.org/10.1116/1.1618238.

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Sequeda, Federico O. "Integrated Circuit Fabrication — A Process Overview." JOM 37, no. 5 (May 1985): 43–50. http://dx.doi.org/10.1007/bf03257740.

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Nahar, R. K. "Materials and Processes for Integrated Circuit Fabrication." IETE Journal of Education 41, no. 3-4 (July 2000): 71–74. http://dx.doi.org/10.1080/09747338.2000.11415732.

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Murduck, J. M., A. Kirschenbaum, A. Mayer, V. Morales, and C. Lavoie. "High-performance Nb integrated circuit process fabrication." IEEE Transactions on Appiled Superconductivity 13, no. 2 (June 2003): 87–90. http://dx.doi.org/10.1109/tasc.2003.813651.

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Habibpour, Omid, Wlodzimierz Strupinski, Niklas Rorsman, Pawel Ciepielewski, and Herbert Zirath. "Generic Graphene Based Components and Circuits for Millimeter Wave High Data-rate Communication Systems." MRS Advances 2, no. 58-59 (2017): 3559–64. http://dx.doi.org/10.1557/adv.2017.433.

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ABSTRACT We are developing millimeter wave (mm-wave) components and circuits based on hydrogen-intercalated graphene. The development covers epitaxial graphene growth, device fabrication, modelling, integrated circuit design and fabrication, and circuit characterizations. The focus of our work is to utilize the distinctive graphene properties and realize new components that can overcome some of the main challenges of existing mm-wave technologies in term of linearity.
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Gierczak, Miroslaw Gracjan, Jacek Wróblewski, and Andrzej Dziedzic. "The design and fabrication of electromagnetic microgenerator with integrated rectifying circuits." Microelectronics International 34, no. 3 (August 7, 2017): 131–39. http://dx.doi.org/10.1108/mi-02-2017-0010.

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Purpose The paper focuses on design, fabrication and characterization of electromagnetic microgenerators with integrated rectifying circuits to convert AC output signal to DC one. The work includes research on simulation of voltage-rectifying circuits, including charge pump, realization of the experimental printed circuit board (PCB) with selected electronic circuits and the execution of the final structure with integrated rectifying circuit. Measurements were performed on these circuits. Design/methodology/approach Electromagnetic microgenerators include multipole permanent magnets secured on rotor three-phase brushless direct current (BLDC) motor and planar multilayer multiple coils. These were fabricated using low temperature co-fired ceramics (LTCC) technology. In our experiment, six rectifying circuits were simulated and tested with a structure consisting of eight layers of coils and with an outer diameter of 50 mm fabricated earlier. Findings The microgenerator with Graetz bridge generates higher output power than the modified charge pump at the same rotary speed. However, it is less stable for the distance change between the structure and the magnets than the modified charge pump, which has more constant output power in a wider range of load resistance. Originality/value The presented electronic rectifying circuits are novel for LTCC-based electromagnetic microgenerator application. The structure with integrated rectifying circuits allows generation of electrical output power larger than 100 mW at the rotor speed of about 8,000 rpm.
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Dissertations / Theses on the topic "Integrated Circuit Fabrication"

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Rutherford, William C. "Gallium arsenide integrated circuit modeling, layout and fabrication." Thesis, University of British Columbia, 1987. http://hdl.handle.net/2429/26733.

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The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Fan, Wei Ph D. Massachusetts Institute of Technology. "Advanced modeling of planarization processes for integrated circuit fabrication." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78446.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 215-225).
Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted.
by Wei Fan.
Ph.D.
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Buttar, Alistair George. "CMOS process simulation." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/13282.

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Villalaz, Ricardo A. "Volume Grating Couplers for Optical Interconnects: Analysis, Design, Fabrication, and Testing." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07102004-165012/unrestricted/villalaz%5Fricardo%5Fa%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Thomas Gaylord.
Glytsis, Elias, Committee Co-Chair ; Buck, John, Committee Member ; Kohl, Paul, Committee Member ; Adibi, Ali, Committee Member ; Gaylord, Thomas, Committee Chair. Vita. Includes bibliographical references.
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Chai, Yang. "Fabrication and characterization of carbon nanotubes for interconnect applications /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20CHAI.

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Broadfoot, Stephen. "Design, fabrication and testing of a novel W-band monolithic millimetre-wave integrated circuit mixer." Thesis, University of Glasgow, 1999. http://theses.gla.ac.uk/1741/.

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La, Pietra Andrew R. "Establishing a bipolar fabrication service for analog circuit realization at the Rochester Institute of Technology /." Online version of thesis, 1991. http://hdl.handle.net/1850/11272.

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Kamal, Tazrien. "Development of an integrated organic film removal and surface conditioning process using low molecular weight alcohols for advanced Integrated Circuit (IC) fabrication." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/11255.

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Kacker, Karan. "Design and fabrication of free-standing structures as off-chip interconnects for microsystems packaging." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26464.

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Thesis (Ph.D)--Mechanical Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Dr. Suresh K. Sitaraman; Committee Member: Dr. F. Levent Degertekin; Committee Member: Dr. Ioannis Papapolymerou; Committee Member: Dr. Madhavan Swaminathan; Committee Member: Dr. Nazanin Bassiri-Gharb. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Menezes, Gary. "Modeling, design, fabrication and characterization of glass package-to-PCB interconnections." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51781.

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Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.
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Books on the topic "Integrated Circuit Fabrication"

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Shepherd, Peter. Integrated circuit design, fabrication, and test. New York: McGraw-Hill, 1996.

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Shepherd, Peter. Integrated Circuit Design, Fabrication and Test. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8.

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Simons, Rainee N. Novel low loss wide-band multi-port integrated circuit technology for RF/microwave applications. [Cleveland, Ohio]: National Aeronautics and Space Administration, Glenn Research Center, 2001.

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Simons, Rainee N. Novel low loss wide-band multi-port integrated circuit technology for RF/microwave applications. [Cleveland, Ohio]: National Aeronautics and Space Administration, Glenn Research Center, 2001.

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Simons, Rainee N. Novel low loss wide-band multi-port integrated circuit technology for RF/microwave applications. [Cleveland, Ohio]: National Aeronautics and Space Administration, Glenn Research Center, 2001.

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Simons, Rainee. Novel low loss wide-band multi-port integrated circuit technology for RF/microwave applications. [Cleveland, Ohio]: National Aeronautics and Space Administration, Glenn Research Center, 2001.

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Kondo, K. Morphological evolution of electrodeposits and electrochemical processing in ULSI fabrication and electrodeposition of and on semiconductors IV: Proceedings of the international symposia. Edited by Electrochemical Society Electrodeposition Division, Electrochemical Society. Dielectric Science and Technology Division, Electrochemical Society Electronics Division, and Electrochemical Society Meeting. Pennington, NJ: Electrochemical Society, 2005.

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Custom-specific integrated circuits: Design and fabrication. New York: Dekker, 1985.

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The worldwide IC wafer fabrication foundry market. Saratoga, Calif: Electronic Trend Publications, 1993.

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1936-, Sze S. M., ed. Fundamentals of semiconductor fabrication. New York: Wiley, 2004.

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Book chapters on the topic "Integrated Circuit Fabrication"

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Morant, M. J. "Integrated Circuit Fabrication Processes." In Integrated Circuit Design and Technology, 33–47. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4899-7198-2_3.

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Murray, Alan F., and H. Martin Reekie. "Fabrication of Silicon Integrated Circuits." In Integrated Circuit Design, 43–62. London: Macmillan Education UK, 1987. http://dx.doi.org/10.1007/978-1-349-18758-4_3.

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Murray, Alan F., and H. Martin Reekie. "Fabrication of Silicon Integrated Circuits." In Integrated Circuit Design, 43–62. New York, NY: Springer New York, 1987. http://dx.doi.org/10.1007/978-1-4899-6675-9_3.

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Shepherd, Peter. "The IC Design Process." In Integrated Circuit Design, Fabrication and Test, 1–20. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_1.

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Shepherd, Peter. "IC Families." In Integrated Circuit Design, Fabrication and Test, 21–41. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_2.

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Shepherd, Peter. "Transistor-Level Design." In Integrated Circuit Design, Fabrication and Test, 42–96. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_3.

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Shepherd, Peter. "IC Realization." In Integrated Circuit Design, Fabrication and Test, 97–116. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_4.

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Shepherd, Peter. "CAD." In Integrated Circuit Design, Fabrication and Test, 117–45. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_5.

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Shepherd, Peter. "Testing." In Integrated Circuit Design, Fabrication and Test, 146–75. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_6.

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Shepherd, Peter. "Afterword." In Integrated Circuit Design, Fabrication and Test, 176–81. London: Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13656-8_7.

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Conference papers on the topic "Integrated Circuit Fabrication"

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Chim, Stanley S. C., and Gordon S. Kino. "Optical metrology for integrated circuit fabrication." In Micro - DL tentative, edited by William H. Arnold. SPIE, 1991. http://dx.doi.org/10.1117/12.44430.

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Garg, Siddharth. "Inspiring trust in outsourced integrated circuit fabrication." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927158.

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Johri, P. K. "Dispatching in an integrated circuit wafer fabrication line." In the 21st conference. New York, New York, USA: ACM Press, 1989. http://dx.doi.org/10.1145/76738.76855.

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Lee, Hyun-Shik, Shin-Mo An, Seung Gol Lee, B. H. O, Se Geon Park, and El-Hang Lee. "Fabrication of a flexible optical printed circuit board (FO-PCB)." In Integrated Optoelectronic Devices 2007, edited by Louay A. Eldada and El-Hang Lee. SPIE, 2007. http://dx.doi.org/10.1117/12.708704.

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Bayat, Khadijeh, Mahdi F. Baroughi, and Nosratollah Granpayeh. "Design of a test set for characterization of optical devices in silica-based optical integrated circuit technology." In Photonics Fabrication Europe, edited by Giancarlo C. Righini. SPIE, 2003. http://dx.doi.org/10.1117/12.472448.

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Tan, Cher Ming, and FeiFei He. "Predicting Integrated Circuit Reliability from Wafer Fabrication Technology Reliability Data." In 2007 International Symposium on Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/isicir.2007.4441849.

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Salzman, K. A. "Statistical process control implementation for GaAs integrated circuit fabrication." In 1992 GaAs IC Symposium Technical Digest. IEEE, 1992. http://dx.doi.org/10.1109/gaas.1992.247187.

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Shilpi, Kapil Bhatt, Sandeep Kumar, Sandeep, and C. C. Tripathi. "Fabrication and characterization of Al/PMMA/Cr metal-insulator-metal diode." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8073897.

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Mukherjee, Biswanath. "Ambipolar organic field-effect transistor and inverter: Hybrid fabrication and high photoresponse." In 2017 Devices for Integrated Circuit (DevIC). IEEE, 2017. http://dx.doi.org/10.1109/devic.2017.8073943.

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Jewell, Tanya E., and Donald L. White. "Integrated Optical Circuit Grating Fabrication Using 0.25 µm Optical Lithography." In O-E/Fiber LASE '88, edited by Mark A. Mentzer. SPIE, 1988. http://dx.doi.org/10.1117/12.960070.

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Reports on the topic "Integrated Circuit Fabrication"

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Penn, John. 0.15-micron Gallium Nitride (GaN) Microwave Integrated Circuit Designs Submitted to TriQuint Semiconductor for Fabrication. Fort Belvoir, VA: Defense Technical Information Center, September 2012. http://dx.doi.org/10.21236/ada570172.

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Penn, John. Gallium Arsenide (GaAs) Microwave Integrated Circuit Designs Submitted to TriQuint Semiconductor for Fabrication (ARL Tile #2). Fort Belvoir, VA: Defense Technical Information Center, September 2010. http://dx.doi.org/10.21236/ada529992.

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Resnick, Douglas, and Konstantin Likharev. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication. Fort Belvoir, VA: Defense Technical Information Center, August 2008. http://dx.doi.org/10.21236/ada487894.

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Wagner, G. R. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, April 1994. http://dx.doi.org/10.21236/ada282505.

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Wagner, G. R. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, January 1994. http://dx.doi.org/10.21236/ada277684.

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Talisa, S. H., and J. Talvacchio. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, March 1995. http://dx.doi.org/10.21236/ada292480.

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Wagner, G. R. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, July 1992. http://dx.doi.org/10.21236/ada256109.

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Wagner, G. R. Processing, Fabrication and Demonstration of HTS Integrated Microwave CIrcuits. Fort Belvoir, VA: Defense Technical Information Center, April 1993. http://dx.doi.org/10.21236/ada265789.

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Wagner, G. R. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, January 1993. http://dx.doi.org/10.21236/ada263161.

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Talisa, S. H., J. Talvacchio, and G. R. Wagner. Processing, Fabrication, and Demonstration of HTS Integrated Microwave Circuits. Fort Belvoir, VA: Defense Technical Information Center, October 1994. http://dx.doi.org/10.21236/ada290220.

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