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Journal articles on the topic 'Integrated Circuit Fabrication'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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1

Abelson, L. A., and G. L. Kerber. "Superconductor integrated circuit fabrication technology." Proceedings of the IEEE 92, no. 10 (October 2004): 1517–33. http://dx.doi.org/10.1109/jproc.2004.833652.

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2

Takeda, Yasunori, Tomohito Sekine, Rei Shiwaku, Tomohide Murase, Hiroyuki Matsui, Daisuke Kumaki, and Shizuo Tokito. "Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor." Applied Sciences 8, no. 8 (August 9, 2018): 1331. http://dx.doi.org/10.3390/app8081331.

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The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

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3

Rao, S., A. J. Strojwas, J. P. Lehoczky, and M. J. Schervish. "Monitoring multistage integrated circuit fabrication processes." IEEE Transactions on Semiconductor Manufacturing 9, no. 4 (1996): 495–505. http://dx.doi.org/10.1109/66.542165.

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4

Lam, H. W. "SIMOX SOI for integrated circuit fabrication." IEEE Circuits and Devices Magazine 3, no. 4 (July 1987): 6–11. http://dx.doi.org/10.1109/mcd.1987.6323126.

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5

Resnick, D. J., W. J. Dauksher, D. Mancini, K. J. Nordquist, T. C. Bailey, S. Johnson, N. Stacey, et al. "Imprint lithography for integrated circuit fabrication." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 21, no. 6 (2003): 2624. http://dx.doi.org/10.1116/1.1618238.

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6

Sequeda, Federico O. "Integrated Circuit Fabrication — A Process Overview." JOM 37, no. 5 (May 1985): 43–50. http://dx.doi.org/10.1007/bf03257740.

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7

Nahar, R. K. "Materials and Processes for Integrated Circuit Fabrication." IETE Journal of Education 41, no. 3-4 (July 2000): 71–74. http://dx.doi.org/10.1080/09747338.2000.11415732.

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8

Murduck, J. M., A. Kirschenbaum, A. Mayer, V. Morales, and C. Lavoie. "High-performance Nb integrated circuit process fabrication." IEEE Transactions on Appiled Superconductivity 13, no. 2 (June 2003): 87–90. http://dx.doi.org/10.1109/tasc.2003.813651.

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9

Habibpour, Omid, Wlodzimierz Strupinski, Niklas Rorsman, Pawel Ciepielewski, and Herbert Zirath. "Generic Graphene Based Components and Circuits for Millimeter Wave High Data-rate Communication Systems." MRS Advances 2, no. 58-59 (2017): 3559–64. http://dx.doi.org/10.1557/adv.2017.433.

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ABSTRACT We are developing millimeter wave (mm-wave) components and circuits based on hydrogen-intercalated graphene. The development covers epitaxial graphene growth, device fabrication, modelling, integrated circuit design and fabrication, and circuit characterizations. The focus of our work is to utilize the distinctive graphene properties and realize new components that can overcome some of the main challenges of existing mm-wave technologies in term of linearity.

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10

Gierczak, Miroslaw Gracjan, Jacek Wróblewski, and Andrzej Dziedzic. "The design and fabrication of electromagnetic microgenerator with integrated rectifying circuits." Microelectronics International 34, no. 3 (August 7, 2017): 131–39. http://dx.doi.org/10.1108/mi-02-2017-0010.

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Purpose The paper focuses on design, fabrication and characterization of electromagnetic microgenerators with integrated rectifying circuits to convert AC output signal to DC one. The work includes research on simulation of voltage-rectifying circuits, including charge pump, realization of the experimental printed circuit board (PCB) with selected electronic circuits and the execution of the final structure with integrated rectifying circuit. Measurements were performed on these circuits. Design/methodology/approach Electromagnetic microgenerators include multipole permanent magnets secured on rotor three-phase brushless direct current (BLDC) motor and planar multilayer multiple coils. These were fabricated using low temperature co-fired ceramics (LTCC) technology. In our experiment, six rectifying circuits were simulated and tested with a structure consisting of eight layers of coils and with an outer diameter of 50 mm fabricated earlier. Findings The microgenerator with Graetz bridge generates higher output power than the modified charge pump at the same rotary speed. However, it is less stable for the distance change between the structure and the magnets than the modified charge pump, which has more constant output power in a wider range of load resistance. Originality/value The presented electronic rectifying circuits are novel for LTCC-based electromagnetic microgenerator application. The structure with integrated rectifying circuits allows generation of electrical output power larger than 100 mW at the rotor speed of about 8,000 rpm.

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11

Singh, Vimlesh, Priyanka Bansal, and P. K.Singhal. "Microstrip line Antenna Fabrication Material." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 340. http://dx.doi.org/10.14419/ijet.v7i2.8.10437.

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This paper presents an extensive survey of electromagnetic materials used for antenna fabrication, which find application in Civilian life as well as defense life. When a densely packed microwave integrated circuit is designed, it requires protection from higher power transient because of specific polarization and frequency response. To meet specification of such kind of microwave circuits it is desired to exploit properties of fabricating materials, which are not found in nature but can be prepared with specific proportion of chemical element combination. This study provides in-depth responses of materials toward electromagnetic wave's characteristics such as dielectric, flexible electronics, electrical and thermal properties, which have vast potential in communication engineering.

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12

Ting, Chiu H., and M. Paunovic. "Selective Electroless Metal Deposition for Integrated Circuit Fabrication." Journal of The Electrochemical Society 136, no. 2 (February 1, 1989): 456–62. http://dx.doi.org/10.1149/1.2096654.

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13

Harrold, S. J. "Book Review: Integrated Circuit Design, Fabrication and Test." International Journal of Electrical Engineering Education 35, no. 2 (April 1998): 188–89. http://dx.doi.org/10.1177/002072099803500210.

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14

Godfrey, D. J. "Modelling physical processes in silicon integrated circuit fabrication." Physics in Technology 17, no. 6 (November 1986): 260–64. http://dx.doi.org/10.1088/0305-4624/17/6/i03.

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15

Wang, Shou-guo, and Ching-yuen Chan. "Fabrication of integrated resistors in printed circuit boards." Journal of Central South University 18, no. 3 (June 2011): 739–43. http://dx.doi.org/10.1007/s11771-011-0756-9.

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16

del Alamo, Jesús A. "GaAs Integrated Circuit Manufacturing." MRS Bulletin 17, no. 4 (April 1992): 42–44. http://dx.doi.org/10.1557/s0883769400041063.

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In the mid 1980s, reports of exciting progress from GaAs integrated circuit (IC) performance from R&D laboratories world-wide portrayed a rosy future for GaAs. Now, in the early 1990s, true to their reputation, GaAs ICs are still largely the stuff of the future. In fact, deployment of GaAs ICs in real systems has been disappointingly slow. In 1985, the commercial GaAs IC market was forecast to reach $800 million by 1990. The actual figure was only $142 million. To put this number in perspective, it represents less than 0.4% of the total Si IC merchant market.In a recent survey of the GaAs industry, Kato explored the causes for GaAs troubles, with startling findings. The issue certainly does not seem to be a performance one because GaAs ICs are sufficiently ahead of alternative technologies. Material quality is not a problem either. Extremely high-quality 3 in. and 4 in. GaAs wafers are now on the market at reasonable prices. On the other hand, several serious deficiencies center around IC manufacturing. The price of the final GaAs ICs is perceived as not competitive with alternative technologies. This is rooted in the low yields and poor repeatability of the manufacturing lines. A great contribution to cost is time-consuming functionality testing, particularly for analog products. For MMICs (monolithic microwave integrated circuits) in particular, final testing can easily become the bottleneck of the entire fabrication process. There is also much uncertainty about reliability. This might explain to a large extent the low customer confidence in the technology. Kato reports that fundamental technical problems in making GaAs ICs are still believed to remain.

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17

Amelian, Atieh, and Shahram Etemadi Borujeni. "A Side-Channel Analysis for Hardware Trojan Detection Based on Path Delay Measurement." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850138. http://dx.doi.org/10.1142/s0218126618501384.

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Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01[Formula: see text]ns can detect more than 80% of Trojans.

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18

Joshi, R. V., R. S. Blewer, and S. Murarka. "Metallization for Integrated Circuit Manufacturing." MRS Bulletin 20, no. 11 (November 1995): 33–37. http://dx.doi.org/10.1557/s088376940004553x.

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This issue of the MRS Bulletin focuses on current interconnect metallurgies practiced in the manufacturing of integrated circuits (ICs). The issue should serve as a reference for researchers, scientists, engineers, and those who are not familiar with the IC arena.Al-metallization requires special attention due to its wide usage in logic and memory circuits. Logic requirements drive technology toward improved circuit performance while memory improvements require high device and wiring densities. As the dynamic random access memory (DRAM) evolves from 64 Mbits to 256 Mbits, ultralarge-scale integrated (ULSI) wiring will decrease to below sub-0.3 μm in dimensions. Such circuits require robust, reliable back end of the line (BEOL) technology that meets high-performance, low-cost, stringent electromigration requirements. We feel that several of these emerging interconnect fabrication techniques have reached a sufficient level of maturity to warrant a reasonable exposition. We will concentrate on metallization systems in this issue, leaving a discussion of dielectrics for the future, due to space limitations.The semiconductor industry has relied on aluminum technology since the 1960s because it is a well-established, low-cost technology. Early improvements in the electromigration resistance of Al lines by the addition of Cu impurities after 1971 helped this metallurgy to endure further feature size reductions, without degradation of reliability. However, the relentless reduction in via and line size once again may bring into question the limitation of Al reliability. As a result, work on alternate low-resistivity and high-electromigration-resistant metals like Cu is continuing in parallel.

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19

Colinge, Jean-Pierre, and Robert W. Bower. "Silicon-on-lnsulator Technology." MRS Bulletin 23, no. 12 (December 1998): 13–15. http://dx.doi.org/10.1557/s0883769400029766.

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Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.

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20

Yohannes, D., A. Kirichenko, S. Sarwana, and S. K. Tolpygo. "Parametric Testing of HYPRES Superconducting Integrated Circuit Fabrication Processes." IEEE Transactions on Applied Superconductivity 17, no. 2 (June 2007): 181–86. http://dx.doi.org/10.1109/tasc.2007.897399.

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21

Ligtenberg, Allart. "Advantages of Facilities Monitoring System in Integrated Circuit Fabrication." Journal of the IEST 29, no. 6 (November 1, 1986): 41–45. http://dx.doi.org/10.17764/jiet.1.29.6.n76778t00p364777.

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This paper discusses a computerized Facilities Monitor and Control System, which has been in use for several years at Hewlett Packard's Cupertino Integrated Circuit Division. Over 350 transducers monitor the IC fabrication support systems such as deionized (DI) water, process gases, process environment, cleanroom equipment and environment, as well as systems which ensure industrial hygiene, safety and environmental compliance. Examples illustrate how the Facilities Monitor System information has been used to improve yield, diagnose process control problems, prevent contamination and improve the facilities, resulting in significant cost savings. This is accomplished by continuous real-time monitoring, historical data acquisition and analysis, trendlining, correlation studies and various levels of alarm notification.

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22

Yamakawa, Takeshi, and Hideyuki Kabuo. "A programmable fuzzifier integrated circuit—synthesis, design, and fabrication." Information Sciences 45, no. 2 (July 1988): 75–112. http://dx.doi.org/10.1016/0020-0255(88)90035-7.

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23

Wong, C. P. "An Overview of Integrated Circuit Device Encapsulants." Journal of Electronic Packaging 111, no. 2 (June 1, 1989): 97–107. http://dx.doi.org/10.1115/1.3226528.

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The rapid development of integrated circuit technology from small-scale integration (SSI) to very large scale integration (VLSI) has had great technological and economical impact on the electronics industry. The exponential growth of the number of components per IC chip, the exponential decrease of device dimensions, and the steady increase in IC chip size have imposed stringent requirements, not only on the IC physical design and fabrication, but also on IC encapsulants. This report addresses the purpose of encapsulation, encapsulation techniques, and a general overview of the application of inorganic and organic polymer materials as electronic device encapsulants.

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24

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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25

AGARWAL, BIPUL, RAJASEKHAR PULLELA, UDDALAK BHATTACHARYA, DINO MENSA, QING-HUNG LEE, LORENE SAMOSKA, JAMES GUTHRIE, and MARK RODWELL. "ULTRAHIGH fmax AlInAs/GaInAs TRANSFERRED-SUBSTRATE HETEROJUNCTION BIPOLAR TRANSISTORS FOR INTEGRATED CIRCUITS APPLICATIONS." International Journal of High Speed Electronics and Systems 09, no. 02 (June 1998): 643–70. http://dx.doi.org/10.1142/s0129156498000270.

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Transferred-substrate heterojunction bipolar transistors (HBTs) have demonstrated very high bandwidths and are potential candidates for very high speed integrated circuit (IC) applications. The transferred-substrate process permits fabrication of narrow and aligned emitter-base and collector-base junctions, reducing the collector-base capacitance and increasing the device f max . Unlike conventional double-mesa HBTs, transferred-substrate HBTs can be scaled to submicron dimensions with a consequent increase in bandwidth. This paper introduces the concept of transferred-substrate HBTs. Fabrication process in the AlInAs/GaInAs material system is presented, followed by DC and RF performance. A demonstration IC is shown along with some integrated circuits in development.

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26

KUMAR, RANJITH, ZHIYU LIU, and VOLKAN KURSUN. "TECHNIQUE FOR ACCURATE POWER AND ENERGY MEASUREMENT WITH THE COMPUTER-AIDED DESIGN TOOLS." Journal of Circuits, Systems and Computers 17, no. 03 (June 2008): 399–421. http://dx.doi.org/10.1142/s0218126608004381.

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Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented. The research community tends to assume that the built-in functions provide accurate power figures. This blind-trust in the CAD tools, however, may lead to gross errors in power estimation. A generic methodology to accurately measure the power and energy consumption with the circuit simulators is described in this paper. An equation to calculate the device power consumption based on the different current conduction paths in a MOSFET is presented. An expression for the total power consumption of a complex circuit is derived by explicitly considering the different circuit terminals including the inputs, the outputs, and the body-contacts. Results indicate that the power measurements with the built-in functions of widely used commercial circuit simulators can introduce significant errors in a 65 nm CMOS technology. For deeply scaled nano-CMOS circuits, a conscious power and energy measurement with the proposed explicit methodology is recommended for an accurate pre-fabrication circuit characterization.

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27

Lee, El Hang, In Joo Chin, Yong Ku Kwon, S. G. Lee, B. H. O, S. G. Park, and Kyong Hon Kim. "Synthesis and Fabrication of Novel Polymeric/Organic Materials for Micro/Nano-Scale Optical Printed Circuit Board and VLSI Photonic Integrated Circuit Application." Solid State Phenomena 124-126 (June 2007): 459–62. http://dx.doi.org/10.4028/www.scientific.net/ssp.124-126.459.

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We report on the synthesis and fabrication of novel polymer/organic materials for application for what we call optical printed circuit board (O-PCB) for VLSI photonic circuit (VLSI-PIC). We synthesize copolymers containing cross-linkable pendant groups suitable for embossing and novel device fabrication. We also synthesize organic-inorganic hybrid materials of low optical absorption, good adhesion, low dielectric constant, high dielectric strength, high thermal stability, excellent photo-patterning possibility and variability of refractive index. Steps of synthesis and fabrication of these materials are described along with their optical, material, and performance characteristics. O-PCB and VLSI photonic circuit design and fabrication processes are also presented.

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28

Gutierrez, Cassie, Rudy Salas, Gustavo Hernandez, Dan Muse, Richard Olivas, Eric MacDonald, Michael D. Irwin, et al. "CubeSat Fabrication through Additive Manufacturing and Micro-Dispensing." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 001021–27. http://dx.doi.org/10.4071/isom-2011-tha4-paper3.

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Fabricating entire systems with both electrical and mechanical content through on-demand 3D printing is the future for high value manufacturing. In this new paradigm, conformal and complex shapes with a diversity of materials in spatial gradients can be built layer-by-layer using hybrid Additive Manufacturing (AM). A design can be conceived in Computer Aided Design (CAD) and printed on-demand. This new integrated approach enables the fabrication of sophisticated electronics in mechanical structures by avoiding the restrictions of traditional fabrication techniques, which result in stiff, two dimensional printed circuit boards (PCB) fabricated using many disparate and wasteful processes. The integration of Additive Manufacturing (AM) combined with Direct Print (DP) micro-dispensing and robotic pick-and-place for component placement can 1) provide the capability to print-on-demand fabrication, 2) enable the use of micron-resolution cavities for press fitting electronic components and 3) integrate conductive traces for electrical interconnect between components. The fabrication freedom introduced by AM techniques such as stereolithography (SL), ultrasonic consolidation (UC), and fused deposition modeling (FDM) have only recently been explored in the context of electronics integration and 3D packaging. This paper describes a process that provides a novel approach for the fabrication of stiff conformal structures with integrated electronics and describes a prototype demonstration: a volumetrically-efficient sensor and microcontroller subsystem scheduled to launch in a CubeSat designed with the CubeFlow methodology.

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29

Hirakuri, Kenji K., Masayuki Yoshimura, and Gernot Friedbacher. "Application of DLC films as masks for integrated circuit fabrication." Diamond and Related Materials 12, no. 3-7 (March 2003): 1013–17. http://dx.doi.org/10.1016/s0925-9635(02)00379-5.

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30

Maezawa, Masaaki, Liliang Ying, Sucheta Gorwadkar, Guofeng Zhang, Hai Wang, Xiangyan Kong, Zhen Wang, and Xiaoming Xie. "Fabrication of Planar Gradiometers by Using Superconducting Integrated Circuit Technology." Physics Procedia 65 (2015): 173–76. http://dx.doi.org/10.1016/j.phpro.2015.05.103.

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31

Marathe, A. P., F. Ludwig, T. Van Duzer, and L. Lee. "Process issues and components for HTS digital integrated circuit fabrication." IEEE Transactions on Appiled Superconductivity 5, no. 2 (June 1995): 3135–38. http://dx.doi.org/10.1109/77.403256.

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32

Stiffler, S. R. "Oxidation‐induced substrate strain in advanced silicon integrated‐circuit fabrication." Journal of Applied Physics 68, no. 1 (July 1990): 351–55. http://dx.doi.org/10.1063/1.347141.

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33

Friedman, D. J., M. H. Hansen, V. N. Nair, and D. A. James. "Model-free estimation of defect clustering in integrated circuit fabrication." IEEE Transactions on Semiconductor Manufacturing 10, no. 3 (1997): 344–59. http://dx.doi.org/10.1109/66.618208.

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34

Franco, Emilio, Francisco Perdigones, Blas Salvador, and José Manuel Quero. "Bonding process using integrated electrothermal actuators for microfluidic circuit fabrication." Journal of Micromechanics and Microengineering 28, no. 7 (April 17, 2018): 075006. http://dx.doi.org/10.1088/1361-6439/aababb.

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35

Pierrat, C. "Dry etched molybdenum silicide photomasks for submicron integrated circuit fabrication." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 9, no. 6 (November 1991): 3132. http://dx.doi.org/10.1116/1.585326.

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36

Dayhoff, Judith, and Robert Atherton. "A Model for Wafer Fabrication Dynamics in Integrated Circuit Manufacturing." IEEE Transactions on Systems, Man, and Cybernetics 17, no. 1 (January 1987): 91–100. http://dx.doi.org/10.1109/tsmc.1987.289336.

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37

Pico, Carey A., Michael A. Lieberman, and Nathan W. Cheung. "PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation." Journal of Electronic Materials 21, no. 1 (January 1992): 75–79. http://dx.doi.org/10.1007/bf02670923.

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38

Kota, S., G. K. Ananthasuresh, S. B. Crary, and K. D. Wise. "Design and Fabrication of Microelectromechanical Systems." Journal of Mechanical Design 116, no. 4 (December 1, 1994): 1081–88. http://dx.doi.org/10.1115/1.2919490.

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An attempt has been made to summarize some of the important developments in the emerging technology of microelectromechanical systems (MEMS) from the mechanical engineering perspective. In the micro domain, design and fabrication issues are very much different from those of the macro world. The reason for this is twofold. First, the limitations of the micromachining techniques give way to new exigencies that are nonexistent in the macromachinery. One such difficulty is the virtual loss of the third dimension, since most of the microstructures are fabricated by integrated circuit based micromachining techniques that are predominantly planar. Second, the batch-produced micro structures that require no further assembly, offer significant economical advantage over their macro counterparts. Furthermore, electronic circuits and sensors can be integrated with micromechanical structures. In order to best utilize these features, it becomes necessary to establish new concepts for the design of MEMS. Alternate physical forms of the conventional joints are considered to improve the manufacturability of micromechanisms and the idea of using compliant mechanisms for micromechanical applications is put forth. The paper also reviews some of the fabrication techniques and the micromechanical devices that have already been made. In particular, it discusses the fabrication of a motor-driven four-bar linkage using the “boron-doped bulk-silicon dissolved-wafer process” developed at The University of Michigan’s Center for Integrated Sensors and Circuits.

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39

Weikle, R. M., T. W. Crowe, and E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications." International Journal of High Speed Electronics and Systems 13, no. 02 (June 2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.

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Harmonic generation based on frequency multipliers has proven to be the most successful and widely used solid-state technology for generating power at submillimeter wavelengths. Over the last several years, the development of new device technologies, implementation of innovative circuits, and application of advanced integrated-circuit processing techniques to frequency multiplier design have resulted in unprecedented levels of performance throughout the submillimeter-wave frequency band. This paper reviews the technological innovations, device options, circuit architectures, and fabrication technologies that have made harmonic generation such a successful approach to source development in the submillimeter spectrum.

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40

Iwai, Hiroshi, Kuniyuki Kakushima, and Hei Wong. "CHALLENGES FOR FUTURE SEMICONDUCTOR MANUFACTURING." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 43–81. http://dx.doi.org/10.1142/s0129156406003539.

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The downsizing of CMOS devices has been accelerated very aggressively in both production and research in recent years. Sub-100 nm gate length CMOS large-scale integrated circuits (LSIs) have been used for many applications and five nanometer gate length MOS transistor was even reported. However, many serious problems emerged when such small geometry MOSFETs are used to realize a large-scale integrated circuit. Even at the 'commercial 45 nm (HP65nm) technology node', the skyrocketing rise of the production cost becomes the greatest concern for maintaining the downsizing trend towards 10 nm. In this paper, future semiconductor manufacturing challenges for nano-sized devices and ultra large scale circuits are analyzed. The portraits of future integration circuit fabrication and the distribution of semiconductor manufacturing centers in next decade are sketched. The possible limits for the scaling will also be elaborated.

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Rathore, Pradeep Kumar, Brishbhan Singh Panwar, and Jamil Akhtar. "A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique." Microelectronics International 32, no. 2 (May 5, 2015): 81–95. http://dx.doi.org/10.1108/mi-11-2014-0048.

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Purpose – The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors. Design/methodology/approach – This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge. Findings – The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits. Originality/value – The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

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Spry, David J., Philip G. Neudeck, Liang-Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim, Michael J. Krasowski, and Norman F. Prokop. "Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (January 1, 2016): 000249–56. http://dx.doi.org/10.4071/2016-hitec-249.

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Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

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Zhang, Chuang, Chang-Ling Zou, Yan Zhao, Chun-Hua Dong, Cong Wei, Hanlin Wang, Yunqi Liu, Guang-Can Guo, Jiannian Yao, and Yong Sheng Zhao. "Organic printed photonics: From microring lasers to integrated circuits." Science Advances 1, no. 8 (September 2015): e1500257. http://dx.doi.org/10.1126/sciadv.1500257.

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A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

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Xu, D., R. F. Pinizzotto, and J. A. Sees. "Sub-part-per-trillion detection and analysis of submicrometer particles in integrated circuit processing chemicals." Journal of Materials Research 13, no. 3 (March 1998): 717–25. http://dx.doi.org/10.1557/jmr.1998.0090.

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We have developed a new technique for the analysis of particulate contaminants in liquids (or gases) with an elemental detectability limit as low as 0.1 parts per trillion, and a particle concentration detectability limit as low as 1 particle/ml for particles greater than 0.2 μm in diameter. Samples are prepared using extraction replication and analyzed using analytical transmission electron microscopy. The methodology has been applied to the analysis of H2O2 and HF, important chemicals in integrated circuit fabrication. The new methodology should become an important tool in the identification of submicron-sized particles which adversely affect integrated circuit fabrication.

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Abecassis, Úrsula, Davies de Lima Monteiro, Luciana Salles, Carlos de Moraes Cruz, and Pablo Agra Belmonte. "Impact of CMOS Pixel and Electronic Circuitry in the Performance of a Hartmann-Shack Wavefront Sensor." Sensors 18, no. 10 (September 29, 2018): 3282. http://dx.doi.org/10.3390/s18103282.

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This work presents a numerical simulation of a Hartmann-Shack wavefront sensor (WFS) that assesses the impact of integrated electronic circuitry on the sensor performance, by evaluating a full detection chain encompassing wavefront sampling, photodetection, electronic circuitry and wavefront reconstruction. This platform links dedicated C algorithms for WFS to a SPICE circuit simulator for integrated electronics. The complete codes can be easily replaced in order to represent different detection or reconstruction methods, while the circuit simulator employs reliable models of either off-the-shelf circuit components or custom integrated circuit modules. The most relevant role of this platform is to enable the evaluation of the applicability and constraints of the focal plane of a given wavefront sensor prior to the actual fabrication of the detector chip. In this paper, we will present the simulation results for a Hartmann-Shack wavefront sensor with an orthogonal array of quad-cells (QC) integrated along with active-pixel (active-pixel sensor (APS)) circuitry and analog-to-digital converters (ADC) on a “complementary metal oxide semiconductor” (CMOS) process and deploying a modal wavefront reconstructor. This extended simulation capability for wavefront sensors enables the test and verification of different photosensitive and circuitry topologies for position-sensitive detectors combined with the simulation of sampling microlenses and reconstruction algorithms, with the goal of enhancing the accuracy in the prediction of the wavefront-sensor performance before a detector CMOS chip is actually fabricated.

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Kim, Bruce C., Sai Evana, and Rahim Kasim. "Packaging of MEMS for Integrated RF Circuit Verifications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 000926–51. http://dx.doi.org/10.4071/2011dpc-tp24.

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This paper provides development of MEMS switches and packaging of MEMS to test radio frequency circuits used in wireless products such as cell phones and network routers. We discuss fabrication of MEMS using low voltage magnetic materials and their configurations to achieve the optimum switch to test RF low noise amplifiers. We have accomplished a very unique methodology to test low noise amplifiers using built-in sellf-test technique and our MEMS switches are proposed to achieve the verification of low noise amplifiers. Furthermore, we have used MEMS switches that we developed to perform self calibration to correct for the parametric variations and faults within the deep submicron CMOS circuits. We also discuss packaging of MEMS and low noise amplifier using 3D TSV technology.

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Kazior, Thomas E. "Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 372, no. 2012 (March 28, 2014): 20130105. http://dx.doi.org/10.1098/rsta.2013.0105.

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Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

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Fan, Dejiu, Byungjun Lee, Caleb Coburn, and Stephen R. Forrest. "From 2D to 3D: Strain- and elongation-free topological transformations of optoelectronic circuits." Proceedings of the National Academy of Sciences 116, no. 10 (February 12, 2019): 3968–73. http://dx.doi.org/10.1073/pnas.1813001116.

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Optoelectronic circuits in 3D shapes with large deformations can offer additional functionalities inaccessible to conventional planar electronics based on 2D geometries constrained by conventional photolithographic patterning processes. A light-sensing focal plane array (FPA) used in imagers is one example of a system that can benefit from fabrication on curved surfaces. By mimicking the hemispherical shape of the retina in the human eye, a hemispherical FPA provides a low-aberration image with a wide field of view. Due to the inherently high value of such applications, intensive efforts have been devoted to solving the problem of transforming a circuit fabricated on a flat wafer surface to an arbitrary shape without loss of performance or distorting the linear layouts that are the natural product of this fabrication paradigm. Here we report a general approach for fabricating electronic circuits and optoelectronic devices on nondevelopable surfaces by introducing shear slip of thin-film circuit components relative to the distorting substrate. In particular, we demonstrate retina-like imagers that allow for a topological transformation from a plane to a hemisphere without changing the relative positions of the pixels from that initially laid out on a planar surface. As a result, the resolution of the imager, particularly in the foveal region, is not compromised by stretching or creasing that inevitably results in transforming a 2D plane into a 3D geometry. The demonstration provides a general strategy for realizing high-density integrated circuits on randomly shaped, nondevelopable surfaces.

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Amirnudin, Amirul Adlan, Farahiyah Mustafa, Anis Maisarah Mohd Asry, and Sy Yi Sim. "Vibration Based Energy Harvesting Interface Circuit using Diode-Capacitor Topologies for Low Power Applications." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 4 (December 1, 2017): 1943. http://dx.doi.org/10.11591/ijpeds.v8.i4.pp1943-1947.

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<span>A battery-less energy harvesting interface circuit to extract electrical energy from vibration has been proposed in this paper for low power applications. The voltage doubler integrated with DC – DC boost converter circuits were designed and simulated using MultiSIM software. The circuit was then fabricated onto a printed circuit board (PCB), using standard fabrication process. The Cockcroft Walton doubler was chosen to be implemented in this study by utilizing diode-capacitor topologies with additional RC low pass filter. The DC – DC boost converter has been designed using a CMOS step -up DC – DC switching regulators, which are suitable for low input voltage system. The achievement of this interface circuit was able to boost up the maximum voltage of 5 V for input voltage of 800 mV.</span>

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Min, Chul Hong, and Tae Seon Kim. "Design and Fabrication of Printed Circuit Board (PCB) Integrated Energy Harvester." Journal of the Korean Institute of Electrical and Electronic Material Engineers 26, no. 11 (November 1, 2013): 846–51. http://dx.doi.org/10.4313/jkem.2013.26.11.846.

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