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Relevant bibliographies by topics / Integrated circuit layout

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Academic literature on the topic 'Integrated circuit layout'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 August 2024

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Journal articles on the topic "Integrated circuit layout"

1

Wei, Yiding, Jun Liu, Dengbao Sun, Guodong Su, and Junchao Wang. "From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits." Symmetry 15, no. 6 (June 16, 2023): 1272. http://dx.doi.org/10.3390/sym15061272.

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Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.

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Kasprowicz, Dominik, and Maria Hayder. "Net-Shape-Based Automated Detection of Integrated-Circuit Layout Plagiarism." Electronics 10, no. 24 (December 20, 2021): 3181. http://dx.doi.org/10.3390/electronics10243181.

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Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in industry. A procedure was proposed that compares IC layouts based on the physical representation of particular electrical nets, i.e., on the shape of the features drawn on conducting layers (metals and polysilicon). At the heart of this method is the Needleman–Wunsch algorithm, used for decades in tools aligning sequences of amino acids or nucleotides. Here, it is used to quantify the visual similarity of nets within the pair of layouts being compared. The method was implemented in Python and successfully used to identify clusters of similar layouts within two pools of designs: one composed of logic gates and one containing operational transconductance amplifiers.

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Indrusiak, Leandro Soares, and Ricardo Augusto da Luz Reis. "3D integrated circuit layout visualization using VRML." Future Generation Computer Systems 17, no. 5 (March 2001): 503–11. http://dx.doi.org/10.1016/s0167-739x(00)00036-4.

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Maris Ferreira, Pietro, Emilie Avignon-Meseldzija, Philippe Bénabès, and Francis Trélin. "Surface versus Performance Trade-offs: A Review of Layout Techniques." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–16. http://dx.doi.org/10.29292/jics.v17i1.589.

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Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.

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Vania Agata and Rr. Aline Gratika Nugrahani. "HAK DESAIN TATA LETAK SIRKUIT TERPADU PADA IMPLEMENTASI ALGORITMA ENKRIPSI BC3 DI INDONESIA." Reformasi Hukum Trisakti 6, no. 2 (May 17, 2024): 703–14. http://dx.doi.org/10.25105/refor.v6i2.19719.

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Integrated circuit layout design (DTLST) is one of the relatively new forms of intellectual property, especially in the context of Industrial Property Rights. Law No. 32 of 2000 regulates the layout design of integrated circuits. The first DTLST certificate was granted by DJKI Kemenkhumham in 2018 with certificate number IDL000000001 to Dr. Eng. Sarwono Sutikno and team. The problem formulation in this article is how the legal protection process of Layout Design of BC3 Encryption Algorithm Implementation on Hardware with DTLST Number IDL000000001 according to Law No. 32 of 2000 concerning DTLST and whether that design has qualified as an Integrated Circuit Layout Design. The research uses normative legal research methods, with secondary and primary data. Based on the results of the study, the Layout Design of BC3 Encryption Algorithm Implementation on Hardware has protection for 10 years since October 30th, 2018, where the protection is obtained from the date of acceptance because no commercial exploitation is carried out. The conclusion is that The Layout Design of BC3 Encryption Algorithm Implementation on Hardware is a work that has passed the checking process by DJKI, where this design has passed and meets the originality requirements.

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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.

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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.

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Fourie, Coenrad J., and Kyle Jackman. "High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout." Journal of Physics: Conference Series 2323, no. 1 (August 1, 2022): 012034. http://dx.doi.org/10.1088/1742-6596/2323/1/012034.

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Abstract Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

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Gusmão, António, Pedro Alves, Nuno Horta, Nuno Lourenço, and Ricardo Martins. "Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization." Electronics 12, no. 1 (December 27, 2022): 110. http://dx.doi.org/10.3390/electronics12010110.

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Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an “optimal” floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization processes with several constraints; or placement retargeting from legacy designs/templates, which rely heavily on legacy layout data. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover the different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, proximity, and symmetry island constraints are formulated for the first time in the literature, and an unsupervised loss function is used for the artificial neural network model to learn how to generate placements that follow them. The use of a deep learning model makes push-button speed placement generation possible, additionally, as only sizing data are required for its training, it discards the need to acquire legacy layouts containing insights into this vast set of, often neglected, constraints. The model is ultimately used to produce floorplans from scratch at push-button speed for real state-of-the-art analog structures, including technology nodes not used for training. A case-study comparison with a floorplan design made by a human-expert presents improvements in the fulfillment of every constraint, reaching an overall improvement of around 70%, demonstrating the approach’s value in placement design.

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Русанов, А. В., Л. В. Сопина, and А. В. Бунина. "BANDGAP REFERENCE VOLTAGE SOURCE FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 19, no. 4 (September 7, 2023): 71–76. http://dx.doi.org/10.36622/vstu.2023.19.4.009.

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предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключевую роль, сравнивая опорное напряжение с выходным (или частью выходного) напряжением, и управляет проходным элементом для обеспечения этого равенства. Представлены описание электрических схем усилителей, основные электрические характеристики, результаты моделирования, указаны особенности разработки топологии интегральной схемы. ОУ разработаны на базе отечественного технологического процесса с проектными нормами 3 мкм. Разработка схемы и топологии проводилась в специализированной системе автоматизированного проектирования интегральных схем. Для моделирования схемы использовались сертифицированные математические модели полупроводниковых приборов. Разработанные топологии ОУ прошли верификацию, состоящую из проверки соблюдения проектных норм (Design rule check, DRC), восстановления электрической схемы из топологии и сравнения топологии с исходной схемой (Layout vs Schematic, LVS) the article proposes two IP blocks of operational amplifiers (op-amps) built on n-channel and p-channel differential pairs. Op-amps are universal blocks on the basis of which you can build many different electronic devices. Currently, op amps are widely used, both in the form of individual chips and as IP blocks as part of more complex integrated circuits. The developed IP blocks are intended for use in integrated circuits of linear voltage stabilizers as error amplifiers. In voltage regulators, the error amplifier plays a key role by comparing the reference voltage to the output (or part of the output voltage) voltage and drives the pass element to ensure this equality. The description of the electrical circuits of amplifiers, the main electrical characteristics, the results of modeling are presented, the features of the development of the integrated circuit topology are indicated. The op amps are developed on the basis of the domestic BiCMOS technological process with design standards of 3 µm. The development of the scheme and topology was carried out in a specialized system for automated design of integrated circuits. To model the circuit, certified mathematical models of semiconductor devices were used. The developed layouts of the op-amp have passed verification, consisting of checking compliance with design standards (Design rule check, DRC), restoring the electrical circuit from the layout and comparing the layout with the original circuit (Layout vs Schematic, LVS)

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Qiu, Tian. "Application and possibility of machine learning in integrated circuit design." Applied and Computational Engineering 6, no. 1 (June 14, 2023): 60–66. http://dx.doi.org/10.54254/2755-2721/6/20230457.

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Artificial Intelligence has had an impact on the field of integrated circuits. Artificial Intelligence technology is gradually replacing the traditional methodology of implementing Integrated Circuit tasks, which consumes a lot of time, funding, and labor. Traditionally, electronic products, like chips, which consist of a large number of circuits, were very slow and costly to process, because it was done by humans. The engineers have to design the layout, carry out operations, verify, and test the circuits, and this is actually extremely inefficient and expensive. However, with the help of Artificial Intelligence technology, efficiency can be greatly improved. The algorithms of Artificial Intelligence to a large extent, accelerated the process of designing, detecting, and maintaining the Integrated Circuit. Nowadays, many companies are applying Artificial Intelligence to upgrade their own products. Machine Learning is one of the main branches of Artificial Intelligence, and its powerfulness has provided a lot of help in the Integrated Circuit tasks. This paper discussed and analyzed the application and possibility of machine learning specifically in Integrated Circuit design activities through literature review and data research.

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Dissertations / Theses on the topic "Integrated circuit layout"

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Harter, Andrew Charles. "Three-dimensional integrated circuit layout." Thesis, University of Cambridge, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.335724.

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Griffin, Glenn. "Intelligent circuit recognition for VLSI layout verification." Master's thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-04272010-020102/.

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Paroski, Andrew John. "Deform a new approach for redistributing placements /." Diss., Online access via UMI:, 2006.

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Rutherford, William C. "Gallium arsenide integrated circuit modeling, layout and fabrication." Thesis, University of British Columbia, 1987. http://hdl.handle.net/2429/26733.

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The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.

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Chowdhury, M. Foysol. "An expert system for analogue integrated circuit layout design." Thesis, University of Essex, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.303493.

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Kim, Kwanghyun. "An interactive design rule checker for integrated circuit layout." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/50034.

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An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed.
Master of Science
incomplete_metadata

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Zhang, Xibo. "RF integrated circuit design options : from technology to layout /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20ZHANG.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 59-61). Also available in electronic version. Access restricted to campus users.

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Liesenberg, H. K. E. "A layout module for a silicon compiler." Thesis, University of Newcastle Upon Tyne, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.353769.

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Robinson, Jayne Helen. "Artifical intelligence applied to MMIC layout." Thesis, Queen's University Belfast, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295424.

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Books on the topic "Integrated circuit layout"

1

Harter, Andrew. Three-dimensional integrated circuit layout. Cambridge: Cambridge University Press, 1991.

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Harter, Andrew. Three-dimensional integrated circuit layout. Cambridge: Cambridge University Press, 2009.

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inc, Motorola, ed. Introduction to integrated-circuit layout. Englewood Cliffs, NJ: Prentice-Hall, 1985.

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Lengauer, T. Combinatorial algorithms for integrated circuit layout. Stuttgart: B.G. Teubner, 1990.

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Lengauer, Thomas. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2.

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Lengauer, Thomas. Combinatorial algorithms for integrated circuit layout. Chichester: Wiley, 1990.

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Hsu, Chi-Ping. Signal routing in integrated circuit layout. Ann Arbor, Mich: UMI Research Press, 1986.

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Lengauer, T. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1992.

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Lin, Chieh. Mixed-signal layout generation concepts. Boston, MA: Kluwer Academic Publishers, 2004.

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Lin, Chieh. Mixed-signal layout generation concepts. Boston: Kluwer Academic Publishers, 2003.

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Book chapters on the topic "Integrated circuit layout"

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Lengauer, Thomas. "Circuit Partitioning." In Combinatorial Algorithms for Integrated Circuit Layout, 251–301. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_6.

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Lengauer, Thomas. "Introduction to Circuit Layout." In Combinatorial Algorithms for Integrated Circuit Layout, 3–29. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_1.

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Tehranipoor, Mohammad, Hassan Salmani, and Xuehui Zhang. "Design for Hardware Trust: Layout-Aware Scan Cell Reordering." In Integrated Circuit Authentication, 69–90. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00816-5_5.

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Lengauer, Thomas. "The Layout Problem." In Combinatorial Algorithms for Integrated Circuit Layout, 221–50. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_5.

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Morant, M. J. "Full-custom Circuit and Layout Design." In Integrated Circuit Design and Technology, 143–60. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4899-7198-2_9.

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Lengauer, Thomas. "Compaction." In Combinatorial Algorithms for Integrated Circuit Layout, 579–647. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_10.

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Lengauer, Thomas. "Optimization Problems." In Combinatorial Algorithms for Integrated Circuit Layout, 31–45. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_2.

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Lengauer, Thomas. "Graph Algorithms." In Combinatorial Algorithms for Integrated Circuit Layout, 47–135. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_3.

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Lengauer, Thomas. "Operations Research and Statistics." In Combinatorial Algorithms for Integrated Circuit Layout, 137–217. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_4.

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Lengauer, Thomas. "Placement, Assignment, and Floorplanning." In Combinatorial Algorithms for Integrated Circuit Layout, 303–77. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2_7.

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Conference papers on the topic "Integrated circuit layout"

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Chari, K. S., and Manoj Sharma. "Integrated circuit layout design screening." In 2013 IEEE Conference on Information & Communication Technologies (ICT). IEEE, 2013. http://dx.doi.org/10.1109/cict.2013.6558303.

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Roberts, Rebecca M. C., and Coenrad J. Fourie. "Layout-to-schematic as a step towards layout-versus-schematic verification of SFQ integrated circuit layouts." In AFRICON 2013. IEEE, 2013. http://dx.doi.org/10.1109/afrcon.2013.6757839.

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Singh, Rama, Matt Ziegler, Gary Ditlow, Fook-Luen Heng, Jin-Fuw Lee, and Mark Lavin. "Layout-aware through-process circuit analysis." In 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era. IEEE, 2007. http://dx.doi.org/10.1109/dtis.2007.4449514.

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Liu, H. C. H., and M. Soma. "Fault diagnosis for analog integrated circuits based on the circuit layout." In Proceedings Pacific Rim International Symposium on Fault Tolerant Systems. IEEE, 1991. http://dx.doi.org/10.1109/rfts.1991.212953.

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Pikus, Fedor G., and J. Andres Torres. "Non-uniform yield optimization for integrated circuit layout." In 27th Annual BACUS Symposium on Photomask Technology, edited by Robert J. Naber and Hiroichi Kawahira. SPIE, 2007. http://dx.doi.org/10.1117/12.746722.

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Lemko, I. V., Ya V. Belyaev, D. V. Kostygov, N. N. Nevirkovets, Yu A. Andryakov, and A. A. Mikhteeva. "Integrated circuit layout design for a micromechanical accelerometer." In 2017 24th Saint Petersburg International Conference on Integrated Navigation Systems (ICINS). IEEE, 2017. http://dx.doi.org/10.23919/icins.2017.7995648.

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Feinerman, Oron, Mor Sofer, and Elishai Ezra Tsur. "Computer-Aided Design of Valves-Integrated Microfluidic Layouts Using Parameter-Guided Electrical Models." In ASME 2018 5th Joint US-European Fluids Engineering Division Summer Meeting. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/fedsm2018-83362.

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Integrated microfluidic networks are being rapidly deployed in academia and industry for a vast spectrum of applications, ranging from molecular biology to quantum physics. Current design paradigm for microfluidic layouts is typically based on numerical modeling, which is not suitable for rapid prototyping nor parameter driven design. Here, we utilize the hydraulic-electric circuit analogy to propose a circuit analysis methodology and an open-source framework for a parameter-guided design of integrated microfluidic layouts. We provide a method with which a user can intuitively define the circuit’s constraints and an algorithm which optimizes the hydraulic layout according to physical constraints. Our algorithm supports valves-integrated design and provides a simulation framework that describes fluid flow with different valves configuration.

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van Staden, Ruben, Johannes A. Delport, Johannes A. Coetzee, and Coenrad J. Fourie. "Layout versus Schematic with Design/Magnetic Rule Checking for Superconducting Integrated Circuit Layouts." In 2019 IEEE International Superconductive Electronics Conference (ISEC). IEEE, 2019. http://dx.doi.org/10.1109/isec46533.2019.8990956.

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Yuan, Zhaohui, Shilei Sun, and Gaofeng Wang. "Recognizing Geometric Path from Polygon-Based Integrated Circuit Layout." In 2008 Fifth IEEE International Symposium on Embedded Computing (SEC). IEEE, 2008. http://dx.doi.org/10.1109/sec.2008.22.

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Po Fu Chou, Chun Ming Tsai, and Yu Hsiang Shu. "Layout debugging demonstration by FIB circuit edit." In 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010). IEEE, 2010. http://dx.doi.org/10.1109/ipfa.2010.5531976.

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Reports on the topic "Integrated circuit layout"

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Ahmed, Mohammad. Early Layout Design Exploration in TSV-based 3D Integrated Circuits. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.5509.

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