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1

Harter, Andrew. Three-dimensional integrated circuit layout. Cambridge: Cambridge University Press, 1991.

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2

Harter, Andrew. Three-dimensional integrated circuit layout. Cambridge: Cambridge University Press, 2009.

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3

inc, Motorola, ed. Introduction to integrated-circuit layout. Englewood Cliffs, NJ: Prentice-Hall, 1985.

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4

Lengauer, T. Combinatorial algorithms for integrated circuit layout. Stuttgart: B.G. Teubner, 1990.

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5

Lengauer, Thomas. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1990. http://dx.doi.org/10.1007/978-3-322-92106-2.

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6

Lengauer, Thomas. Combinatorial algorithms for integrated circuit layout. Chichester: Wiley, 1990.

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7

Hsu, Chi-Ping. Signal routing in integrated circuit layout. Ann Arbor, Mich: UMI Research Press, 1986.

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8

Lengauer, T. Combinatorial Algorithms for Integrated Circuit Layout. Wiesbaden: Vieweg+Teubner Verlag, 1992.

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9

Lin, Chieh. Mixed-signal layout generation concepts. Boston, MA: Kluwer Academic Publishers, 2004.

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10

Lin, Chieh. Mixed-signal layout generation concepts. Boston: Kluwer Academic Publishers, 2003.

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11

Wong, D. F. Algorithmic aspects of VLSI circuit layout. Urbana, Ill: Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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12

Hastings, Alan. The art of analog layout. Upper Saddle River, NJ: Prentice Hall, 2001.

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13

Majid, Sarrafzadeh, and Lee D. T, eds. Algorithmic aspects of VLSI layout. Singapore: World Scientific, 1993.

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14

Bing, Lu. Layout optimizations in VLSI designs. Dordrecht: Kluwer Academic Publishers, 2001.

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15

Bexten, Volker Meyer zu. User-controlled layout synthesis for analog integrated circuits. Aachen: Verlag Shaker, 1994.

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16

Baker, R. Jacob. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1998.

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17

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. New York: IEEE Press, 2005.

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18

1960-, Li Harry W., and Boyce David E. 1940-, eds. CMOS circuit design, layout, and simulation. New York: IEEE Press, 1997.

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19

Institute of Electrical and Electronics Engineers., ed. CMOS circuit design, layout, and simulation. 2nd ed. Piscataway, NJ: IEEE Press, 2008.

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20

Lampaert, Koen. Analog layout generation for performance and manufacturability. Boston: Kluwer Academic, 1999.

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21

Ponchak, George E. Coplanar waveguide EEsoF MICAD macros make circuit layout easy. [Washington, DC]: National Aeronautics and Space Administration, 1991.

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22

Tan, Cher Ming. Electromigration Modeling at Circuit Layout Level. Singapore: Springer Singapore, 2013.

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23

Sapatnekar, Sachin S. Design automation for timing-driven layout synthesis. Boston: Kluwer Academic Publishers, 1993.

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24

Yu, Meng-Lin. Automatic random logic layout synthesis: A module generator approach. Urbana, Ill: Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1986.

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25

Weatherhogg, Ian R. Design of an analogue transmission line driver circuit and software development for analogue integrated circuit layout. Salford: University of Salford, 1990.

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26

Bushnell, Michael L. Design automation: Automated full-custom VLSI layout using the ULYSSES design environment. Boston: Academic Press, 1988.

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27

Amos, Duncan. Make Your Own PCBs with EAGLE: From Schematic Designs to Finished Boards. New York: McGraw-Hill Education, 2017.

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28

J, Alpert Charles, Mehta Dinesh P, and Sapatnekar Sachin S. 1967-, eds. Handbook of algorithms for physical design automation. Boca Raton: CRC Press, 2009.

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29

Khatri, Sunil P. Cross-talk noise immune VLSI design using regular layout fabrics. Boston: Kluwer Academic, 2001.

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30

J, Alpert Charles, Mehta Dinesh P, and Sapatnekar Sachin S. 1967-, eds. Handbook of algorithms for physical automation. Boca Raton: CRC Press, 2009.

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31

Sarrafzadeh, Majid. Modern placement techniques. Boston: Kluwer Academic, 2003.

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32

Hastings, Alan. The art of analog layout. Beijing: Tsinghua University Press, 2004.

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33

Farsaei, Ahmadreza. Introduction to Layout Design and Automation of Photonic Integrated Circuits. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-25288-4.

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34

Lampaert, Koen. Analog Layout Generation for Performance and Manufacturability. Boston, MA: Springer US, 1999.

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35

Uyemura, John P. Chip design for submicron VLSI: CMOS layout and simulation. Ottawa: Thomson, 2004.

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36

Ravikumār, C. P. Parallel methods for VLSI layout design. Norwood, N.J: Ablex, 1996.

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37

Martins, Ricardo M. F. Generating Analog IC Layouts with LAYGEN II. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013.

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38

Graeb, Helmut E. Analog Layout Synthesis: A Survey of Topological Approaches. Boston, MA: Springer Science+Business Media, LLC, 2011.

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39

Lau, Hok-Chan. An expert system for trimming and forming tool set layout for integrated circuits (IC). [s.l: The Author], 1992.

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40

Harter, A. C. Three-Dimensional Integrated Circuit Layout. Cambridge University Press, 2011.

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41

Harter, A. C. Three-Dimensional Integrated Circuit Layout. Cambridge University Press, 2010.

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42

Layout Techniques for Integrated Circuit Designers. Artech House, 2022.

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43

Electromigration Modeling at Circuit Layout Level. Springer Verlag, Singapore, 2013.

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44

Saint, Judy, and Christopher Saint. IC Mask Design: Essential Layout Techniques. McGraw-Hill Professional, 2002.

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45

Hastings, Alan, and Roy Alan Hastings. The Art of Analog Layout. Prentice Hall, 2000.

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46

Algorithmic Aspects of VLSI Layout. World Scientific Publishing Co Pte Ltd, 1993.

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47

Algorithmic Aspects of VLSI Layout. World Scientific Publishing Co Pte Ltd, 1993.

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48

Baker, R. Jacob. Cmos: Circuit Design, Layout, and Simulation. Wiley & Sons, Incorporated, John, 2010.

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49

Baker, R. Jacob. Cmos: Circuit Design, Layout, and Simulation. Wiley & Sons, Incorporated, John, 2019.

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50

Baker, R. Jacob. Cmos: Circuit Design, Layout, and Simulation. Wiley & Sons, Incorporated, John, 2019.

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