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Journal articles on the topic 'Integrated circuit layout'
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Wei, Yiding, Jun Liu, Dengbao Sun, Guodong Su, and Junchao Wang. "From Netlist to Manufacturable Layout: An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits." Symmetry 15, no. 6 (June 16, 2023): 1272. http://dx.doi.org/10.3390/sym15061272.
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Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.
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Kasprowicz, Dominik, and Maria Hayder. "Net-Shape-Based Automated Detection of Integrated-Circuit Layout Plagiarism." Electronics 10, no. 24 (December 20, 2021): 3181. http://dx.doi.org/10.3390/electronics10243181.
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Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in industry. A procedure was proposed that compares IC layouts based on the physical representation of particular electrical nets, i.e., on the shape of the features drawn on conducting layers (metals and polysilicon). At the heart of this method is the Needleman–Wunsch algorithm, used for decades in tools aligning sequences of amino acids or nucleotides. Here, it is used to quantify the visual similarity of nets within the pair of layouts being compared. The method was implemented in Python and successfully used to identify clusters of similar layouts within two pools of designs: one composed of logic gates and one containing operational transconductance amplifiers.
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Indrusiak, Leandro Soares, and Ricardo Augusto da Luz Reis. "3D integrated circuit layout visualization using VRML." Future Generation Computer Systems 17, no. 5 (March 2001): 503–11. http://dx.doi.org/10.1016/s0167-739x(00)00036-4.
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Maris Ferreira, Pietro, Emilie Avignon-Meseldzija, Philippe Bénabès, and Francis Trélin. "Surface versus Performance Trade-offs: A Review of Layout Techniques." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–16. http://dx.doi.org/10.29292/jics.v17i1.589.
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Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.
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Vania Agata and Rr. Aline Gratika Nugrahani. "HAK DESAIN TATA LETAK SIRKUIT TERPADU PADA IMPLEMENTASI ALGORITMA ENKRIPSI BC3 DI INDONESIA." Reformasi Hukum Trisakti 6, no. 2 (May 17, 2024): 703–14. http://dx.doi.org/10.25105/refor.v6i2.19719.
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Integrated circuit layout design (DTLST) is one of the relatively new forms of intellectual property, especially in the context of Industrial Property Rights. Law No. 32 of 2000 regulates the layout design of integrated circuits. The first DTLST certificate was granted by DJKI Kemenkhumham in 2018 with certificate number IDL000000001 to Dr. Eng. Sarwono Sutikno and team. The problem formulation in this article is how the legal protection process of Layout Design of BC3 Encryption Algorithm Implementation on Hardware with DTLST Number IDL000000001 according to Law No. 32 of 2000 concerning DTLST and whether that design has qualified as an Integrated Circuit Layout Design. The research uses normative legal research methods, with secondary and primary data. Based on the results of the study, the Layout Design of BC3 Encryption Algorithm Implementation on Hardware has protection for 10 years since October 30th, 2018, where the protection is obtained from the date of acceptance because no commercial exploitation is carried out. The conclusion is that The Layout Design of BC3 Encryption Algorithm Implementation on Hardware is a work that has passed the checking process by DJKI, where this design has passed and meets the originality requirements.
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Guang, Yang, Bin Yu, and Huang Hai. "Design of a High Performance CMOS Bandgap Voltage Reference." Advanced Materials Research 981 (July 2014): 90–93. http://dx.doi.org/10.4028/www.scientific.net/amr.981.90.
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Bandgap voltage reference, to provide a temperature and power supply insensitive output voltage, is a very important module in the analog integrated circuits and mixed-signal integrated circuits. In this paper, a high performance CMOS bandgap with low-power consumption has been designed. It can get the PTAT (Proportional to absolute temperature) current, and then get the reference voltage. Based on 0.35μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that , when the temperature changes from -40 to 80 °C, the proposed circuit’s reference voltage achieve to 1.2V, temperature coefficient is 3.09ppm/°C. Adopt a series of measures, like ESD protection circuit, in layout design. The ultimately design through the DRC and LVS verification, and the final layout size is 700μm * 560μm.
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Fourie, Coenrad J., and Kyle Jackman. "High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout." Journal of Physics: Conference Series 2323, no. 1 (August 1, 2022): 012034. http://dx.doi.org/10.1088/1742-6596/2323/1/012034.
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Abstract Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.
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Gusmão, António, Pedro Alves, Nuno Horta, Nuno Lourenço, and Ricardo Martins. "Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization." Electronics 12, no. 1 (December 27, 2022): 110. http://dx.doi.org/10.3390/electronics12010110.
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Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an “optimal” floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization processes with several constraints; or placement retargeting from legacy designs/templates, which rely heavily on legacy layout data. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover the different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, proximity, and symmetry island constraints are formulated for the first time in the literature, and an unsupervised loss function is used for the artificial neural network model to learn how to generate placements that follow them. The use of a deep learning model makes push-button speed placement generation possible, additionally, as only sizing data are required for its training, it discards the need to acquire legacy layouts containing insights into this vast set of, often neglected, constraints. The model is ultimately used to produce floorplans from scratch at push-button speed for real state-of-the-art analog structures, including technology nodes not used for training. A case-study comparison with a floorplan design made by a human-expert presents improvements in the fulfillment of every constraint, reaching an overall improvement of around 70%, demonstrating the approach’s value in placement design.
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Русанов, А. В., Л. В. Сопина, and А. В. Бунина. "BANDGAP REFERENCE VOLTAGE SOURCE FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 19, no. 4 (September 7, 2023): 71–76. http://dx.doi.org/10.36622/vstu.2023.19.4.009.
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предложены два сложнофункциональных (СФ/IP) блока операционных усилителей (ОУ), построенных на n-канальной и р-канальной дифференциальных парах. ОУ являются универсальными блоками, на основе которых можно построить множество различных электронных узлов. В настоящее время ОУ получили широкое применение как в виде отдельных чипов, так и в виде IP-блоков в составе более сложных интегральных схем. Разработанные IP-блоки ОУ предназначены для применения в интегральных схемах линейных стабилизаторов напряжения в качестве усилителей ошибки. В стабилизаторах напряжения усилитель ошибки выполняет ключевую роль, сравнивая опорное напряжение с выходным (или частью выходного) напряжением, и управляет проходным элементом для обеспечения этого равенства. Представлены описание электрических схем усилителей, основные электрические характеристики, результаты моделирования, указаны особенности разработки топологии интегральной схемы. ОУ разработаны на базе отечественного технологического процесса с проектными нормами 3 мкм. Разработка схемы и топологии проводилась в специализированной системе автоматизированного проектирования интегральных схем. Для моделирования схемы использовались сертифицированные математические модели полупроводниковых приборов. Разработанные топологии ОУ прошли верификацию, состоящую из проверки соблюдения проектных норм (Design rule check, DRC), восстановления электрической схемы из топологии и сравнения топологии с исходной схемой (Layout vs Schematic, LVS) the article proposes two IP blocks of operational amplifiers (op-amps) built on n-channel and p-channel differential pairs. Op-amps are universal blocks on the basis of which you can build many different electronic devices. Currently, op amps are widely used, both in the form of individual chips and as IP blocks as part of more complex integrated circuits. The developed IP blocks are intended for use in integrated circuits of linear voltage stabilizers as error amplifiers. In voltage regulators, the error amplifier plays a key role by comparing the reference voltage to the output (or part of the output voltage) voltage and drives the pass element to ensure this equality. The description of the electrical circuits of amplifiers, the main electrical characteristics, the results of modeling are presented, the features of the development of the integrated circuit topology are indicated. The op amps are developed on the basis of the domestic BiCMOS technological process with design standards of 3 µm. The development of the scheme and topology was carried out in a specialized system for automated design of integrated circuits. To model the circuit, certified mathematical models of semiconductor devices were used. The developed layouts of the op-amp have passed verification, consisting of checking compliance with design standards (Design rule check, DRC), restoring the electrical circuit from the layout and comparing the layout with the original circuit (Layout vs Schematic, LVS)
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Qiu, Tian. "Application and possibility of machine learning in integrated circuit design." Applied and Computational Engineering 6, no. 1 (June 14, 2023): 60–66. http://dx.doi.org/10.54254/2755-2721/6/20230457.
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Artificial Intelligence has had an impact on the field of integrated circuits. Artificial Intelligence technology is gradually replacing the traditional methodology of implementing Integrated Circuit tasks, which consumes a lot of time, funding, and labor. Traditionally, electronic products, like chips, which consist of a large number of circuits, were very slow and costly to process, because it was done by humans. The engineers have to design the layout, carry out operations, verify, and test the circuits, and this is actually extremely inefficient and expensive. However, with the help of Artificial Intelligence technology, efficiency can be greatly improved. The algorithms of Artificial Intelligence to a large extent, accelerated the process of designing, detecting, and maintaining the Integrated Circuit. Nowadays, many companies are applying Artificial Intelligence to upgrade their own products. Machine Learning is one of the main branches of Artificial Intelligence, and its powerfulness has provided a lot of help in the Integrated Circuit tasks. This paper discussed and analyzed the application and possibility of machine learning specifically in Integrated Circuit design activities through literature review and data research.
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Nazhif Ali Murtadho. "Perlindungan Hukum Terhadap Desain Tata Letak Sirkuit Terpadu Ditinjau dari Perspektif Pidana Dalam Hukum Positif." Jurnal Hukum Bisnis 2, no. 1 (January 19, 2024): 1–21. http://dx.doi.org/10.37606/j-kumbis.v2i1.135.
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The main issues in Intellectual Property Rights are regarding legal protection, because Intellectual Property Rights are experiencing rapid development. Because IPR is exclusively owned by the creator and the legal protection prevents violations of Intellectual Property Rights by other parties who are not authorized by criminal sanctions. Indonesia has ratified the TRIPs Agreement, through Law No. 7 of 1994 and the issuance of Law Number 32 of 2000 concerning Layout Design of Integrated Circuits that are able to protect as well as secure and enforce legal protection oh the rights of creators in this case are the exclusive. Rights of every person (designer). By using normative methods with data collection techniques through literature studies to examine primary legal materials including legislation, secondary legal materials include expert opinions. DTLST according to article 1 paragraph (2) is the creation of a three-dimensional layout design of various active components and partly or wholly related in an integrated unit, 3D circuit layout is to prepare an integrated circuit. And the term of DTLST protection is 10 years from the date of registration.
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Musa, Wahab, Sri Wahyuni Dali, and Ade Irawaty Tolago. "Design of Digital Parity Generator Layout Using 0.7 micron Technology." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 5 (October 1, 2018): 3550. http://dx.doi.org/10.11591/ijece.v8i5.pp3550-3559.
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The proposed digital parity generator circuit is an integrated circuit functions to detect data errors at the transmitter end, and check it at the receiving end. In digital communications, the digital messages are transmitted in the form of 1’s and 0’s between two points. It is an error free if both are the same. The purpose of this research is to implement a design method of digital parity generator layout with 0.7 micron process technology ECPD07 from Tanner Tools. Layout design starts from making schematic circuit, test function and make a layout. Next, check the layout results in terms of design rules and verify the desired functionality gradually. The results show that the circuit has functioned well as an odd parity generator. The simulation results obtained with loads CL = 25 fF, tpLH = 2nS and tpHL = 1.46 nS indicate that tp = 1.73nS or operating frequency of 578 MHz. The integrated digital parity generator circuit using transmission gate has a size of 14758 um2 (78.5 um x188 um), consisting of 74 gates.<br /><br />
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Gusmão, António, Rafael Vieira, Nuno Horta, Nuno Lourenço, and Ricardo Martins. "Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation." Electronics 11, no. 23 (November 29, 2022): 3964. http://dx.doi.org/10.3390/electronics11233964.
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The layout design of analog integrated circuits has been defying all automation attempts, and it is still primarily a handcrafting process carried by circuit designers on traditional layout editing frameworks. This paper presents a toolbox based on deep learning techniques and a sturdy graphical user interface to assist designers during that process. The underlying mechanism of this toolbox relies on a simple pairwise device interaction circuit description, i.e., the circuits’ topological constraints, to propose valid floorplan solutions for block-level structures, including topologies and deep nanometer technology nodes not used for its training, at push-button speed. Despite its automatic functionalities, the toolbox is focused on explainable artificial intelligence, involving the designer in the synthesis flow via filtering and editing options over the candidate floorplan solutions. This constant state of human-machine feedback environment turns the designer aware of the impact of each device’s position change and inherent tradeoffs while suggesting subsequent moves, ultimately increasing the designers’ productivity in this time-consuming and iterative task. Finally, the toolbox is shown to instantly generate floorplans with similar or better constraint fulfilment than human designed solutions for state-of-the-art analog circuit blocks.
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Atallah, Mikhail J., and Susanne E. Hambrusch. "An assignment algorithm with applications to integrated circuit layout." Discrete Applied Mathematics 13, no. 1 (January 1986): 9–22. http://dx.doi.org/10.1016/0166-218x(86)90064-8.
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ALARCÓN, EDUARD, GERARD VILLAR, and ALBERTO POVEDA. "CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS." Journal of Circuits, Systems and Computers 13, no. 04 (August 2004): 789–811. http://dx.doi.org/10.1142/s0218126604001714.
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Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.
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Kadlubowski, L. A., and P. Kmon. "Multichannel integrated circuit for time-based measurements in 28 nm CMOS." Journal of Instrumentation 19, no. 02 (February 1, 2024): C02004. http://dx.doi.org/10.1088/1748-0221/19/02/c02004.
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Abstract This paper discusses the application-specific integrated circuit prototype dedicated to readout of hybrid pixel X-ray detectors. The circuit is fabricated in 28 nm CMOS technology and occupies 1.1 × 1.1 mm2 of silicon area. Each of 8 × 4 pixels present in the prototype includes an analog front-end and a digital block with two ring oscillators and their supporting circuits. The circuit can operate in single-photon counting mode or time-based measurement mode. The paper discusses in detail the design decisions that influenced the final in-pixel ring oscillator architecture and layout. Measurement results are presented which demonstrate the performance of ring oscillators as well as regular operating modes of the chip: single photon counting and time-over-threshold measurement.
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Wu, Chan-Liang, and Chih-Wen Lu. "Mitigating the Effects of Design for Manufacturability on Design Iteration Cycles in Advanced Integrated Circuit Design." Electronics 12, no. 24 (December 13, 2023): 4993. http://dx.doi.org/10.3390/electronics12244993.
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In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.
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SENTHILPARI, C., K. DIWAKAR, and AJAY KUMAR SINGH. "LOW POWER, LOW LATENCY, HIGH THROUGHPUT 16-BIT CSA ADDER USING NONCLOCKED PASS-TRANSISTOR LOGIC." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 581–96. http://dx.doi.org/10.1142/s0218126609005277.
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As the CMOS technology continues to scale to achieve higher performance, power dissipation and robustness to leakage and, process variations are becoming major obstacles for circuit design in the nanoscale technologies. Due to increased density of transistors in integrated circuits and higher frequencies of operation, power consumption, propagation delay, PDP, and area is reaching the lower limits. We have designed 16-bit adder circuit by Carry-Select Adder (CSA) using different pass-transistor logic. The adder cells are designed by DSCH3 CAD tools and layout are generated by Microwind 3 VLSI CAD tools. Using CSA technique, the power dissipation, PDP, area, transistor count, are calculated from the layout cell of proposed 16-bit adder for Ultra Deep Submicron feature size of 120, 90, 70, and 50 nm. The UDSM signal parameters are calculated such as signal to noise ratio (SNR), energy per instruction (EPI), Latency, and throughput using layout parameter analysis of BSIM 4. The simulated results show that the CPL is dominant in terms of power dissipation, propagation delay, PDP, and area among the other pass gate logics. Our CPL circuit dominates in terms of EPI, SNR, throughput, and latency in signal parameters analysis. The proposed CPL adder circuit is compared with reported results and found that our CPL circuit gives better performance.
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Weaver, D. J., J. R. A. Cleaver, L. Avery, and H. Ahmed. "Substrate dopant imaging for layout reconstruction of integrated-circuit layers." Microelectronic Engineering 61-62 (July 2002): 1063–67. http://dx.doi.org/10.1016/s0167-9317(02)00583-x.
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VAHEDI, HALEH, STEFANO GREGORI, and RADU MURESAN. "ON-CHIP POWER-EFFICIENT CURRENT FLATTENING CIRCUIT." Journal of Circuits, Systems and Computers 18, no. 03 (May 2009): 565–79. http://dx.doi.org/10.1142/s0218126609005332.
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This paper presents a control circuit which regulates the current consumption of integrated circuits using current injection and voltage scaling techniques. The control circuit can be integrated with smart cards as a countermeasure against power analysis attacks and electromagnetic emanation analysis attacks. We have designed the proposed circuit in 0.18 μm CMOS technology at 1.8 V power supply. The simulation results show that the circuit controls the current through the power supply pin of a model of a smart card microcontroller and attenuates the peak-to-peak current variations by 95%. The power dissipation overhead of the control circuit is less than 20% of the original power dissipation of the smart card microcontroller. Comparing the layout area of the proposed circuit with that of an ASIC 3-DES algorithm in the same technology shows that the control circuit only constitutes 4% of the cryptographic processor. The proposed circuit proves to be especially useful for smart cards and small portable devices, where power dissipation and chip area are critical.
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Mohan, Navya, and J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model." Cryptography 7, no. 1 (January 28, 2023): 4. http://dx.doi.org/10.3390/cryptography7010004.
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The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.
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Ferreira Pontes, Matheus, Clayton Farias, Rafael Schvittz, Paulo Butzen, and Leomar Da Rosa Jr. "Survey on Reliability Estimation in Digital Circuits." Journal of Integrated Circuits and Systems 16, no. 3 (December 31, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i3.568.
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The aggressive technology scaling has significantly affected the circuit reliability. The interaction of environmental radiation with the devices in the integrated circuits (ICs) may be the dominant reliability aspect of advanced ICs. Several techniques have been explored to mitigate the radiation effects and guarantee a satisfactory reliability levels. In this context, estimating circuit radiation reliability is crucial and a challenge that has not yet been overcome. For decades, several different methods have been proposed to provide circuit reliability. Recently, the radiation effects have been more faithfully incorporated in these strategies to provide the circuit susceptibility more accurately. This paper overviews the current trend for estimating the radiation reliability of digital circuits. The survey divides the approaches into two abstraction levels: (i) gate-level that incorporate the layout information and (ii) circuit-level that traditionally explore the logic circuit characteristic to provide the radiation susceptibility of combinational circuits. We also present an open-source tool that incorporates several previously explored methods. Finally, the actual research aspects are discussed, providing the newly emerging topic, such as selective hardening and critical vector identification.
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Alimisis, Vassilis, Christos Dimas, and Paul P. Sotiriadis. "A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier." Electronics 13, no. 5 (February 28, 2024): 921. http://dx.doi.org/10.3390/electronics13050921.
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This study introduces a low-power analog integrated Euclidean distance radial basis function classifier. The high-level architecture is composed of several Manhattan distance circuits in connection with a current comparator circuit. Notably, each implementation was designed with modularity and scalability in mind, effectively accommodating variations in the classification parameters. The proposed classifier’s operational principles are meticulously detailed, tailored for low-power, low-voltage, and fully tunable implementations, specifically targeting biomedical applications. This design methodology materialized within a 90 nm CMOS process, utilizing the Cadence IC Suite for the comprehensive management of both the schematic and layout design aspects. During the verification phase, post-layout simulation results were meticulously cross-referenced with software-based classifier implementations. Also, a comparison study with related analog classifiers is provided. Through the simulation results and comparative study, the design architecture’s accuracy and sensitivity were effectively validated and confirmed.
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Jabri, Marwan A. "Building Rectangular Floorplans–A Graph Theoretical Approach." VLSI Design 1, no. 2 (January 1, 1994): 99–111. http://dx.doi.org/10.1155/1994/46871.
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Rectangular dualisation is a technique used to generate rectangular topologies for use in top-down floorplanning of integrated circuits. In order for this technique to be used in a floorplanning system, its input, the connectivity graph representing an integrated circuit has to fulfill a number of conditions. This paper presents an efficient algorithm that transforms an arbitrary connected graph, representing an integrated circuit, into another graph that is guaranteed to fulfill these conditions and to admit rectangular duals. Effectively, the algorithm solves the global routing problem by using three techniques: passthrough, wiring blocks and collapsed wiring blocks. Resulting floorplans may be passed to a chip assembler and detailed router package to complete the layout. This paper also introduces a novel technique to transform a tree of biconnected sub-graphs into a block neighbourhood graph that is a path.
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Dzahini, D., M. Zeloufi, and L. Gallin-Martel. "A low crosstalk 768-channel of 14-bit analog to digital converters for high resolution array of detectors." Journal of Instrumentation 19, no. 05 (May 1, 2024): C05032. http://dx.doi.org/10.1088/1748-0221/19/05/c05032.
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Abstract This paper presents the design and measurement results of a 768-channel of a 14-bit analog to digital converters. Each sampling channel is equivalent to a pitch of only 8.5 μm with a possible sampling rate from 40 KS/s up to 100 KS/s. Test results show crosstalk of just +/-1 LSB. The circuit architecture and layout structure make it scalable to an exceptionally large format of detectors beyond 1000 channels. The circuit is designed to be used as a side element for multi-channel readout systems or as an IP for transfer to very dense integrated circuits.
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Wang, Jun Ping, Su Yang Qi, and Dan Xu. "A Study on CIF-to-BMP Format Transformation Algorithm." Advanced Materials Research 712-715 (June 2013): 2510–13. http://dx.doi.org/10.4028/www.scientific.net/amr.712-715.2510.
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In the prediction and improvement of integrated circuit yield, it needs to convert CIF file to BMP file in order to calculate the critical area accurately and optimize the subsequent layout, at the same time, the image format of layout is the foundation of random defects hot spot detection. Firstly, the structures of CIF file and BMP file are studied, and various commands of CIF are deeply analyzed. Secondly, we design the algorithm that is based on the primitives are converted into BMP according to the representation of four basic primitives (rectangle, polygon, circularity, line with width) in CIF layout. Finally, we realize the algorithm of the whole CIF files is converted into BMP files. It is simple, conversion accuracy is high, more importantly, laid the foundation for the improvement of integrated circuit yield, and use C++ language to realize the CIF files conversion software based on the algorithm.
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Cho, Minji, Heechul Lee, and Doohyung Woo. "Nonuniformity-Immune Read-In Integrated Circuit for Infrared Sensor Testing Systems." Electronics 9, no. 10 (October 1, 2020): 1603. http://dx.doi.org/10.3390/electronics9101603.
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In this study, a novel IR projector driver that can minimize nonuniformity in electric circuits, using a dual-current-programming structure, is proposed to generate high-quality infrared (IR) scenes for accurate sensor evaluation. Unlike the conventional current-mode structure, the proposed system reduces pixel-to-pixel nonuniformity by assigning two roles (data sampling and current driving) to a single transistor. A prototype of the proposed circuit was designed and fabricated using the SK-Hynix 0.18 µm CMOS process, and its performance was analyzed using post-layout simulation data. It was verified that nonuniformity, which is defined as the standard deviation divided by the mean radiance, could be reduced from 21% to less than 0.1%.
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Ho, Hong Fa. "Reading Process of Integrated Circuit Layout Debugging: Evidence from Eye Movements." Advanced Materials Research 787 (September 2013): 855–60. http://dx.doi.org/10.4028/www.scientific.net/amr.787.855.
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Finding bugs in CMOS Integrated Circuit (IC) layouts is a basic skill for IC design engineers and students alike. The reading process of finding bugs is the basis for learning and teaching in electronic engineering. In this pilot study, eye-movement data was used in analyzing the reading process and nature of five participants (N=5) finding bugs in CMOS layouts. Data analysis of eye movements was based on nine types of ROI (Region of Interest). The ANOVA analysis of eye movements was analyzed. The findings of experimental results included that there were significant differences among the number of fixations of nine types of ROIs. The findings suggest how learners could read the bugged IC layouts effectively and efficiently.
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Ahn, Wonkee, Dereje Agonafer, and Shlomo Novotny. "Methodology for an Integrated (Electrical/Mechanical) Design of PWBA." Journal of Electronic Packaging 126, no. 4 (December 1, 2004): 524–27. http://dx.doi.org/10.1115/1.1827268.
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This paper describes a general methodology of how electrical circuit design data are mapped into an intermediate analyzable representation that supports the information requirement of several thermomechanical analyses, including product optimization/idealization. This paper describes other issues encountered, such as how to integrate product data that spans more than one tool, how to modify and add analysis data necessary during analysis, and how to use data stored in the analysis module from different programing environments. The advantage this process offers is also described by considering a PWBA (Printed Wiring Board Assembly) design, such as layout and layup in an electrical design system.
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Le Gouguec, Thierry, Najib Mahdi, Stéphane Cadiou, Cédric Quendo, Erich Schlaffer, Walter Pessl, and Alain Lefevre. "Modeling up to 45 GHz of coupling between microvias and PCB cavities considering several boundary conditions." International Journal of Microwave and Wireless Technologies 8, no. 3 (February 19, 2016): 421–30. http://dx.doi.org/10.1017/s1759078716000192.
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The recent developments in electronic cards such as the network equipment are characterized by the miniaturization of the board size and the increasing complexity of the layout. Because of these requirements, multi-layered printed circuit boards are commonly used and vias connecting signal lines on different layers, or integrated circuit devices to power and ground planes, are frequently used and often essential. However, a via is not an ideal transmission line. Besides, it creates discontinuities at high frequencies leading to high insertion loss degradation of signal which limits the performances of integrated circuit and systems. In this paper, the impacts of coupling between via and parallel-plates cavity on the response of microwave integrated devices are highlighted in the first part. Then, to describe the intrinsic interaction between the via transition and parallel-plate modes, the notion of parallel-plates matrix impedances is presented and new boundary conditions like open or plated through holes shielded boundaries of the cavities are introduced. Then, using this physics-based model, an intuitive equivalent circuit has been developed. Finally, the proposed approach and the equivalent circuits were validated by using comparisons with electromagnetic simulations and measurements in different scenarios.
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TAKAHASHI, Yuichiro. "No. 6: On “Act Concerning the Circuit Layout of a Semiconductor Integrated Circuit (Maskwork Law)”." Journal of Information Processing and Management 46, no. 8 (2003): 509–17. http://dx.doi.org/10.1241/johokanri.46.509.
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Yesil, Abdullah. "Floating Memristor Employing Single MO-OTA with Hard-Switching Behavior." Journal of Circuits, Systems and Computers 28, no. 02 (November 12, 2018): 1950026. http://dx.doi.org/10.1142/s0218126619500269.
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In this paper, we presented Multi-Output Operational Transconductance Amplifier (MO-OTA)-based floating memristor emulator circuit. The designed memristor circuit has only one MO-OTA and one grounded capacitor which is attractive for an integrated circuit. It does not consist of any multiplication circuit block to obtain nonlinear behavior of memristor. It is difficult to obtain the hard-switching voltage–current relationship than the smooth-switching voltage–current relationship of memristor but we obtained hard-switching voltage–current characteristics using single floating memristor circuit. The complete memristor circuit is laid by using Cadence Environment using TSMC 0.18[Formula: see text][Formula: see text]m process parameters. The layout area of MO-OTA occupies an area of 34[Formula: see text][Formula: see text]m [Formula: see text] 14[Formula: see text][Formula: see text]m. Its post-layout simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner and radical temperature changes. All post-layout simulations agree well with theoretical analyses. As application examples, different connections such as serial, parallel and single of memristor emulator are investigated to test its connectivity.
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Palumbo, Gaetano, and Giuseppe Scotti. "A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route." Journal of Low Power Electronics and Applications 11, no. 4 (October 28, 2021): 42. http://dx.doi.org/10.3390/jlpea11040042.
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This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art.
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Movchan, Andrey K., Eugeniy V. Lomakov, Eugeniy V. Rogozhnikov, and Kirill V. Savenko. "Investigation a method for measuring blood pressure with a capacitive integrated sensor." Radioelectronics. Nanosystems. Information Technologies. 16, no. 1 (March 14, 2024): 43–52. http://dx.doi.org/10.17725/j.rensit.2023.16.043.
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A method of wireless measurement of blood flow parameters is investigated using an implantable passive capacitive sensor and an external reader. This device is designed to measure the parameters of blood flow in the human body, through the installation of a passive capacitive sensor and inductive coupling with an external reader device. The method of wireless measurement is based on the connection of resonant circuits at an operating frequency of 10 MHz. The mathematical calculation of the device circuit is presented. The result of the calculation was the dependence of the output voltage of the external reader on the change of capacitance in the implanted passive sensor. The values of the potential sensitivity of the device are obtained. The manufactured layout of the device and its parameters are presented. The mock-up allowed to investigate the dependences of the coupling factor of the circuits when using coils of an external reader of different sizes. Also the measurement of the output voltage of the external reader from the value of the passive sensor capacitance was made. The value of real sensitivity of the device layout was measured.
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Li, Shuo, Nan Pan, Sen Gao, and Lei Li. "Three State Output Module and Digital Switch Circuit Based on Threshold Memristor." Journal of Physics: Conference Series 2395, no. 1 (December 1, 2022): 012021. http://dx.doi.org/10.1088/1742-6596/2395/1/012021.
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Abstract A memristor is a new electronic device with small volumes and small fluctuations. As a two-terminal device, it is mainly characterized by non-volatility and nanoscale characteristic size. Memristors can also calculate and store at the same time, which has a broad application prospect in logic circuits. Traditional integrated circuit technology has been very mature. And CMOS technology has almost reached the limit of physical size. Compared with traditional circuit components, memristor devices are compatible with CMOS circuits with their fast computing speed, low power consumption, and small layout area. A three-state output module based on a threshold memristor is proposed. The structure includes an inverter, a PMOS tube, two NMOS tubes, and two threshold memristors. Compared with the traditional three-state gate which only uses CMOS technology, the circuit area required by the module is smaller and the overall power consumption is lower, which caters to the development trend of portable and low-power electronic devices. Then the digital switch circuit using this module is introduced, which provides a new idea for the data transmission circuit. The circuit and module are simulated and verified by LTspice software.
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Su, Rong Jun. "Environmental Risk Evaluation on Integrated Circuit Industry." Applied Mechanics and Materials 209-211 (October 2012): 1203–6. http://dx.doi.org/10.4028/www.scientific.net/amm.209-211.1203.
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In order to evaluate the environmental risk of integrated circuit industry, a new integrated circuit chip project was taken as an example to be investigated and analyzed. Its engineering features, process flow, risk identification, risk source intensity and measures to prevent risks were proposed. Risk identification shows that main poisonous and harmful chemicals(PHC) are corrosives and antioxidants, flammable gases and liquids and poisonous gases. Transportation, production and storage risk of PHC and potential accidental risk caused by external factors were proposed. Risk source analysis indicates that the probability of damaging and leaking accidents on facilities is 10-1 times/year. In the case of cylinders leakage, leakage rates of SiF4, Cl2 and ClF3 will be 17 g/s, 8 g/s and 8 g/s respectively. Evaporation rates of isopropyl alcohol, HF and HCl acids are 0.09 g/s. 0.38 g/s and 55 g/s respectively. Finally, Overall layout and construction safety measures, safety precautions on dangerous chemical storage and transportation, technology design and automatic control design, and emergency plan to prevent risk accident were also proponed. This work will be helpful for environmental impact assessment on similar industries.
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Lee, Min Su, and Hee Chul Lee. "Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit." IEEE Transactions on Nuclear Science 60, no. 4 (August 2013): 3084–91. http://dx.doi.org/10.1109/tns.2013.2268390.
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Mototaka, Kuribayashi. "Automatic layout design method of wirings in integrated circuit using hierarchical algorithm." Computer Integrated Manufacturing Systems 10, no. 2 (May 1997): 171. http://dx.doi.org/10.1016/s0951-5240(97)84321-2.
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Zhang, Lihong, Rabin Raut, Yingtao Jiang, Ulrich Kleine, and Yoohwan Kim. "A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs." International Journal of Circuit Theory and Applications 33, no. 6 (2005): 487–501. http://dx.doi.org/10.1002/cta.332.
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Petitgirard, Julien, Tony Piguet, Philippe Baucour, Didier Chamagne, Eric Fouillien, and Jean-Christophe Delmare. "Steady State and 2D Thermal Equivalence Circuit for Winding Heads—A New Modelling Approach." Mathematical and Computational Applications 25, no. 4 (October 18, 2020): 70. http://dx.doi.org/10.3390/mca25040070.
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The study concerns the winding head thermal design of electrical machines in difficult thermal environments. The new approach is adapted for all basic shapes and solves the thermal behaviour of a random wire layout. The model uses the nodal method but does not use the common homogenization method for the winding slot. The layout impact can be precisely studied to find different hotspots. To achieve this a Delaunay triangulation provides the thermal links between adjoining wires in the slot. Voronoï tessellation gives a cutting to estimate thermal conductance between adjoining wires. This thermal behaviour is simulated in cell cutting and it is simplified with the thermal bridge notion to obtain a simple solving of these thermal conductances. The boundaries are imposed on the slot borders with Dirichlet condition. Then solving with many Dirichlet conditions is described. Some results show different possible applications with rectangular and round shapes, one ore many boundaries, different limit condition values and different layouts. The model can be integrated into a larger model that represents the stator to have best results.
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LIAO, CHEN, XIAODAO CHEN, and SHIYAN HU. "DISCRETE WAVELET TRANSFORM BASED CIRCUIT LAYOUT FINGERPRINTING USING CHAOTIC SYSTEM." Journal of Circuits, Systems and Computers 21, no. 07 (November 2012): 1250049. http://dx.doi.org/10.1142/s0218126612500491.
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Tight time-to-market pressure requires CAD tools to heavily involve component reuse, or intellectual property (IP) reuse, which imposes intense security concerns on IP protection. For the IP providers, it is critical to protect their products against unauthorized reproduction. Thus, circuit layout fingerprinting becomes quite important which helps the IP providers to detect which user distributes the illegal IPs. However, previous works addressing the circuit fingerprinting all have large area and runtime overhead. In this paper, a novel efficient discrete wavelet transform (DWT)-based key sensitive circuit layout fingerprinting technique using chaotic system is proposed. The new circuit layout fingerprinting technique targets to be applied after placement and routing, while before fabrication. Thus, it only slightly impacts the original design and introduces small runtime overhead as well. To further enhance the security, the chaotic system based on Fibonacci transformation is integrated. The experimental results demonstrate that our chaotic DWT-based technique largely outperforms a median-based technique for various attacks. The chaotic DWT-based technique improves the detection error rate by 68.5% for the gate swapping attack, by 65.8% for the random perturbation attack, by 54.8% for the partition-based perturbation attack and by 54.5% for the combined perturbation attack. In addition, the average wirelength overhead is only 0.0149% compared to the original design and the average runtime overhead is only 6.73 s. These demonstrate the effectiveness of our circuit layout fingerprinting technique.
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Banu, Viorel, Josep Montserrat, Mihaela Alexandru, Xavier Jordá, José Millan, and Philippe Godignon. "Monolithic Integration of Power MESFET for High Temperature SiC Integrated Circuits." Materials Science Forum 778-780 (February 2014): 891–94. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.891.
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This work provides experimental result on fabricated 4H-SiC lateral power MESFET intended to be used in further development of high temperature integrated circuits for power application. The power SiC MESFET device was developed using a planar technology on silicon carbide and P implant isolation technique. Its destination to monolithic integration demands a lateral layout connection topology. The use of quite high doped N type epitaxial layer (1017cm-3) typical for the integrated circuits raises difficulties to keep the leakage current of the Schottky gate in a decent range. Therefore, a hexagonal close loop gate in conjunction with three metal interconnection levels was adopted, thus obtaining a compact lateral MESFET device and avoiding any drain to source parasitic leakage path. Using the tungsten gate MESFETS, the first generation of monolithic integrated lateral power MESFET device was integrated on the same wafer with digital circuits and a voltage reference analog circuit able to operate up to 250C. The temperature range can be next improved by using higher barrier for the gate contact.
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Myderrizi, Indrit, and Ali Zeki. "A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology." Journal of Circuits, Systems and Computers 26, no. 11 (April 17, 2017): 1750182. http://dx.doi.org/10.1142/s0218126617501821.
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With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.
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Alimisis, Vassilis, Nikolaos P. Eleftheriou, Argyro Kamperi, Georgios Gennis, Christos Dimas, and Paul P. Sotiriadis. "General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers." Electronics 12, no. 20 (October 11, 2023): 4211. http://dx.doi.org/10.3390/electronics12204211.
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This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.
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Davydov, D., and S. Obukhov. "PARAMETERIZED SAVINGS HEURISTIC FOR OPTIMIZING INFIELD CABLE ROUTING OF OFFSHORE WIND FARMS." Bulletin of the South Ural State University series "Power Engineering" 21, no. 3 (2021): 66–75. http://dx.doi.org/10.14529/power210308.
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The article discusses an approach to solving the problem of optimizing the routing of infield power cables layout to improve the efficiency and cost-effectiveness of offshore wind farms. Optimization seeks to reduce the total cost of the infield collection system while bearing in mind the constraints including use of sufficiently sized cables and the required absence of cable crossings in the circuit diagram. The problem is a degree-constrained capacitated minimum spanning tree (DCMST) problem with dependent node costs. Search for solu-tion is based on an integrated approach that uses a hybrid optimization algorithm, which combines a parameterized savings heuristic and particle swarm optimization to optimize the parameters of the primary algorithm, ultimately enabling better solutions. Several tests have been performed to compare the constructed circuit diagrams against solutions yielded by other algorithms; tests showed the proposed approach to significantly improve the efficiency of the constructed circuits as demonstrated in a series of tests and evaluated by comparison with other methods, as well as by comparing the efficiency and cost-effectiveness of the optimized routing against the actual layout of the Walney 1 offshore wind farm.
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LAI, Xiaoling, Jian ZHANG, Ting JU, Qi ZHU, and Yangming GUO. "Single event upset reinforcement technology of DICE flip-flop based on layout design." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 40, no. 6 (December 2022): 1305–11. http://dx.doi.org/10.1051/jnwpu/20224061305.
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D flip-flop is the basis of timing logic circuit, and SEMU phenomenon tends to be serious with the integrated circuit process size shrinking to nanometer scale. The anti-SEU ability based on DICE structure for D flip-flop cannot meet the requirements of aerospace engineering. Based on the SEU reinforcement technology of D flip-flop under nano-technology and the SEU mechanism of DICE structure, a layout-level anti-SEU flip-flop design method based on DICE circuit structure is proposed considering the circuit performance, area, power consumption and other resource costs. And then a D flip-flop with SEU resistance is designed by commercial 65 nm process, and the designed flip-flop area is 1.8 times that of commercial structure flip-flop. The function and and radiation simulation results indicate that the establishment time and transmission delay of the flip-flop are equivalent to those of the commercial one, and no SEU occurs under the Ge ion bombardment with the LET threshold of approximately 37 MeV·cm2/mg. The performance of the flip-flop circuit and the ability to resist single particle soft error are excellent. In the anti-radiation ASIC design, the area, wiring resources and timing overhead caused by the reinforcement of the D flip-flop circuit are greatly saved.
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Белявцев, А. В., А. В. Русанов, and Т. С. Шайкина. "RC OSCILLATOR FOR A DOMESTIC TECHNOLOGICAL PROCESS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА 20, no. 1 (April 1, 2024): 45–50. http://dx.doi.org/10.36622/1729-6501.2024.20.1.007.
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предложен сложно-функциональный (СФ/IP) блок RC-генератора, построенный на МОП-транзисторах. Генератор является блоком тактирования для большого числа электронных устройств, не требовательных к стабильности частоты, но чувствительных к размеру. Данный блок предназначен для применения в составе интегральных схем стабилизаторов напряжения. Приведено описание электрической схемы генератора, его основные электрические характеристики и результаты моделирования (зависимости частоты генератора и его тока потребления от температуры и напряжения питания схемы, получены значения нестабильности частоты и зависимость частоты генератора от технологических отклонений, температуры и напряжения питания). Сделан вывод об относительной стабильности характеристик генератора при изменениях внешних параметров и технологических флуктуаций. Приведена топология разработанного СФ блока RC-генератора. Генератор разработан на базе отечественного технологического процесса с проектными нормами 180 нм. Разработка схемы и топологии проводилась в специализированной системе автоматизированного проектирования работ (САПР) интегральных схем. Для моделирования схемы использовались математические модели полупроводниковых приборов, предоставленные фабрикой изготовителем. Топология генератора прошла успешную верификацию на соблюдение проектных норм (Design rule check, DRC) и соответствия топологии исходной схеме (Layout vs. Schematic, LVS) a functional block (IP) of RC oscillator is proposed. The oscillator is a clocking unit for a large number of electronic devices where frequency stability is not required, but small die size is important. This block is intended for use as part of integrated circuits of voltage regulators. The description of the electrical circuit of the oscillator with electrical specs as well as simulation results are presented. We obtained the following characteristics: oscillator frequency and current consumption plot versus temperature and supply voltage, frequency instability due to process, temperature and voltage variations. Then we have considered the relative stability of the oscillator characteristics under changes in external conditions and technological fluctuations. We present the RC oscillator IP block layout. The oscillator is designed in Russian 180 nm CMOS process. The circuit and layout design were carried out in a specialized IC design CAD system. The mathematical models of semiconductor devices provided by the manufacturer were used to simulate our circuit. The oscillator layout has been successfully verified for compliance with design rules (Design rule check, DRC) and comparing the layout with the schematic (Layout vs. Schematic, LVS)
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Jurik, Patrik, Miroslav Sokol, Pavol Galajda, and Milos Drutarovsky. "Analysis and Implementation of Controlled Semiconductor Switch for Ultra-Wideband Radar Sensor Applications." Sensors 23, no. 17 (August 24, 2023): 7392. http://dx.doi.org/10.3390/s23177392.
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All ultra-wideband (UWB) sensor applications require hardware designed directly for their specific application. The switching of broadband radio frequency and microwave signals is an integral part of almost every piece of high-frequency equipment, whether in commercial operation or laboratory conditions. The trend of integrating various circuit structures and systems on a chip (SoC) or in a single package (SiP) is also related to the need to design these integrated switches for various measuring devices and instruments in laboratories, paradoxically for their further development. Another possible use is switching high-frequency signals in telecommunications devices, whether mobile or fixed networks, for example, for switching signals from several antennas. Based on these requirements, a high-frequency semiconductor integrated switch with NMOS transistors was designed. With these transistors, it is possible to achieve higher integration than with bipolar ones. Even though MOSFET transistors have worse frequency characteristics, we can compensate them to some extent with the precise design of the circuit and layout of the chip. This article describes the analysis and design of a high-frequency semiconductor integrated switch for UWB applications consisting of three series-parallel switches controlled by CMOS logic signals. They are primarily intended for UWB sensor systems, e.g., when switching and configuring the antenna MIMO system or when switching calibration tools. The design of the switch was implemented in low-cost 0.35 µm SiGe BiCMOS technology with an emphasis on the smallest possible attenuation and the largest possible bandwidth and isolation. The reason for choosing this technology was also that other circuit structures of UWB systems were realized in this technology. Through the simulations, individual parameters of the circuit were simulated, the layout of the chip was also created, and the parameters of the circuit were simulated with the parasitic extraction and the inclusion of parasitic elements (post-layout simulations). Subsequently, the chip was manufactured and its parameters were measured and evaluated. Based on these measurements, the designed and fabricated UWB switch was found to have the following parameters: a supply current of 2 mA at 3.3 V, a bandwidth of 6 GHz, an insertion loss (at 1 GHz) of −2.2 dB, and isolation (at 1 GHz) of −33 dB, which satisfy the requirements for our UWB sensor applications.
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Patel, Ambresh, and Ritesh Sadiwala. "Performance Analysis of Various Complementary Metaloxide Semiconductor Logics for High Speed Very Large Scale Integration Circuits." SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology 15, no. 01 (January 30, 2023): 91–95. http://dx.doi.org/10.18090/10.18090/samriddhi.v15i01.13.
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The demand for VLSI low voltage high-performance low power systems are increasing significantly. Today's deviceapplications necessitate a system that consumes little power and conserves performance. Recent battery-powered lowvoltagedevices optimize power and high-speed constraints. Aside from that, there is a design constraint with burst-modetype integrated circuits for small devices to scale down. Low voltage low power static CMOS logic integrated circuitsoperate at a slower rate and cannot be used in high performance circuits. As a result, dynamic CMOS logic is used inintegrated circuits because it requires fewer transistors, has lower parasitic capacitance, is faster, and enables pipelinedsystem architecture with glitch-free circuits. It has, however, increased power dissipation. Both types of CMOS circuits withlow power dissipation overcome their own shortcomings.This paper discusses dynamic CMOS logic circuits and their structures. Various logics are also discussed and on the basisof the results obtained, logic which is best suited for designing CMOS logic circuit will be found out. The logic on the basisof structure layout and design which gives best results for high-speed VLSI circuits, is found out.
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Li, Xiangyu, Pengjun Wang, Hao Ye, Haonan He, and Xiaowei Zhang. "Study of a High-Precision Read-Out Integrated Circuit for Bridge Sensors." Micromachines 14, no. 11 (October 29, 2023): 2013. http://dx.doi.org/10.3390/mi14112013.
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Bridge sensors are widely used in military and civilian fields, and their demand gradually increases each year. Digital sensors are widely used in the military and civilian fields. High-precision and low-power analog-to-digital converters (ADCs) as sensor read-out circuits are a research hotspot. Sigma-delta ADC circuits based on switched-capacitor topology have the advantages of high signal-to-noise ratio (SNR), good linearity, and better compatibility with CMOS processes. In this work, a fourth-order feed-forward sigma-delta modulator and a digital decimation filter are designed and implemented with a correlated double sampling technique (CDS) to suppress pre-integrator low-frequency noise. This work used an active pre-compensator circuit for deep phase compensation to improve the system’s stability in the sigma-delta modulator. The modulator’s local feedback factor is designed to be adjustable off-chip to eliminate the effect of process errors. A three-stage cascade structure was chosen for the post-stage digital filter, significantly reducing the number of operations and the required memory cells in the digital circuit. Finally, the layout design and engineering circuit were fabricated by a standard 0.35 μm CMOS process from Shanghai Hua Hong with a chip area of 9 mm2. At a 5 V voltage supply and sampling frequency of 6.144 MHz, the modulator power consumption is 13 mW, the maximum input signal amplitude is −3 dBFs, the 1 Hz dynamic range is about 118 dB, the modulator signal-to-noise ratio can reach 110.5 dB when the signal bandwidth is 24 kHz, the practical bit is about 18.05 bits, and the harmonic distortion is about −113 dB, which meets the design requirements. The output bit stream is 24 bits.